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EEWeb.com INTERVIEW Issue 67

October 9, 2012

Scott Nelson

Senior Vice President of the Memory Business Unit Toshiba America Electronics Components, Inc. Electrical Engineering Community Visit www.eeweb.com

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TABLE OF CONTENTS

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Scott Nelson TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Interview with Scott Nelson - Senior Vice President for the Memory Business Unit

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Featured Products The Evolution of the NAND Flash Interface BY DOUG WONG WITH TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.

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An exploration into the recent improvements to the legacy NAND flash interface that have been made in order to improve the interface speed.

Spectrum Analyzer and High Speed Data: An Odd Couple

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BY MIKE STEINBERGER WITH SISOFT An introduction to the spectrum analyzer and how it can be used to provide valuable insights into clocking, power supply noise and crosstalk in high speed data signals.

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RTZ - Return to Zero Comic

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EEWeb PULSE

Scott

Nelson Toshiba Inc.

Senior Vice President for the Memory Business Unit Toshiba America Electronic Components Inc.

49

EEWeb||Electrical ElectricalEngineering EngineeringCommunity Community EEWeb


.

INTERVIEW What first interested you in electronics? After graduating college, I entered into the aerospace industry, working for Northrop here in Southern California. After several years at Northrop, I made the decision to accept a position with Toshiba in 1986 – making my tenure with the company at 26 years and counting. What interested me in pursuing a career in the electronic industry was the technology – specifically, the technology leadership of Toshiba back in the DRAM days. This industry was relatively young, with what seemed to be endless potential and a full spectrum of exciting challenges. Over the years, I worked my way up through the organization and in 1995, I stepped into my first management role, where I undertook a two-year Six Sigma process improvement assignment and finished that assignment as a director. In 2007 I moved into my current role as Senior Vice President for the Memory Business Unit. What are the major memory products that Toshiba produces? In 1999, Toshiba made a very strategic decision to exit the DRAM business and focus all of our efforts and technology in NAND. Toshiba invented Flash technology—in 1984, we invented NOR flash memory and in 1987, we introduced NAND flash memory at an IEEE meeting. We’ve been very NAND-centric since 2000, and all of our memory products are supported by NAND technology. The NAND process itself is a bit more involved and complicated than its predecessors. For quite awhile, it was a barrier to entry into the market—the ability to manufacture

NAND with a sustainable yield that would be profitable. Toshiba had been in it since its inception, so when the market really took off with digital imaging, we were well prepared. What do you see as the next big direction to improve current NAND products? When Toshiba entered the NAND market, there was really only one type of NAND—single level cell

“We currently offer managed NAND solutions that manage bad block management, wear leveling and ECC, such as eMMC - which can be used in the mobile and gaming space. Another solution is managing ECC with the NAND chip.” (SLC) NAND. More and more, well-suited applications and opportunities came into the market and if we fast forward to where we are today—there are now four grades of NAND on the market, which can be classified as retail, OEM, SSD and the enterprise grade – which requires higher performance and higher

endurance. NAND is adapting and evolving to these applications in these new segments. Of late, NAND is emerging with faster interfaces, thus, Toshiba offers Toggle 2.0 interface with transfer rates up to 400MT/s/. For these emerging enterprise applications that need higher endurance, we have SLC product and also a grade of MLC that is more robust than consumer grade MLC. Do you think NAND will continue to be able to shrink? Will the density of packages be able to increase at the same rate? There’s a lot of talk about that in the market right now, and I would say that yes, it is slowing for the floating gate technology. Maybe there are one or two more steps to it before it plateaus. We are going to start looking at it in terms of other NAND implementations that may not be floating gate—perhaps a 3D type of NAND solution where density is going to be achieved by arranging transistors vertically. The other challenge is how to step down in the process - the actual physics of NAND - which is universal to all the NAND suppliers in the industry. It requires more and more error correction, and time-to-market is a constant accelerator, making it more challenging to adopt nextgeneration NAND to keep up with the increasing requirements of ECC. Toshiba’s products are moving from raw NAND solutions to managed NAND solutions. We currently offer managed NAND solutions that manage bad block management, wear leveling and ECC, such as eMMC - which can be used in the mobile and gaming space. Another solution is managing ECC with the Visit www.eeweb.com

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EEWeb PULSE NAND chip, whether for consumer or industrial applications. For engineers, using a managed NAND solution means they don’t have to worry about ECC requirements. The value proposition is the speeding up of the memory storage implementation and accelerating time to market of their product. Is Toshiba building more fabs? The fundamentals of the NAND market are very healthy. If we look at some of the analyst’s projections, it shows the “info-plosion,” which is an image of storage that’s necessary to store all this data that continues to grow at a very fast rate, creating opportunity for NAND in the data centers. If we look from a midterm plan basis, the projections are 62% annual growth rate in terms of gigabytes between now and 2014, with roughly 75% of that being new applications and 25% being what we call ‘organic growth’ – ie.USB, SD cards and MP3 players. That brings us to the supply side of it. We will scale our factories in terms of what’s happening in the market. We recently opened our Fab 5, and when we built that fab in anticipation of what the demand would be, we only built half of it, so we are now looking at and making investments in line with what we see today as far as market demand. Tell us about the Enterprise market. Do you see that market growing a lot? That’s one of the biggest growth areas for NAND right now. In the enterprise space, the value proposition that NAND brings is much different than it is for the consumer space. In the consumer arena, where you’re talking about

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“Our leading-edge technology and innovation has enabled us to bring products to market that allow engineers to be creative and differentiate their products in many ways.” USB and SD cards, it really comes down to price. Enterprise is a completely different proposition altogether. It’s more about the total cost of ownership. Increasing storage demand and quicker access to data are driving demands on data centers (i.e. the cloud) and implementing NAND into the storage hierarchy enables datacenters to meet this challenge. When you look at the value that NAND brings into the enterprise data storage area, the green storage factor it offers should not be overlooked. Excessive heat and insufficient power are some of the top challenges data centers face. Deploying enterprise NAND based storage into data centers is a welcomed solution - a green storage solution - as NAND based arrays and SSDs use far less power which requires less cooling than traditional 15K HDD enterprise storage solutions. A single SSD in an enterprise application can replace multiple short-stroked 15,000 RPM

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hard disk drives. With that comes less power requirements, less air conditioning to keep the room at the right temperature and a significant decrease in the overall square footage of the data center. Without NAND flash, data centers could not effectively scale. An enterprise NAND SSD has been shown to be capable of 500x greater IOPS than an enterprise 15k disk drive, and brings a 90% reduction in power consumption. That’s the value proposition for NAND in the enterprise. Are there any new memory devices coming from Toshiba? As the industry platforms and capabilities moves towards high definition (HD), file sizes will increase. This creates an


INTERVIEW application and system knowledge and good communications skills, one of the skills I especially like to see when hiring an engineer is a strong aptitude for the business side. Some of the best engineers I have worked with have an MBA in addition to their technical degree. Do you have any hobbies outside of work? I really enjoy riding dirt bikes out in the desert with my wife and three sons. Going out to the desert for the weekend is a great way to unwind. We’re based out of Orange County here in Southern California, so it’s a relatively short drive to the high deserts either to the north - near an old mining ghost town called Randsburg, or inland near the Salton Sea. There are plenty of places to ride and explore in these areas, and we try to get out there as often as we can.

opportunity for high performance cards and USB drives to move content quickly to and from host and removable media - and also via WIFI. We have announced a high speed SD card called Exceria, which features some of the fastest write and read speeds in the industry (90MB/s and 95MB/s). We’ve also recently added a line of USB flash drives that are compliant with the new USB 3.0 standards –Super Speed USB; and earlier this year debuted FlashAir™, the world’s first SDHC memory card with embedded wireless LAN functionality to meet scotthe SD Memory Card iSDIO Standard. On the embedded side, we have new products built on our industryleading 19nm process: eMMC, Smart NAND and BENAND.

How have you seen the company change over the years? Toshiba has made some very significant and bold moves in the market—as previously noted, leaving the DRAM business and putting everything we have in the NAND market. Here we are in the present and Toshiba has been leading the charge for NAND flash ever since. Our leadingedge technology and innovation has enabled us to bring products to market that allow engineers to be creative and differentiate their products in many ways. What are some of the things that you look for when hiring an engineer? In addition to proven technical ability,

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The Evolution of the

NAND Flash Interface by

SPEED LIMIT

25 us

| Electrical Engineering Community Electrical Engineering Community 129 EEWeb |EEWeb

Doug Wong

Senior Member, Technical Staff Toshiba America Electronic Components, Inc.

Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis NAND flash memory has been nostrud exercitation ullamco laboris nisi ut indispensable in theconsequat. creation aliquip ex ea commodo Duis ofautemany ofin reprehenderit the consumer irure dolor in voluptate velit esse cillum dolore eu fugiat nulla devices we now take for pariatur. Excepteur sint occaecat cupidgranted, including digital atat non proident, sunt in culpa qui officia still cameras, portable media deserunt mollit anim id est laborum.

players, and smart phones. Sed ut perspiciatis unde omnis iste natus This article will explore the error sit voluptatem accusantium recent improvements to therem doloremque laudantium, totam aperiam,NAND eaque ipsa quaeinterface ab illo invenlegacy flash tore have veritatisbeen et quasi architecto beatae that made in order vitae dicta sunt explicabo. Nemo enim toipsamimprove thevoluptas interface voluptatem quia sit asperspeed. natur aut odit aut fugit, sed quia conse-

quuntur magni dolores eos qui ratione voluptatem sequi nesciunt. Neque porro quisquam est, qui dolorem ipsum quia dolor sit amet, consectetur, adipisci velit, sed quia non numquam eius modi tempora incidunt ut labore et dolore magnam aliquam quaerat voluptatem. Ut enim ad minima veniam, quis nostrum exercitationem ullam corporis suscipit laboriosam, nisi ut aliquid ex ea commodi consequatur? Quis autem vel eum iure reprehenderit qui in ea voluptate velit esse


PROJECT Since the early 1990’s, the density of NAND flash has increased by more than 1000 times. Interestingly enough, the basic interface itself has proven to be so adaptable that it is still available today. That interface is the basic asynchronous interface, which, when compared to the newer interfaces that have been developed recently, is also referred to as the legacy interface. The NAND asynchronous interface is a non-clocked interface similar to that of a memory-mapped I/O (input/output) device. It is composed of 7 control lines and an 8 bit data bus: (chip enable (/CE), address latch enable (ALE), command latch enable (CLE), read enable (/RE), write enable (/WE), ready/ busy (R/B), and write protect (/WP). Unlike most nonvolatile memory devices available at the time (MROM, EPROMs, NOR flash), there were and are no explicit address lines on the NAND interface. In retrospect, it was a good decision to put the address register inside the NAND. This allowed easy density migration from one density to another - without having to change the board pinout. For other memory devices such as SRAM, MROMs, EPROMs, and NOR Flash, it was necessary to allow for additional address lines to accommodate future higher density devices and, oftentimes, the address pin assignments of devices from different manufacturers did not match. As a historical note, there was a prototype NAND flash with a random access interface, but it never made it to production. Since the NAND flash was intended from the beginning to be used for mass data storage, it is logical for it to have an interface similar to an I/O device like a disk drive. Therefore, the NAND has 3 basic internal registers: control, address and data, and these can be memory mapped into the host processor’s address space using /CE, ALE, and CLE with the direction of the data controlled by the host using /RE and /WE. The peak bus speed of data transfers for the asynchronous NAND interface is specified in the datasheet by the read cycle time (tRC) and the write cycle time (tWC), which are typically the same. In the original 16 Mbit NAND, the cycle time was 50 ns resulting in a peak bandwidth of 20 MB/s. Today, the cycle time has decreased to about 25 ns (40 MB/s). For many applications, the bandwidth of the asynchronous NAND interface continues to be sufficient - which is

why this legacy interface continues to be supported even today.

Why was a higher speed interface necessary? As NAND flash continued to increase in storage capacity over the years, the internal page size grew. The page is the unit of data transfer from the internal memory to internal buffers. So, the page size is the number of bytes that are read from memory during a read cycle operation or the number of bytes that are programmed during a write operation. In the original 16 Mbit NAND, the page size was 264 bytes. The internal page read time was 25 us and the time to readout a page was tRC * 264 or 13 us. As the page size grew over time (512 bytes, 2kB, 4kB, 8kB, and now 16kB), the readout time became a bottleneck. The legacy asynchronous NAND interface was simply too slow.

DDR Interface NAND The legacy asynchronous NAND is an SDR (single data rate) interface in which one byte is transferred per cycle. To improve the bandwidth, it was obvious that transferring two data bytes per cycle instead of just one would double the throughput. Double-data rate (DDR) DRAMs had already paved the way, so it was only natural for NAND to adopt the same technique. In a DDR device, data is transferred on both the rising edge and falling edge of a control signal, thus transferring two data bytes per cycle. But what should the control signal be? In synchronous DRAMs, there was a clock signal. Up until this point, NAND had never had a clock signal. Two camps developed: the toggle mode camp and the ONFI (Open NAND Flash Interface) camp. The toggle mode camp favored the addition of a single signal, DQS (Data in, data out (Q), Strobe) to the existing NAND signals which “toggles” only when data needs to be transferred between the host and the NAND. The ONFI camp preferred to have an interface that is more similar to synchronous DRAM, and, in addition to the DQS signal, redefines write enable to be the clock and read enable to be the data direction. Because of this, sometimes you will hear toggle mode devices referred to as asynchronous DDR and ONFI devices referred to as synchronous DDR.

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EEWeb PULSE CE# ALE CLE WE# RE# R/B# WP#

CE# ALE CLE WE# RE# R/B# WP# DQS

CE# ALE CLE CLK W/R# R/B# WP# DQS

DQ0-7

DQ0-7

DQ0-7

Legacy Async

Toggle 1.0

CE# ALE CLE WE# RE# R/B# WP# DQS DQS# RE VREF DQ0-7

ONFI NV-DDR

Toggle 2.0 ONFI NV-DDR2

Figure 1: Legacy, Toggle Mode and ONFI

Toggle 1.0 NAND The Toggle 1.0 interface was designed to have 3-4 times the transfer rate of the existing asynchronous SDR interface. A typical Toggle 1.0 device has a transfer speed of 133 MB/s with DQS toggling at 66 MHz during the actual data transfer. But for command cycles, address cycles, and status cycles, data is transferred one byte at a time just like the legacy asynchronous interface. It is only during data input cycles when data is being written to the NAND, and data output cycles when data is being read from the NAND, that the DQS signal is used. DQS is a bidirectional signal that is driven by the source of the

data flow. During a write cycle, the source of the data is the host, so DQS is driven by the host. During a read cycle, the source of the data is the NAND, so DQS is driven by the NAND (actually, the host still controls the data transfer because even though DQS is being driven by the NAND, it is a regenerated read enable (RE#) signal from the host). Toggle mode 1.0 is designed to support data rates of 133 MB/s over an 8 bit bus. The basic data input timing (host writing data to the NAND) is shown below. The number of bytes transferred must be even, and all signals are single-ended. The NAND latches data on the rising and falling edges of DQS.

CE

CLE

tCALS

ALE tCDQSS

tDSC tWPRE

I/O

14

tWPSTH

tDSC tDQSL

tWPST

tDQSL

tDQSH

tDQSH

tDS tDH tDS tDH

tDS tDH tDS tDH

D0

D1

D2

D3

EEWeb | Electrical Engineering Community

DN-2 DN-1

DN


PROJECT The basic data output timing (host reading data from the NAND) is shown below. The host toggles RE# and the NAND generates a copy on DQS, which is fed back to the host. The rising and falling edges of DQS delimit the data window on the data bus. It is the host’s responsibility to sample in the middle of the data window.

power up. A Set Features command is used to enable the toggle 2.0 signals and features. Although the TSOP package continues to be the standard for legacy asynchronous NAND devices, the latest toggle mode devices have standardized on the JEDEC 132/152 BGA (ball grid array). This

tCS

CE

tRC tRPRE

RE

tREH

tRC tRP

tREH

tRPST

tRP

tDQSRE

tDQSRE

tDQSRE DQS

Hi-z

tCHZ

tDQSRE

Hi-z

tDQSQ I/O

tRPSTH

Hi-z

tDQSQ D0

tDQSQ D1

D2

tQHS

tQHS

tQH

Toggle 2.0 NAND The development of the toggle 2.0 interface addressed the need for even higher transfer speeds. Currently, the target speed for toggle 2.0 is 400 MB/s over an 8 bit bus. In order to achieve higher speeds, it was realized that certain high speed signals had to be differential signals: DQS and RE#. Therefore, their complements, DQS# and RE were added. Ideally, all the data lines would be differential as well, but this would be too big a change and controllers would not be able to support it easily. Instead, a VREF pin was added to improve timing accuracy for the remaining non-differential signals. Normally, VREF is Vccq/2 and precisely defines the voltage which separates logical 0 from a 1. Additional features of toggle 2.0 include programmable strength pin drivers and on-die termination.

Dn-3

Dn-2

Dn

Dn-1

Hi-z

tQHS tDVW

is a 2 channel package with two separate data buses, enabling users to support multiple NAND data channels with half the number of packages compared to single channel package designs. This is increasingly important in high bandwidth designs such as solid state disk drives and enterprise data center memory array systems. Ever since its inception, NAND flash has continuously evolved in order to meet the diverse and everchanging needs of the market. Legacy asynchronous NAND, along with the faster Toggle mode and ONFI versions, have allowed NAND flash to be adopted in a wide variety of applications beyond the original consumer market. NAND flash has truly become the ubiquitous mass storage solid state memory device it was originally intended to be.

Since the I/O power scales with frequency and the I/O voltage squared, in most high speed designs, the I/O voltage Vccq is 1.8V instead of 3.3V in order to reduce power dissipation. Toggle 2.0 devices are compatible with toggle 1.0 devices and actually default to toggle 1.0 mode at Visit www.eeweb.com

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An Odd Couple Michael Steinberger

Lead Architect, Serial Channel Products

A spectrum analyzer is an essential instrument for RF and microwave circuit design. However, at first glance it seems to be an odd choice for analyzing high speed serial data channels. This article introduces the spectrum analyzer and explains how it can be used to provide valuable insights into clocking, power supply noise, and crosstalk in high speed data signals.

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1.0 GET ANOTHER OPINION Typically, high speed serial data signals are measured using sampling oscilloscopes or real time oscilloscopes, bit error rate test sets, and occasionally by more specialized equipment such as time interval analyzers. While these instruments provide valuable data, they don’t provide the complete picture. Just as we analyze passive electrical interconnects in both the time domain (time domain reflectometry [1]) and frequency domain (S parameters), we should be measuring data signals in both the time domain and frequency domain. The frequency domain view provides an effective complement to the time domain view we already have. It’s like getting another opinion on a medical diagnosis.

Boston Radio Tu 120 100 80 60 40 20

This article introduces the spectrum analyzer as a way to measure high speed data signals in the frequency domain. After introducing the basic principles of the spectrum analyzer, it explains how the spectrum analyzer can be used to quickly measure reference clock phase noise, data or clock based DCD (duty cycle distortion), power supply noise and crosstalk.

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WBOS Mike FM WJMN

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2.0 GENERAL PURPOSE RADIO The spectrum analyzer is in essence a very general purpose radio, so we’ll compare it to a traditional car radio.

Figure 2: Hypothetical result of tuning a car radio in the Boston a

A spectrum analyzer operates in exactly the same way except that, rather than perform AM or FM reception and drive a speaker, the spectrum analyzer usually displays the spectral density on a logarithmic scale in a format very similar to Figure 2. (There is also an earphone jack on the back of the instrument, but that doesn’t get used very often.) The dynamic range is very wide: typically 70dB or better.

Figure 1: A traditional car radio

Suppose you were driving around the Boston metropolitan area and tuning the FM radio from one end of the dial to the other. Figure 2 illustrates the result you might get. At first, all you would hear is static. Then when you get to 92.9 MHz, WBOS would come in. Then at 93.7 MHz you would get Mike FM, perhaps with a different quality of reception, followed by WJMN; and so it would go up through the FM band.

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The other major differences between a car radio and a spectrum analyzer are that spectrum analyzer has a wider tuning range: typically from audio frequencies up to many giga-Herz, and the spectrum analyzer has a selectable reception bandwidth. The variable reception bandwidth, called resolution bandwidth, is fundamentally different from a car radio. Whereas the car radio has a fixed reception bandwidth, typically less than 20 kHz, the resolution bandwidth of a spectrum analyzer can be selected from a range that typically goes from 1 Khz or less to perhaps 3 MHz. Every point displayed by the spectrum analyzer represents the power in a frequency band that is as

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one should clearly understand how to calculate the frequency spectrum of a time domain signal [2]. Most of us saw this mathematics in graduate school; however, it doesn’t get applied very often in day to day work.

uning Experience

Stated succinctly, the spectrum of a signal is the Fourier transform of the autocorrelation of the signal. We recognize the Fourier transform as the way to get from the time domain to the frequency domain, and vice versa. Autocorrelation is a less common operation, however. Autocorrelation is defined as an expected value

R(τ ) = E(x(t + τ )x∗ (t))

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For example, consider a data signal with random bits. Since the data is random, each bit is only correlated with itself, and the adjacent bits are equally likely to be a one or a zero, the situation is as illustrated in Figure 3.

WFNX WCIB WKLB WPXC WODS WBCN WXLO WROR WMJX WAAF WXKS

WZLX

WCRB

Hz SportsHub

That is, slide the signal in time by a delay T. For each time t, multiply the translated signal times the original signal. Take the average. Slide to a new time delay T. Repeat.

x (t) x (t+t)

area

t

wide as the resolution bandwidth and centered around the frequency at which the data point is displayed. In other words, the resolution bandwidth determines the frequency resolution of the display. Sweep time, the time needed to accumulate a display, is closely related to resolution bandwidth. Consider that the spectrum analyzer must dwell at each frequency long enough to accumulate a valid frequency point. In other words, it takes a few milliseconds to accumulate a valid data point when the resolution bandwidth is 1 KHz, but only a few microseconds when the resolution bandwidth is 1 MHz. Furthermore, the number of independent data points is proportional to the frequency span and inversely proportional to the resolution bandwidth. Thus, the required sweep time is inversely proportional to the square of the resolution bandwidth. Sweep times can therefore range from a small fraction of a second to a few minutes. 3.0 CALCULATING FREQUENCY SPECTRA In order to make best use of the frequency domain data,

average is proportional to overlap

R (t)

Figure 3: Autocorrelation of a random data signal

In this case, we note that the autocorrelation function is a triangle. To calculate the Fourier transform, we note that the triangle is also the convolution of a square pulse with itself. The Fourier transform of a square wave is sine x over x (sinc function), so the Fourier transform of a square pulse convolved with itself is the sinc function squared.

sin2 ( ωτ2 0 ) S(ω) = ( ωτ2 0 )2 where T0 is the unit interval for the data. Note that autocorrelation and convolution are almost, but not quite the same thing. Autocorrelation is calculated by having both x(t) and x(t+T) go in the same direction Visit www.eeweb.com

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Ref -7.06 dBm

10 dB/div

Ref -7.06 dBm

-17.1 -27.1 -37.1 -47.1 -57.1 -67.1 -77.1 -87.1 -97.1 Start: 10 MHz #Res BW 1.0MHz

#VBW 3.0 MHz

Stop 2.900 GHz Sweep 2.80 ms (1001 pts)

Start: 2.900 GHz #Res BW 1.0MHz

#VBW 3.0 MHz

Figure 4: Example of a full frequency sweep of a PRBS7 data signal

10 dB/div

Ref -7.06 dBm

-17.1 -27.1 -37.1 -47.1 -57.1 -67.1 -77.1 -87.1 -97.1 Center: 5.1160 GHz #Res BW 1.0MHz

#VBW 3.0 MHz

Figure 5: Magnified sweep of PRBS7 data signal

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Span 200.0 MHz Sweep 1.84 ms (1001 pts)

Stop 6.500 GH Sweep 6.00 ms (1001 pts


of several time domain functions.

Ref -7.06 dBm

3. The frequency spectrum is the product of the Fourier transforms of the time domain functions. 4.0 EXAMPLE DATA Figure 4 shows an example of a spectrum analyzer measurement of a data signal with a PRBS7 (27-1 pseudorandom bit stream) data pattern. Figure 5 is a magnified sweep of the same data.

Start: 6.500 GHz #Res BW 1.0MHz

#VBW 3.0 MHz

Stop 10.000 GHz Sweep 5.87 ms (1001 pts)

while convolution is calculated using x(t) and x(T-t), and thus has the two waveforms in the integral go in opposite directions. The only reason the math above works out so neatly is because the square pulse is symmetrical in time, and therefore looks the same going forwards or backwards. Other frequency spectra can be calculated using the same techniques: 1. Identify the structure of the autocorrelation function. 2. Express the autocorrelation function as the convolution

The first thing to notice in Figure 4 is that there are numerous uniformly spaced spectral components that seem to contain most of the energy. The spacing is a little over 80 MHz, or exactly the data rate divided by 127. That is to be expected for a PRBS7 pattern (length = 127). Consider thxat the autocorrelation function of this data pattern is exactly like that of Figure 3, except that the triangle is repeated every 127 bits when the data patternr repeats. The autocorrelation function is therefore the convolution of the triangle with a series of impulses in the time domain spaced 127 bits apart. When the Fourier transform is applied, the series of impulses in the time domain beecomes a series of impulses in the frequency domain.

sin2 ( ωτ2 0 ) comb((27 − 1)ωτ0 ) S(ω) = ( ωτ2 0 ) 27 − 1 Figure 6 also suggests several other phenomena. First of all, note that the spectral density rises a bit above

COMP Interface - PRBS7 data pattern -30.0 -40.0 -50.0

Volts (V)

Hz s)

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-60.0

Power Supply Noise??

Clock Leakage??

x1: (5034.0M) x2: (5115.0M) dx: 81.090M

Transmit Reference Clock Phase Noise

-70.0 -80.0 -90.0 -100.0 -110.0 5050.0

5100.0

5150.0

5200.0

Hertz (MHz) Figure 6: Analysis of magnified frequency sweep data (Figure 5)

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EEWeb PULSE the noise floor in the vicinity of a spectral component. This is probably due to the phase noise of the transmit reference clock, in that it is typical of the 1/f phase noise of an oscillator. This phase noise could be studied in more detail by using a shorter data pattern (e.g., repeating 1/0), thus increasing the spectral density of the signal with respect to the noise floor. One could achieve the same effect by decreasing the input attenuation on the spectrum analyzer. However, some care would required, since decreasing the input attenuation could significantly increase nonlinearities in the spectrum analyzer front end. It’s also possible to make a preliminary estimate of the transmit reference clock phase noise from the existing data.

data. In this case, the data demonstrates that there was clock based DCD on the transmitter. We know it was clock based DCD because of the lower amplitude spectral components centered half way between the main spectral components of the PRBS7 pattern.

COMP -30.0 -40.0

Volts (V)

Another phenomenon in Figure 6 is a spectral component at exactly one half of the data rate. This could be leakage of a half rate clock used internal to the transmitter. 5.0 POWER SUPPLY NOISE At least for those IC cores that are clocked at a high frequency, typically about 70% of the current is consumed by the flip flops and the clock distribution network, even when the IC is actively processing data. This makes sense in that to operate at high clock rates, the logic design must be heavily pipelined, and so there are a lot of flip flops, with every flip flop consuming current on every clock cycle.

Some of the spectral components in Figure 6 could be due to power supply noise; however, they’re at such a low level that they would not significantly affect system performance. 6.0 DUTY CYCLE DISTORTION Figure 7 shows another magnified sweep of the same

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-50.0 -60.0 -70.0 -80.0 -90.0 -100.0 100.0

In other words, most of the core current in a high frequency IC core is consumed at the core clock frequency and its harmonics. Thus, if power supply noise is leaking directly into the data signal, it will be most prominent as a spectral component at the core clock frequency. Similarly, if power supply noise is modulating the delay of the clock and data paths in the transmitter, then that phase modulation will be readily apparent as spectral components separated from the main data signal spectral components by plus or minus the core clock frequency. Any such phase modulation can therefore be sensitively and accurately measured using a spectrum analyzer.

y1: (-25.610 y2: (-50.670 dy: -25.060

200

Figure 7: Spectral analysis demonstrating the presen

There are two types of DCD: clock based and data based. In the most common form of clock based DCD, every other clock edge (e.g., an even numbered clock edge) is delayed with respect to the one that came before it (e.g., an odd numbered clock edge). This is distinctly different from data based DCD, in that for data based DCD, rising data edges are delayed with respect to falling data edges, or vice-versa. While the autocorrelation functions for clock based DCD and data based DCD are far too complex to make a closed form solution practical, we can explain the effect of each impairment on the measured spectrum, and provide a useful rule of thumb for estimating the magnitude of each impairment when measured using a PRBS7 data pattern. Clock based DCD in a repeating data pattern with

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an odd number of bits will show up in a measured spectrum as a series of spectral components with a frequency spacing equal to one over twice the data pattern duration. Thus, for example, a PRBS7 has length 127, which is an odd number. Therefore the frequency spacing of the clock based DCD spectral components

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Thus, for example, the 25 dB level difference for the clock based DCD in Figure 7 is about 0.056 UI, peak to peak. Data based DCD in a repeating data pattern will show up in a measured spectrum as a spectral component

P Interface - PRBS7 pattern

0) 0)

0.0

300.0

400.0

500.0

Hertz (MHz)

nce of clock-based DCD

will be the data rate divided by 254. The reason is that if one repetition of the data pattern starts on an even numbered clock cycle, the next repetition will start on an odd numbered clock cycle. Thus, the waveform won’t be exactly the same again until two repetitions of the data pattern have gone by. In effect, the length of the data pattern has been doubled. The rule of thumb for clock based DCD is that given • Sd: The level of one of the main data spectral components near DC, in dB • Sc: The level of one of the lower level half frequency spaced components near DC, in dB

DCDclock (pk − pk) = 10

Sc−Sd 20

at a frequency equal to the data rate. Consider that Figure 3 and Equation 2 assume that all data bits have exactly the same duration. If, however, data based DCD is present in a data pattern such as PRBS7, then every repetition of the data pattern will be exactly the same, but the bits within the data pattern will not all have the same duration. Thus, while there will still only be spectral components at multiples of the pattern repetition rate, as in Equation 3, the spectral components will not null out completely at a frequency equal to the data rate. The rule of thumb for data based DCD in a PRBS7 data pattern is that given • S0: The level of a spectral component near DC, in dB • Sf: The level of the spectral component at a frequency equal to the data rate, in dB Visit www.eeweb.com

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PRBS7 with no DCD

dBVoltsA2/Hz (dBVA2/Hz)

60.0 50.0 40.0 30.0 20.0 10.0 0

0.50

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Figure 8: Spectral density for PRBS7 computational experiment with no DCD

PRBS7 with 0.25 UI pk-pk of clock based DCD Clock based DCD spectral components

dBVoltsA2/Hz (dBVA2/Hz)

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Figure 9: Spectral density for PRBS7 computational experiment with 0.25 UI pk-pk clock based DCD

dBVoltsA2/Hz (dBVA2/Hz)

PRBS7 with 0.25 UI pk-pk of data based DCD Data based DCD

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Figure 10: Spectral density for PRBS7 computational experiment with 0.25 UI pk-pk clock based DCD

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• IL: The insertion loss of the measurement channel at a frequency equal to the data rate, in dB

DCDdata (pk − pk) ≈ 0.2 · 10

Sf −S0+IL 20

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9.0 REFERENCES [1] Mike Steinberger, “TDR: Reading the Tea Leaves”, EEWeb, http://www.eeweb.com/blog/michael_ steinberger/tdr-reading-the-tea-leaves

To illustrate the difference in spectra between clock based DCD and data based DCD, I performed a computational experiment using an ideal PRBS7 data pattern and a DCD amplitude of 0.25 UI, peak to peak. The results are shown in the figures on the left.

[2] A. Papoulis, Probability, Random Variables, and Stochastic Processes, chapter 10, McGraw-Hill, Inc., 1965.

7.0 CROSSTALK

About the Author

It’s also possible to use a spectrum analyzer to measure the level of a crosstalk interferor while the victim transmitter is active. Consider that each data pattern has its own signature in the frequency domain. For example, a PRBS15 can be easily distinguished from a PRBS7 because the spacing of the spectral components is so very different. Therefore, one could drive the victim transmitter with a PRBS15 and the aggressor transmitter with a PRBS7, and the level of crosstalk would be easy to measure. When making this measurement, be sure to account for the fact that the power in a single spectral component is inversely proportional to the number of spectral components. That is, the total power is constant. Thus, 24 dB would have to be added to the PRBS15 spectral components in order to compare them to the PRBS7 spectral components.

Michael Steinberger, Ph.D., is responsible for leading SiSoft’s ongoing tool development effort for the design and analysis of serial links in the 5-30 Gbps range. Dr. Steinberger has over 30 years experience in the design and analysis of very high speed electronic circuits. Dr. Steinberger began his career at Hughes Aircraft designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital long-distance transmission. He was instrumental in the development of high speed digital backplanes used throughout Lucent’s transmission product line. Prior to joining SiSoft, Dr. Steinberger led a group of over 20 design engineers at Cray Inc. responsible for SerDes design, high speed channel analysis, PCB design and custom RAM design.

8.0 A VERSATILE TOOL This article has demonstrated that a spectrum analyzer can be a versatile tool for evaluating high speed serial data signals. Its frequency domain view complements the time domain view provided by high speed oscilloscopes and other, similar instruments. In particular, the spectrum analyzer can evaluate reference clock phase noise, power supply noise, clock leakage, DCD, and crosstalk far more effectively than the time domain instruments. The measurements are easy to make and interpret, making the spectrum analyzer a valuable tool for interactive investigation in the laboratory.

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Get the Datasheet and Order Samples http://www.intersil.com

Single or Multiple Cell Li-ion Battery Powered 4-Channel and 6-Channel LED Drivers ISL97692, ISL97693, ISL97694A The ISL97692, ISL97693, ISL97694A are Intersil’s highly integrated 4- and 6-channel LED drivers for display backlighting . These parts maximize battery life by featuring only 1mA quiescent current, and by operating down to 2.4V input voltage, with no need for higher voltage supplies. The ISL97692 has 4 channels and provides 8-bit PWM dimming with adjustable dimming frequency up to 30kHz. The ISL97693 has 6 channels with Direct PWM dimming control. The ISL97694A has 6 channels and provides 8-, 10-, or 12-bit PWM dimming with adjustable dimming frequency up to 30kHz, 7.5kHz, or 1.875kHz, respectively, controlled with I2C or PWM input. ISL97692 and ISL97694A feature phase shifting that may be enabled optionally, with a phase delay between channels optimized for the number of active channels. In ISL97694A, phase shifting can multiply the effective dimming frequency by 6 allowing above-audio PWM dimming with 10-bit dimming resolution. The ISL97692/3/4A employ adaptive boost architecture, which keeps the headroom voltage as low as possible to maximize battery life while allowing ultra low dimming duty cycle as low as 0.005% at 100Hz dimming frequency in Direct PWM mode. The ISL97692/3/4A incorporate extensive protection functions including string open and short circuit detections, OVP, and OTP. The ISL97692/3 are offered in the 16 Ld 3mmx3mm TQFN package and ISL97694A is offered in the 20 Ld 3mmx4mm TQFN package. All parts operate in ambient temperature range of -40°C to +85°C.

Features • 2.4V Minimum Input Voltage, No Need for Higher Voltage Supplies • 4 Channels, up to 40mA Each (ISL97692) or 6 Channels, up to 30mA Each (ISL97693/4A) • 90% Efficient at 6P5S, 3.7V and 20mA (ISL97693/4A) • Low 0.8mA Quiescent Current • PWM Dimming Control with Internally Generated Clock - 8-bit Resolution with Adjustable Dimming Frequency up to 30kHz (ISL97692/4A) - 12-bit Resolution with Adjustable Dimming Frequency up to 1.875kHz (ISL97694A) - Optional Automatic Channel Phase Shift (ISL97692/4A) - Linear Dimming from 0.025%~100% up to 5kHz or 0.4%~100% up to 30kHz (ISL97692/4A) • Direct PWM Dimming with 0.005% Minimum Duty Cycle at 100Hz • ±2.5% Output Current Matching • Adjustable Switching Frequency from 400kHz to 1.5MHz

Applications • Tablet, Notebook PC and Smart Phone Displays LED Backlighting

Related Literature (Coming Soon) • AN1733 “ISL97694A Evaluation Board User Guide” • AN1734 “ISL97693 Evaluation Board User Guide” • AN1735 “ISL97692 Evaluation Board User Guide” 10

L1

VIN: 2.4V~5.5V

10µH

4.7µF

10

D1

VOUT: 24.5V, 6 x 20mA 4.7µF 4.7µF

1

VIN LX COMP

15nF 12k

100pF 470k

OVP 2.2nF

ISL97694A

ILED (mA)

1µF

23.7k

ISET 53k

AGND

PGND

0.1

0.01 fPWM: 200Hz

SDA/PWMI SCL

CH1

EN

CH2

FPWM 291k

FSW

143k

0.001

CH3 CH4 CH5

0.0001 0.001

CH6

FIGURE 1. ISL97694A TYPICAL APPLICATION DIAGRAM

July 19, 2012

FN7839.2 28

fPWM: 100Hz

0.01 0.1 1 INPUT DIMMING DUTY CYCLE (%)

10

FIGURE 2. ULTRA LOW PWM DIMMING LINEARITY

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