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INTERVIEW

EEWeb Issue 78

December 25, 2012

John Tanner

CEO, Tanner Research

TECHNICAL ARTICLE

New Approach to Analog Productivity TECHNICAL ARTICLE

Power Interfacing the Internet of Things - Part 2

Electrical Engineering Community

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Experts Exchanging Ideas Every Day. VISIT DIGIKEY.COM/TECHXCHANGE TODAY! Digi-Key is an authorized distributor for all supplier partners. New products added daily. Š 2012 Digi-Key Corporation, 701 Brooks Ave. South, Thief River Falls, MN 56701, USA


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TABLE OF CONTENTS

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John Tanner Tanner research Interview with John Tanner - CEO

Featured Products

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New Approach to Accelerating Analog Productivity

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By Tanner EDA How Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives.

MCU Wars 2.4 - The DevCon Experience Two experts in RTOS sit down to discuss their experiences at DevCon 2012 and what sets this convention apart from the others.

Power Interfacing the Fundamental Component of the Internet of Things - Part 2

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By Roderick Bacon with Intersil How the Internet of Things is a new burgeoning field by combining sensing, embedded computing and communication technologies.

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RTZ - Return to Zero Comic

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Tann 4

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INTERVIEW

ner

Tanner Research Visit www.eeweb.com

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EEWeb PULSE How did you get into electrical engineering? I started by learning programming as an undergrad at a small liberal arts college in Iowa. On an internship, I got to work on a minicomputer; that got me exposed to The TTL Cookbook and The CMOS Cookbook. From that experience I learned more about the parts that went into computers….and got exposure to digital design. While still an undergrad I built a Z80based computer (the first computer on the Wartburg campus!). That led me to pursue graduate work at Caltech in Pasadena. I started in 1979 as an EE and during that first year while taking a VLSI design course we received a pre-print of Carver Mead’s seminal textbook, Introducton to VLSI Design. It was that course that opened my eyes to the broader canvas for circuit design. We used Xerox PARC (MOSIS was just getting formed) to fab our custom integrated circuits. We actually got back chips that we had designed! Of course, the EDA tools were very crude. We used black & white vector scopes for layout and did check plotting for verification. After 1 year in the EE program I changed to computer science; that’s where chip work was done at Caltech. It was my introduction to CAD class – and the task of having to write software – that set the groundwork for Tanner EDA’s L-Edit. Later – as a grad student – I started a small company with some classmates. We had an idea for a chip and bought a 4.77 Mhz PC to help create the design. We “splurged” on an RGB monitor! We decided to program our own software for the chip design in lieu

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“The software tools created for that start-up became so popular that I decided to spin out and form Tanner Research. Nearly 25 years later, we are still serving the needs of IC and MEMS designers -- now worldwide!” of having to use an expensive CAD workstation. The software tools created for that start-up became so popular that I decided to spin out and form Tanner Research. Nearly 25 years later, we are still serving the needs of IC and MEMS designers – now worldwide! Do you have any tricks up your sleeve? I suggest students seek out entrepreneurial opportunities whenever and wherever possible. When I was in grad school, my friends and I bucked the trend to take internships with large companies and instead started our own company and worked with other entrepreneurial companies. Those experiences proved to be

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invaluable and gave me the courage to form Tanner Research and its various subsidiaries. To this day, we continue to hire summer interns and give them opportunities to work within Tanner EDA or one of our other divisions. We continue to encourage our interns and our employees to embrace an entrepreneurial spirit.


INTERVIEW

What has been your favorite project? Even though it was a while ago, I found the cross-section viewer in L-Edit (Tanner EDA’s complete hierarchical physical layout editor for IC design) to be a very satisfying project. Adding this functionality really gave analog designers something they needed. Whenever

analog designers describe their circuits, they think and talk in that view. Do you have any note-worthy engineering experiences? Seeing our tools used for such great innovations as the Mars Rover, leading healthcare diagnostic tools, and other designs that benefit

business and society, is greatly rewarding. What are you currently working on? Tanner EDA’s upcoming major release – v16 – is the major focus of our team right now. It will feature L-Edit on Open Access. We’ve always embraced industry Visit www.eeweb.com

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“Seeing our tools used for such great innovations as the Mars Rover, leading healthcare diagnostic tools, and other designs that benefit business and society, is greatly rewarding.�

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INTERVIEW standards as a way of making sure our users had access to their designs and to the broad set of tools offered in the industry. The release of v16 will allow our users to have true interoperability with designs created in other tools while simultaneously adding features and capabilities essential for productivity and ease of use.

expansion along the mixed-signal tool flow. Our MEMS tools will continue to evolve to keep up with emerging requirements in that important design domain.

Can you tell us more about Tanner as a company? What is the work culture like?

What challenges do you foresee in our industry?

We’ll continue to grow organically and to align with partners to deliver the technologies and tools our users need.

Tanner Research is a small company; we have about 60 employees worldwide. Because we’re small, our AEs have direct access (literally – down the hall!) to our engineering and development teams. We work very collaboratively within our company and with our customers to help align our tools with the needs of designers.

A major concern I have – and one we hear echoed by our users – is the availability of talent to create analog circuits. While we’re delighted to see many of our customers celebrating major milestones (10, even 20 years) as Tanner users, I worry that there’s not a significant quantity of talent directed towards understanding and addressing the problem domain.

What direction do you see your business heading in the next few years?

What are some of your hobbies outside of work and design?

We’ll continue to build out Open Access and related interoperability capabilities. We also see continued

Oh – I’ve got quite a few hobbies. Many of them wind up becoming divisions or at least projects within

Tanner Research. One is pogo sticks! We worked with a researcher at Carnegie-Mellon to bring a radically new pogo stick design to market. (BoGo – now licensed to Razor). I also have a lot of interest in nutrition and I’ve recently launched NuSci – an initiative to educate the public on topics related to nutrition and science.

For more information about Tanner EDA, visit their website at:

www.tannereda.com

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Offline LED Driver for Retrofit Lamps Maxim Integrated would like to highlight its MAX16841, an offline LED driver that provides flicker-free dimming from maximum light intensity down to zero intensity with both leading-edge (triac) and trailing-edge (transistor) dimmers. Constant frequency control optimizes efficiency at both low- and high-AC line voltages. With a wide 90VAC to 265VAC input range, the MAX16841 is a universal solution for Japanese, Chinese, U.S., and European dimmer models. It allows seamless replacement of incandescent and halogen lamps, thus eliminating compatibility issues with preinstalled dimmers. The MAX16841 prolongs the life of the LED lamps because it can operate without electrolytic capacitors. For more information, please click here.

Floating-Suspension High-Vacuum Pump Agilent Technologies Inc. introduced a high-performance turbomolecular vacuum pump, the TwisTorr 304 FS, which is the first in a new series of high-vacuum pumps featuring Agilent’s novel floating-suspension technology. This technology can be used in a variety of applications and markets, including academic and government research, and the analytical, industrial and nanotech/semiconductor industries. Running at 60,000 rpm, it pumps up to 250 liters per second for N2. It also provides dramatic improvements in reliability and increases light gas compression ratios 100-fold. For more information, please click here.

Dual XAUI Transceiver The TLK3138 is an eight channel serial transceiver. It is compliant with the 10Gbps Ethernet XAUI specification. The TLK3138 provides 10 Gbps high-speed bi-directional point-to-point data transmission. The primary application of this device is in backplanes and front panel connections requiring dual/redundant 10Gbps connections over controlled impedance media of approximately 50Ί. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines. For more information, please click here.

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New Approa Acceleratin Layout

Surpasses Full Custom Traditional Automation Methodologies Tanner EDA

Despite many efforts to automate analog design

and layout, these tasks remain primarily a full custom process, with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive. Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time–consuming aspect of layout and indeed the

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parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield. Layout engineers maintain complete freedom to manually place and route these structures as well as being able to tune the output to their specific requirements. Surpassing traditional automation methodologies, this new layout approach dramatically improves layout productivity and reduces design cycle times while generating structures at a level of quality that consistently matches that of the most experienced layout engineers.


PROJECT

ach to ng Analog &

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CE GENERATION

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rating Analog Analog Surpasses layoutLayout is becoming the primary bottleneck inMethodologies the design process l Automation

analog design where device matching is critical to performance. Expertise even in basic matching techniques can vary from engineer to engineer, which Analog layout has traditionally been considered to be can in some cases lead to the chip failing. Layout more challenging than digital layout. For example, it engineers with the experience and knowledge to go layout, these tasks remain primarily full custom process, with the result that analog takes considerably moreatime to achieve a high level beyond the techniques produce designs that design cycle time. Efforts to automate analog design have not been successfulbasic in of expertise in analog layout as compared to the time much ble to equal the quality levels of full custom design, are complex to are set up andmore use, likely to work the first time, but such required to master digital layout. So it comes as no people are in short supply. A leading analog foundry surprise that digital design automation technology recently cited matching issues as the single biggest has advanced a much pace key thananalog its analog r of accelerating the layout at process by faster generating design primitives, such in their customer’s designs. cause of re–spins ives are often the most time–consuming aspect the of layout and indeed the parts that counterpart. Since digital occupies vast majority ool appliesof matching techniques to address processing produces As process technology moves deep into the nanometer most projects, design cycle common times have trended artifacts, nd creates devices optimized for high yield. realm, the impact of process variations and parasitic downwards even as transistor counts have continued effects have caused the analog layout process to be to increase geometrically. nually place and route these structures as well as being able to tune the output to highly iterative utomation methodologies, newlayout layoutengineers approachuse dramatically layout and time–consuming. Analog layouts Right now, most this analog either a improves often be revised, re–simulated and the results enerating structures at a level of quality that consistently matches that of must the most full custom approach—drawing every polygon—or evaluated over and over again to achieve a robust use basic device generators provided by the foundry solution. In a typical project, analog may occupy only to create MOSFETs, capacitors, resistors, etc. The a small portion of the silicon area but can consume a eneck in the vastdesign majorityprocess of layout engineers manually place these very large portion of the layout effort. As feature sizes devices than together to form basic structures e more challenging digital layout. For analog example, it takes such considerably more time are reduced, the time required for full custom analog s comparedastocurrent the time required master digital it comeslayout as noissurprise mirrors andtodifferential pairs,layout. whichSo in turn rising, with the result that many companies ced at a much pace than its analog counterpart. Since digital occupies the vast arefaster connected together to form the overall circuit. are seeing an increase in time–to–GDSII at nanometer nded downwards even as transistor counts have continued to increase geometrically. The quality of the resulting layout is obviously heavily technology nodes. Figure 1 shows data collected dependent upon the expertise of the individual layout fromgenerators a sampling of customers of IC Mask Design, a full custom approach—drawing every polygon—or use basic device engineer. company that provides analog physical design rs, resistors, etc. The vast majority of layout engineers manually placea these devices rent mirrorsThe and very differential pairs, which in turn are connected together to form the services. long period of time required to develop bviously heavily dependent upon the expertise of the individual layout engineer. expertise in analog layout means that skill levels vary Existing analog automation solutions widely layout amongmeans the members the typical layout team. pertise in analog that skilloflevels vary widely among the members of have not gained acceptance by users The lack of aalso consistent roach among members drives upapproach the time among requiredmembers for the review process and Large and low small vendors offer varying approaches also drives up the time required the review process s. These problems appear most often in theformore difficult areas of high speed, atching is critical to performance. even in basic design matching techniques can to analog automation, ranging from simple device and increases the riskExpertise of needing additional ases lead tospins. the chip failing. Layout engineers experience knowledge generation tools to full–blown analog layout These problems appear mostwith oftenthe in the more and that are much moreareas likelyoftohigh work the first buthigh such people areautomation. in short supply. One analog automation solution focuses difficult speed, lowtime, noise, precision ues as the single biggest cause of re–spins in their customer’s designs. on providing advanced editing features for creating and editing ometer parameterized cells to expedite effects the process of creating matched erative structures. Another tool builds on evised, the parameterized cell approach by again adding many additional parameters analog ea but and technology independence. Both ort. As operate only at the device level, so ustom they do not address the layout of panies circuits and structures, which is not ometer only the most time–consuming part rom a of the analog layout process, but ny that also the portion that is most prone to poor quality and inconsistency. Large amounts of time are required Figure 1: Transistorcount countvs. vs. time time to to GDSII GDSII by Node to generate individual structures Figure 1: Transistor byTechnology Technology Node

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layout of circuits and structures, which is not only the most time–consuming part of the analog layou is most prone to poor quality and inconsistency. Large amounts of time are required to generate ind quality of the resulting layout varies depending upon the skill of the individual engineer.

PROJECT

Figure 2: Generation based on existing DRC rules Figure 2: Generation of structures based of onstructures existing DRC rules.

Anoth to com proces langua own p engine these at a h consid the ke them o Users do no create as inp genera also p of this match skilled a curre be laid pair. O list pri million

Tanner EDA’s HiPer DevGen (High by hand and the quality of the resulting layout varies Tanner EDA’s HiPer DevGen (High Performance Device Generator) accelerates analog Performance Device Generator) depending upon the skill of the individual engineer. generating common structures accelerates analog layout by Another analog layout solution attempts to completely automatically generating common As we’vetheseen above, previous to atry to automate the analog design process have been prim automate analog layout process.methods It provides structures programming that allows users A to new codeapproach is based on accelerating analog layout by gene at the level language of the complete design. As we’ve previous methods to try to creates their own physical cells and its placement engine and over again such as current mirrors, differential pairsseen and above, resistor dividers. This approach automate the analog design process have beenlayout. Ra generates the layout on these cells. But the understanding of based the functional requirements that are needed to produce a high–quality primarily based either at the cell level or at the level coding takes place at a high level that does not take automate analog design, HiPer DevGen accelerates the most time–consuming aspects of the layout of the complete design. A new approach is based on into consideration the basic characteristics of the amount of time required for analog layout while improving quality and design consistency. accelerating analog layout by generating primitives key building blocks and may not lay them out with that are used over andtransistors over againand suchresistors as current the correct considerations. Users often find that MOS as well as M By automatically generating the layout of devices—including mirrors, differential pairs and resistor dividers. This the resulting designs do not compare in quality to a pairs, resistor dividers and other basic structures—this new approach provides nearly the same degre approach creates these building blocks based on an manually created layout. Yet another tool takes as but awith higher Asthen well as automating the tedious,ofrepetitive aspects of the that design understanding the functional requirements are process input set of designquality. rules and generates basic complex which and often veryplaced expensive setupOne process that tois produce required with current analog automation too needed a high–quality layout. Rather than structures, are also and routed. attempting to completely automate analog design, weakness of this approach is that it applies global HiPer DevGen generates both devices and analog design primitives using only the HiPer DevGen accelerates the most time–consuming matching rules to automatically the entire layout while skilled specific technology nodethat asaits input. The for tool itself understands technology and matching aspects of the layout the process to substantially reduce require manual designers understand current mirror, the basic building analog these requirements taken account. Layout engin amount of time required for into analog layout while example, should not beblocks laid out of in the same layout way as awiththe out and place and route these structures. HiPer DevGen is provided with basic default values that mee improving quality and design consistency. differential pair. One more obstacle to adoption is its list price, which quoted at in close to a million dollars designs. For isexample, a differential pair it will always attempt to optimize the drain parasitics ove for a single license. circuits such as down mixers, where the source capacitance is more critical, the designer or layout

parameters, regenerate, simulate the design and converge on an optimal design approach.

Visitrequires www.eeweb.com Retargeting the components to a new technology node simply the user to input the 15manufac


EEWeb PULSE By automatically generating the layout of devices— including MOS transistors and resistors as well as MOS current mirrors, MOS differential pairs, resistor dividers and other basic structures—this new approach provides nearly the same degree of acceleration as full automation, but with higher quality. As well as automating the tedious, repetitive aspects of the design process, HiPer DevGen also eliminates the complex and often very expensive setup process that is required with current analog automation tools. HiPer DevGen automatically generates both devices and analog design primitives using only the manufacturing design rules for the specific technology node as its input. The tool itself understands the technology and matching requirements and automatically generates the basic building blocks of analog layout with these requirements taken into account. Layout engineers have complete freedom to lay out and place and route these structures. HiPer DevGen is provided with basic default values that meet the requirements of 90% of analog designs. For example, in a differential pair it will always attempt to optimize the drain parasitics over the source parasitics. However in circuits such as down mixers, where the source capacitance is more critical, the designer or layout engineer can easily change these parameters, regenerate, simulate the design and converge on an optimal design approach. Retargeting the components to a new technology node simply requires the user to input the manufacturing rules for that technology and regenerate the devices and primitives. So it is possible to very quickly move a design to a new technology node or to a different foundry. HiPer DevGen was designed to be implemented with little or no change to existing design flows. Unlike existing full automation tools, it works with unmodified schematics. It also uses as input netlists produced for schematic driven layout (SDL) and also accepts input directly from S-Edit, Tanner EDA’s schematic editor. HiPer DevGen builds upon Tanner EDA’s existing T-Cell architecture of parameterized cells that exist within the company’s L-Edit layout editor. The generated cells are cached in the database for maximum performance. HiPer DevGen automatically recognizes the building blocks of the design and generates technology–aware building blocks. The layout engineer then connects the blocks together and wires them to pins to complete the design.

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Quality equals that which can be achieved by best analog layout engineers The HiPer DevGen generation engine is “silicon– aware” and produces devices that are optimized for high yield, including double contacts and vias and support for design for manufacturing (DFM) rules, where applicable. The generation engine takes into account over 20 common processing artifacts and applies matching techniques so that these processing effects are reduced where possible or are applied equally across all matched devices. These artifacts include, but are not limited to: » Linear process gradients » Mask misalignment » Implant shadowing » Mechanical stress, including shallow trench isolation (STI) or length of diffusion (LOD) » Photolithographic invariance » Current flow direction » Antenna effect/Vt shift » Well proximity effect (WPE) HiPer DevGen ensures a consistent and high quality approach to the layout of complex analog structures across layout engineers, design teams and engineering sites. The generation engine considers device and interconnect parasitics and silicon area, and produces the optimal solution based on design inputs, foundry manufacturing rules, and user matching requirements. Matching, parasitic, and performance considerations are tuned to specific analog structures such as the previously mentioned differences between current mirrors and differential pairs. The generation engine understands the key parameters associated with each structure and generates the structures so that these key requirements are met while maintaining a continual focus on silicon quality, yield, silicon performance, and matching. The generation engine also can be adjusted to ensure that its output fits the user’s specific matching, parasitic, and performance requirements. For example, HiPer DevGen offers the user the ability to prioritize parasitic performance over matching requirements or vice versa, and also gives precedence to key


sign cycle. Worse still, such as error could produce a circuit that is LVS and DRC 窶田lean by construction, but has a mismatch, resulting the problem only being seen in silicon. HiPer DevGen instantly created the structure shown, with the added assurance that it meets requirements of the targeted technology.

PROJECT

Figure 3: Example current mirror

Figure 3: Example current mirror

Figure 4: Complex current mirror with dummies

Figure 4: Complex current mirror with dummies

4 showswithin a more complex current withthat dummies, butand in thisDRC窶田lean case there are by three output currents. In this case t Figure matching concerns over others a circuit. Formirror,a again circuit is LVS construction, are being scaled by two, two, and four respectively. This structure would take considerably longer than the first example (Figure instance on large devices, where a mismatch to thebut has aof mismatch, resulting in the problem onlyHiPer DevGen a done by hand and its complexitydue increases possibility an error that could cause rework or quality problems. generated this device instantly, with only the manufacturing rules provided as input. linear gradients is recognized as being a priority, the being seen in silicon. HiPer DevGen instantly created generation of the structure can be weighted towards the structure shown, with the added assurance that it that, as opposed to a possible mismatch in drain or meets all requirements of the targeted technology. source area. Figure 4 shows a more complex current mirror, again with dummies, but in this case there are three output Examples of how this approach works in currents. In this case they are being scaled by two, practice two, and four respectively. This structure would take An example of a current mirror is shown in Figure 3. considerably longer than the first example (Figure While an experienced layout engineer would probably 1) if done by hand and its complexity increases the spend only a short time to create this structure, the possibility of an error that could cause rework or possibility exists that he or she might make an error quality problems. HiPer DevGen also generated this that could take hours or even days to resolve later in the device instantly, with only the manufacturing rules design cycle. Worse still, such as error could produce provided as input.

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Figure 4 shows a more complex current mirror, again with dummie are being scaled by two, two, and four respectively. This structure done by hand and its complexity increases the possibility of an erro generated this device instantly, with only the manufacturing rules p Figure 5 shows a simple two fingered differential pair with a guard ring. In this case, the drain capacitance is optimized on both devices and the gates are densely connected in metal in order to reduce gate resistance and lower parasitic channel noise. While this example consists of only two transistors with two fingers each, the care required to lay out the structure increases the layout time dramatically. In conjunction with the increased layout effort, the risk of laying it out incorrectly, such as by optimizing the drain, also increases and these errors are typically only spotted either in silicon or where design flows ensure stringent extraction and post–layout simulation of all circuits. With HiPer DevGen, it is possible to create this instantly and, if necessary, generate multiple variants, allowing circuit designers to simulate each solution and converge on an optimal solution for their design in the shortest period of time.

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Figure 6 shows a more complex differential pair with two devices of eight fingers each as well as a guard ring, protection diodes, and dummy devices. In this case, the capacitance of the source also is being optimized. A device of this complexity would take considerably more time than the previous example to lay out by hand. Manual layout would also present considerable risk of error. For example, moving one of Figure 5: Two finge these devices by a micron could introduce a mismatch into the device. HiPer DevGen instantly generated Figure 5 shows a simple two fingered differential pair with a guard ri this device while simultaneously providing perfect and the gates are densely connected in metal in order to reduce ga matching between both devices. consists of only two transistors with two fingers each, the care requ In conjunction with the increased layout effort, the risk of laying it Figure 7 shows the schematic of a complete circuit with these errors are typically only spotted either in silicon or where de 17 functional devices. The top row of four transistors of all circuits. With HiPer DevGen, it is possible to create this inst (two fingers in each device) is made up of two current designers to simulate each solution and converge on an optimal so mirrors, the next row of four transistors (two fingers in each device) is made up of two differential pairs and the bottom row of three transistors is another current mirror, comprising five gates in total. Figure 8 shows the layout of the same circuit shown in Figure 7. While they are not shown in the schematic, approximately ten dummy devices would also be required in order to ensure matching, bringing the total device count from 17 to 27. A number of analog layout engineers were asked how long it would take them to lay out this circuit, while obeying best layout practice and applying common matching techniques. Their answers ranged from two hours to two days with an average time of approximately five hours. The complexity of the design means that

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Figure 6: Eight finge

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es, but in this case there are three output currents. In this case they would take considerably longer than the first example (Figure 1) if or that could cause rework or quality problems. HiPer DevGen also provided as input.

PROJECT

Figure 5: (Top) Two finger differential pair. Figure 6: (Bottom) Eight finger differential pair.

er differential pair.

nearly every engineer would do it differently and these ing. In this case, the drain capacitance is optimized on both devices differences have the potential, at best, to lengthen the ate resistance and lower parasitic channel noise. While this example review process or, at worst, to create yield problems uired to lay out the structure increases the layout time dramatically. or indeed non–functioning silicon. On the other hand, out incorrectly, such as by optimizing the drain, also increasesusing and HiPer DevGen, a layout engineer instantaneously esign flows ensure stringent extraction and post–layout simulation generated all of the individual structures in the circuit, antly and, if necessary, generate multiple variants, allowing circuit significantly reducing the overall design effort. The olution for their design in the shortest period of time. layout engineer then manually floorplanned the circuit and completed the interconnect between devices. Each device or structure was created exactly the same to meet all requirements of the technology, correct by construction in terms of passing layout versus. schematic checks (LVS), DRC clean and with guaranteed matching. Using this approach, let’s suppose that the designer changes a parameter, such as increasing the number of fingers or making the block shorter or wider to fit a different floor plan. Or maybe multiple configurations are required to address parasitics identified during simulation. If the design were done by hand, alternate versions would probably take just as long as the first version to lay out, consuming additional hours or days. With HiPer DevGen, the layout engineer can simply

er differential pair

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evices by a micron could introduce a mismatch into the device. HiPer DevGen instantly generated this device while simultaneous ng perfect matching between both devices.

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Figure Schematic of example with 17 functional devices Figure 7: Schematic of7:example circuit with 17circuit functional devices.

7 shows the schematic of a complete circuit with 17 functional devices. The top row of four transistors (two fingers in each device up of two current mirrors, the next row of four transistors (two fingers in each device) is made up of two differential pairs and th row of three transistors is another current mirror, comprising five gates in total.

Figure 8: LayoutFigure of example circuit with 17 functional devices. 8: Layout of example circuit with 17 functional devices

e 8 shows the layout of the same circuit shown in Figure 7. While they are not shown in the schematic, approximately ten du d also be required in order to ensure matching, bringing the total device count from 17 to 27.

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mber of analog layout engineers were asked how long it would take them to lay out this circuit, while obeying best la


PROJECT change a parameter and regenerate the structures that make up the design, completing the modifications in a matter of minutes. This acceleration in the design process makes it possible to reduce design cycle time by designing multiple parallel paths to see which one is best for any given circuit. For example, you might evaluate the ability of several different design alternatives to simulate the effects of artifacts such as LOD/STI or WPE. Conclusion HiPer DevGen increases analog layout productivity by accelerating the generation of devices and common analog structures. All cells are generated at a consistently high level of quality. Silicon quality, yield, silicon performance, and matching are as good as the best full custom layout engineer could produce and well above current fully automated layout generation. Design standards are the same for different designers and different projects. Re–targeting to new technology nodes is effortless.

About Tanner EDA Tanner EDA provides of a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs. Founded in 1988, Tanner EDA solutions deliver the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

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Episode 2.4

The DevCon Experience 22

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SPECIAL FEATURE

In this episode of MCU Wars, Jean Labrosse of Micrium and Richard Barry of FreeRTOS talk about their experiences at DevCon 2012 and what sets this convention apart from the others. This series was filmed at DevCon 2012 by Renesas in Anaheim, California. DevCon provides an environment for valuable technical information exchange and access to Renesas’ technology experts and partenrs from around the world. Visit www.eeweb.com

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EEWeb PULSE

How has your experience been at DevCon 2012?

We are very excited to be at DevCon. It’s a very unique conference—RichJean ard and I do a lot of conferences— and you can see that there’s a very personal approach at DevCon that we don’t typically see anywhere else, like having a concierge assigned to every attendee. Certainly, we are very excited to be here, especially considering we have worked with Renesas and created this Power of 2 promotion where all of our software is available for free for customers that are using an RX processor or an RL78 processor. There are no strings attached, you just have to decide to design a RX or RL78 processor before March 31st, 2013. This is a very comprehensive offering that is completely free (in the Americas).

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It’s been fantastic. I’ve been to conferences all over Europe and all Richard over America and I see Jean at all of them. The buzz on the floor has been great—I was on the stand yesterday and it’s always great to talk to people who are using your product to find out what they’re doing with it. One of the things with FreeRTOS is that there are thousands and thousands of users and most of the time I don’t know who they are, so I get a buzz from talking to these people. But the enthusiasm and genuine interest is notable—sometimes you go to a conference and the atmosphere is a bit flat, but here there’s a good buzz and Renesas makes some fantastic products.

SPECIAL FEATURE

“ It’s a very unique conference—Richard and I do a lot of conferences— and you can see that there’s a very personal approach at DevCon that we don’t typically see anywhere else.

” Continued in Episode 5... To view this episode of MCU Wars and other EEWeb videos:

Click Here Visit www.eeweb.com

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TECH ARTICLE ARTICLE TECH

Interfacing the Fundamental Component of the Internet of Things Roderick Bacon Intersil Corp

Part 2

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A buck-boost device such as the ISL9110 is a hybrid regulator that combines both operational characteristics of the buck and boost regulator architectures. The ISL9110, like other buck-boost regulators, can convert an input voltage that is higher than, equal to, and lower than the desired output voltage requirements of the application load. Figure 4 shows the simplified block diagram of the ISL9110 buck-boost regulator. Referencing the waveforms in Figure 4, the ISL9110 regulator in buck mode operation operates by driving the Q1 power transistor with a duty cycle ratio computed by dividing the on-time of the Q1 power transistor divided by the total period of a switching cycle. As with the buck regulator, the Q2 power transistor is the complementary of Q1. For the boost mode operation, referencing the waveforms in Figure 4, the ISL9110 operates by driving the Q4 power transistor with a duty cycle ratio computed by dividing the on-time of the Q4 power transistor divided by the total period of a switching cycle. As with the boost regulator, the Q3 power transistor is the complementary of Q4. Unlike with a typical buck or boot regulator, the ISL9110 has two extra power transistors (which operate in static L

VIN CIN

Coin Cell

IoT Emdedded Module Two Cell Alkaline

Q3

Q2

Q4

Partially: 3.3V minimum

power configurations). For buck mode operation, the Q3 power transistor is on at all times and the Q4 power transistor is off at all times. Conversely for boost mode operation, the Q1 power transistor is on at all times and the Q2 power transistor is off at all times.

OFF ON

ON

Q2

Q3

OFF

OFF

ON

Q3

Q2

ON OFF

Q4

OFF

DUTY CYCLE [D]= D=

ON[tON_Q1] Switching Period[TQ1]

tON VOUT = T VIN

Q1

DUTY CYCLE [D]= D=

ON[tON_Q4] Switching Period[TQ4]

tON VOUT –VIN = T VOUT

Figure 4: ISL9110 buck-boost regulator simplified block diagram, power transistor waveforms for each mode of operation, and duty cycle computation for each mode of operation.

30

RTC

Sensors

MEMS: Motion Sensing

Figure 5: The battery configuration options for the buck regulator for powering the 3.3V biased IoT embedded module

ON

OFF

µC

Three Cell Alkaline

Switching Period

Q4

GND

Partially: 1.1V per cell minimum

Boost Mode Operation

ON

Q1

Buck Regulator

Ambient Light/ Proximity Sensing

COUT

Switching Period

DRAM/FLASH DRAM/Flash

3.3V

Li-Ion/Polymer

Control Circuitry

Buck Mode Operation

Low Power RF Transceiver

VOUT

VIN +

VOUT

Q1

Power Interface

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The limitations of the switching regulator architectures are depicted in Figures 5, 6, and 7. Figure 5 shows the available battery choices for the buck regulator. The coin cell and two cell alkaline power sources are eliminated as choices for a 3.3V biased IoT embedded module, and the remaining battery options (Li-Ion/Polymer and three cell alkaline) can only be used partially since the minimum allowable voltage is 3.3V. Figure 6 shows the battery options available for a boost regulator for the same application conditions where the coin cell and two-cell alkaline are the only viable choices. Figure 7 illustrates how the ISL9110 buck-boost regulator allows for a much wider choice in battery technologies and configurations to interface for an IoT embedded module. As with all engineering choices there is a tradeoff with the ISL9110 buck-boost regulator compared with the buck and boost regulator architectures. The tradeoff is the added cost of the two extra power transistors but with the wider choice in input power choices the capability and


TECH ARTICLE

Coin Cell

Coin Cell

IoT Emdedded Module

IoT Emdedded Module

Power Interface

Power Interface Two Cell Alkaline

Two Cell Alkaline

Low Power RF Transceiver

Low Power RF Transceiver DRAM/FLASH DRAM/Flash

DRAM/FLASH DRAM/Flash

VIN +

VIN

VOUT 3.3V +

Boost Regulator µC

GND

ISL9110: Buck-Boost Regulator

RTC

VOUT

3.3V

µC

GND

RTC

Sensors

Sensors Li-Ion/Polymer

Li-Ion/Polymer Ambient Light/ Proximity Sensing

Ambient Light/ Proximity Sensing

MEMS: Motion Sensing

MEMS: Motion Sensing

Three Cell Alkaline

Three Cell Alkaline

Figure 6: The battery configuration options for the boost regulator for powering the 3.3V biased IoT embedded module

Battery Options

Buck-Boost

Buck

Boost

Coin Cell

YES

NO

YES

Two Cell Alkaline

YES

NO

YES

Li-Ion/Polymer

YES

~YES

NO

Three Cell Alkaline

YES

~YES

NO

Figure 7: The battery configuration options for the ISL9110 buck-boost regulator for powering the 3.3V biased IoT embedded module.

~YES: Partially, battery is not fully utilized.

Complete Battery Powered IoT Emdedded Module

ISL9110 Buck-Boost Regulator

Figure 8: Selection criteria table for various battery technologies and configurations options for a 3.3V biased IoT embedded module.

performance of the constructed embedded module can be enhanced above what can be offered with only a buck or boost regulator. To simplify the regulator selection criteria, Figure 8 summarizes which regulator architecture is optimal for a given battery technology and configuration option. The lower price of the standard buck and boost regulators, as compared with the ISL9110 buck-boost regulator, masks not only the cost of lost opportunities because of the limited battery options but also the extra cost of having to inventory separate module designs for the respective buck and boost regulators. The more capable ISL9110 buck-boost regulator allows for one embedded module design to participate in many market segments that the different battery options make possible. Figure 9 depicts a complete IoT embedded module configuration, which results in superior capability. The battery fuels the capability, i.e., operational longevity in the field or

Low Power RF Transceiver DRAM/FLASH DRAM/Flash

µC

RTC

Sensors

Ambient Light/ Proximity Sensing

MEMS: Motion Sensing

Figure 9: Complete IoT embedded module

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A VBATT

VIN

ISL9110: Buck-Boost Regulator

VOUT

3.3V

3.3V

GND

VDD AVDD

B VBATT

VIN

ISL9110: Buck-Boost Regulator

VOUT

3.3V

3.3V

VIN

GND

ISL9110: LDO Regulator

VOUT

3.3V–VDROPOUT

VDD AVDD

GND

Figure 10: A. ISL9110 connection scheme if an IoT embedded module component input voltage ripple is not critical for its analog circuitry. B. ISL9110 connection scheme (with the ISL9021A LDO) if an IoT embedded module component input voltage ripple is critical for its internal alnalog circuitry.

more powerful module components. It also provides the logistic simplicity offered by only having a single power interface option for a wide input voltage range (1.8V-to-5.5V for ISL9110). If any components in the embedded module have a requirement for low ripple on a separate input for powering internal analog circuitry, a small LDO like the ISL9021A can be used to decimate the regulator output ripple, as depicted in Figure 10, for the module component’s analog power input. The ISL9110 buck-boost regulator is the optimal choice for interfacing the power source with the most fundamental and critical component of the IoT infrastructure. This is due to the expansive choice in battery technologies for the modules that gather the data necessary for realizing the potential impact of the IoT revolution.

References: [1] Kevin Ashton, “That ‘Internet of Things’ Thing,” RFID Journal, 22 June 2009. (http://www.rfidjournal. com/article/view/4986) Retrieved 27 November 2012. [2] Elise Ackerman, “Could An Internet Of Things Startup Be The Next Microsoft? Three Hobby Kits Hold Promise,” Forbes (QUBITS blog), 4 November 2012. (http://www. forbes.com/sites/eliseackerman/2012/11/04/could-an-

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internet-of-things-startup-be-the-next-microsoft-threehobby-kits-hold-promise/) Retrieved 27 November 2012. [3] Bin Guo, Daqing Zhang, and Zhu Wang, “Living with Internet of Things: The Emergence of Embedded Intelligence,” IEEE International Conference on Internet of Things, and Cyber, Physical and Social Computing, 2011, pp. 297-304. [4] Steve Lohr, “Looking to Industry for the Next Digital Disruption,” The New York Times, 23 November 2012. (http://www.nytimes.com/2012/11/24/technology/ inter net/ge-looks-to-industry-for-the-next-digitaldisr uption.html?adxnnl=1&ref=stevelohr&adxn nlx=1354215868-ZSECTykr3eE1WWREYeeRYw) Retrieved 26 November 2012.

About the Author Roderick Bacon is a Staff Strategic Applications Engineer at Intersil. He joined Intersil in August of 2012. Prior to Intersil, and since 1999, he has held positions in IC design, applications, and product definition within power management. He received a BSEE in 1999 from the University of California at Davis (UC Davis).

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TECH ARTICLE

Get the Datasheet and Order Samples http://www.intersil.com

Low Voltage ORing FET Controller ISL6146

Features

The ISL6146 represents a family of ORing MOSFET controllers capable of ORing voltages from 1V to 18V. Together with suitably sized N-channel power MOSFETs, the ISL6146 increases power distribution efficiency when replacing a power ORing diode in high current applications. It provides gate drive voltage for the MOSFET(s) with a fully integrated charge pump.

• ORing Down to 1V and Up to 20V with ISL6146A, ISL6146B, ISL6146D and ISL6146E

The ISL6146 allows users to adjust with external resistor(s) the VOUT - VIN trip point, which adjusts the control sensitivity to system power supply noise. An open drain FAULT pin will indicate if a conditional or FET fault has occurred. The ISL6146A and ISL6146B are optimized for very low voltage operation, down to 1V with an additional independent bias of 3V or greater. The ISL6146C provides a voltage compliant mode of operation down to 3V with programmable Undervoltage Lock Out and Overvoltage Protection threshold levels The ISL6146D and ISL6146E are like the ISL6146A and ISL6146B respectively but do not have conduction state reporting via the fault output. TABLE 1. KEY DIFFERENCES BETWEEN PARTS IN FAMILY PART NUMBER

KEY DIFFERENCES

ISL6146A

Separate BIAS and VIN with Active High Enable

ISL6146B

Separate BIAS and VIN with Active Low Enable

ISL6146C

VIN with OVP/UVLO Inputs

ISL6146D

ISL6146A wo Conduction Monitor & Reporting

ISL6146E

ISL6146B wo Conduction Monitor & Reporting

+

VOLTAGE DC/DC (3V - 20V)

VIN GATE VOUT BIAS ADJ ISL6146B FLT GND

EN

Q2 +

VOLTAGE DC/DC (3V - 20V)

VIN GATE VOUT VOUT BIAS ADJ ISL6146B FLT GND

EN

-

FIGURE 1. TYPICAL APPLICATION

October 5, 2012 FN7667.3

• VIN Hot Swap Transient Protection Rating to +24V • High Speed Comparator Provides Fast <0.3µs Turn-off in Response to Shorts on Sourcing Supply • Fastest Reverse Current Fault Isolation with 6A Turn-off Current • Very Smooth Switching Transition • Internal Charge Pump to Drive N-channel MOSFET • User Programmable VIN - VOUT Vth for Noise Immunity • Open Drain FAULT Output with Delay - Short between any two of the ORing FET Terminals - GATE Voltage and Excessive FET VDS - Power-Good Indicator (ISL6146C) • MSOP and DFN Package Options

Applications • N+1 Industrial and Telecom Power Distribution Systems • Uninterruptable Power Supplies • Low Voltage Processor and Memory • Storage and Datacom Systems

+

Q1

• Programmable Voltage Compliant Operation with ISL6146C

C O M M O N P O W E R

GATE FAST OFF, ~200ns FALL TIME ~70ns FROM 20V TO 12.6V ACROSS 57nF GATE OUTPUT SINKING ~ 6A

B U S +C O M M O N P O W E R B U S

FIGURE 2. ISL6146 GATE HIGH CURRENT PULL-DOWN

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2011, 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.


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