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Issue 13

September 27, 2011

Dr. Aaron Franklin Integrating Carbon Nanomaterials

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TA B L E O F C O N T E N T S TABLE OF CONTENTS

4

Dr. Aaron Franklin RESEARCH STAFF MEMBER AT IBM’S T. J. WATSON RESEARCH CENTER Interview with Dr. Aaron Franklin

8

Replacing Silicon with Carbon Nanotubes BY DR. AARON FRANKLIN Franklin highlights IBM’s motivation for considering carbon nanotubes for a future low-voltage, high-performance computing technology.

Featured Products

12

Zero Power Wireless Sensor Using Energy Processing

13

BY STEVE GRADY WITH CYMBET Cut the power cord forever using a solution that harvests the ambient energy around the wireless sensor device.

19

Is Your FPGA Design Reusable? A Design Checklist BY PHIL SIMPSON WITH ALTERA

Simpson provides a referential checklist for creating a design reuse policy for engineering teams developing reusable FPGA designs.

RTZ - Return to Zero Comic

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INTERVIEW

Franklin IBM’s T. J. Watson Research Center How did you get into engineering and when did you start? When I was about 12 years old, two electrical engineers from Motorola visited my school in Phoenix, AZ. Their descriptions of fabricating electronic components in clean rooms and how they suit up and go through air showers fascinated me. It sounded like a stable, exciting and respectable career and I decided right then to go for it. Over the years, my perspective on the specifics of my career path changed, but I never lost the passion for electrical engineering. During my time as an engineer at Intel, and most recently now as a scientist at IBM, I have participated in science/engineering outreach programs at local schools to try and provide the same spark of lasting interest to other students that those engineers provided for me those many years ago.

for future technologies. Working with nanoscale components means spending a lot of time with electron microscopes and material characterization equipment. My personal favorite is the scanning electron microscope (SEM). My experience using the SEM enables me to quickly image components such as carbon nanotubes, which are only a single atomic layer thick and approximately one nanometer in diameter (10 atoms across!). Also among my favorite tools is

What are your favorite software tools that you use? As a researcher that needs to keep up with the latest scientific publications, I have found using an RSS reader to be invaluable. Most science and engineering journals provide RSS feeds of new, updated content. The RSS reader does all of the searching and sorting for me so that I don’t have to stare blearyeyed at the table of contents for each of the 30-plus journals that I follow. The free reader I use is called NetNewsWire. Also worth mentioning is the free software called Mendeley. It is incredible for organizing research papers in a very accessible, searchable format.

Dr. Aaron Franklin - Research Staff Member at IBM’s T. J. Watson Research Center

What are your favorite hardware tools that you use? I work with nanomaterials to fabricate nanoelectronic devices, such as field-effect transistors,

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FEATURED INTERVIEW

Dr. Aaron

the electron-beam evaporator that I designed and built here at IBM. Evaporators are fairly standard tools for depositing thin films of pure materials (such as gold and titanium), but I specially designed this one for providing exceptionally fast turnaround time at ultrahigh vacuum.


INTERVIEW

What is the hardest/trickiest bug you have ever fixed? It has been my experience that the problems that appear to be the trickiest often turn out to be the ones with the simplest solution. For instance, during my Ph.D. work we ran into an issue with the electrochemical process we were using to create porous aluminum oxide templates. After weeks of troubleshooting the “most probable” causes for the process failure, we finally decided to try using new copper tape, which connects the chip to an alligator clip-style electrode. While it seemed too simplistic for the simple copper tape we’d been using to expire, it proved to be an incontestable fix. From this, and many similar experiences, I have learned to try the simple things first when resolving tricky challenges in the lab. What is on your bookshelf? Everything from Quantum Mechanics by Griffiths to Modern VLSI Devices by Taur and Ning. A

better question would be, “Which books on your shelf do more than just decorate your office?” The answer to that would be Semiconductor Material and Device Characterization by Schroder, Physics of Semiconductor Devices by Sze, and Quantum Transport by Datta. Each of these books is littered with sticky note markers.

... problems that appear to be the trickiest often turn out to be the ones with the simplest solution. Do you have any tricks up your sleeve? In my area, any number of conditions can affect the performance of devices. Therefore, I have found it imperative when trying a new experiment to begin step one with several chips that are processed in parallel. This redundancy, while slightly more time consuming, has proven to enable a very high level of efficiency in my experimental work. By strategically leaving the companion samples at certain steps of the process, they can serve as quick workarounds when the leading chip fails. I’m not sure about anyone else, but things don’t typically work for me the first time!

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What has been your favorite project? Speaking of things working the first time—one of my favorite projects is the one that actually did! An idea came to me on a Friday for a technique of achieving nanoparticle decoration of different metals to selective regions of a substrate. I had one chip already available to try the idea out and sped through the processing early the following week. By the next Wednesday, the results (precisely as I had anticipated them) were staring me in the face. I wrote the paper Thursday and sent it around to my colleagues on Friday to prepare for submission to a journal, just one week following the inception of the idea. That was a one in a thousand type of experience for me to be sure. Do you have any note-worthy engineering experiences involving destruction? I’ve had my share of fun playing with liquid nitrogen, but outside of that I try and avoid such experiences! What are you currently working on? I currently am working on integrating carbon nanomaterials (nanotubes and graphene) into transistors that can provide a unique performance advantage over projected silicon technology. For instance, carbon nanotubes allow for transistors to be scaled down to even smaller dimensions than silicon, without incurring the deleterious impact of high power dissipation. Furthermore, both nanotubes and graphene can be used in transparent and/or flexible

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FEATURED INTERVIEW

Mendeley even provides seamless citation capabilities with popular word processing software, such as Microsoft Word. Most colleagues that I show NetNewsWire and Mendeley to end up converting to both of them and save many hours of time each week. I don’t spend too much time with engineering software, but I have really come to enjoy Google Sketchup (free version). I’ve done everything from a full CAD design of an electronbeam evaporator that I built, to simple schematics for devices that I am fabricating. Overall, I suppose I’m a free software junkie!


INTERVIEW

One of the great things about my current job at IBM is the flexibility to pursue other interests on the side. Most recently, I have begun working on using nanomaterials to enhance the performance of supercapacitors (also called ultracapacitors or electric double-layer capacitors), which are vital components for such energy solutions as solar and wind power.

What challenges do you foresee in our industry? I can only answer this from the perspective of the nanoscale transistor community—my primary area of expertise. While new materials to replace silicon in metaloxide-semiconductor field-effect transistors (MOSFETs) have been studied for decades, we are seeing a more sober approach toward using them in the near future. Frankly, the standard bulk silicon devices cannot be scaled down any smaller than they now are, hence, Intel’s recent move to the new ‘3D’ (trigate) fin structures for the 22 nanometer

technology node. To continue pushing the performance limit for integrated circuits, I foresee a more technology-minded approach to researching materials for siliconreplacement. In conjunction, I also believe that the market for more exotic applications using flexible and/or transparent electronics is going to blossom and provide a new wave of electronics that will be quite unique from the current computing generation.■

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FEATURED INTERVIEW

substrate applications—opening the capability for some very new and exciting electronic device applications.


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PROJECT

Why it’s Still Worth Considering Since the inception of silicon (Si) in the 1960s as the principal material for fabricating integrated circuits, there has been interest in replacing it with a more ideal semiconductor. Dominating the various arguments for replacing Si is the imminent unfeasibility of further scaling (i.e., miniaturizing, shrinking) silicon metal-oxide-semiconductor field-effect transistors (MOSFETs)— the fundamental device of integrated circuits. Transistor scaling is driven by the desire to increase the density of transistors on a chip, thereby amplifying computing performance. Single-walled carbon nanotubes (CNTs)—consisting of a single atomic layer of hexagonallyarranged carbon atoms rolled into seamless cylinders of 1-2 nanometer diameter—have been among the foremost options for a Si replacement. This article briefly highlights the motivation for current projects at IBM that continue to consider CNTs for a future low-voltage, high-performance computing technology. Death of Moore’s Law for Si In a 1965 research paper, one of Intel’s eventual founders, Gordon Moore, made an observation and projection

regarding the rate of transistor scaling—his simple prediction actually became an industry-driving edict, known as “Moore’s Law.” Briefly, the law states that the number of transistors on a chip will double approximately every two years (the timeframe has changed a few times between one and two years), as shown in the Figure 1 plot. While continued innovation has kept the Si MOSFET in stride with Moore’s prediction, it is becoming more widely accepted that the end is close at hand—even within the next few years. What’s most interesting is that the end of Si MOSFET scaling will not necessarily be caused by the inability to fabricate smaller transistors; rather, it is that the scaled transistors operate so poorly and at too high of power. As John Markoff in a recent New York Times article noted, “The problem is not that they cannot squeeze more transistors onto the chips—they surely can—but instead, like a city that cannot provide electricity for its entire streetlight system, that all those transistors could require too much power to run economically.” [1]

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By Dr. Aaron Franklin

In fact, it is safe to say that Moore’s Law, as it was seen for the first forty years, has been dead for more than a decade now. As seen in Figure 1, deviation from the law has become common practice to meet specific application needs (high or low power/ performance). Additionally, the push for faster and more efficient computing is no longer primarily tied to transistor scaling, but is becoming more and more stressed at the architectural level (e.g., multicore processors). Why Carbon Nanotubes? The struggle to keep Si in stride with projected transistor scaling is increasingly evident. The most recent major transition to keep Si alive [2] is a shift from planar devices to 3D fin (or trigate) structures for the 2012 technology. However, even if the Si fin is followed by the Si nanowire, the scaling limits for both gate length (around 10 nm) and supply voltage (around 0.8 V)—both key metrics to reduce for future technology nodes—have little hope of being overcome. It is true that doomsayers of Si have been around for years and innovation has continually managed to prove them wrong; but

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FEATURED PROJECT

Replacing Silicon with Carbon Nanotubes


PROJECT

One of the fastest growing application areas is low-power computing, wherein the supply voltage matters more than the transistor count, even at the cost of performance. Nanotube channels have shown the ability to operate better than any other demonstrated material at low voltages, making them a prime candidate for increasing transistor count even for low-power applications. However, the potential application space for CNTs is not limited to low power. The unmatched currentcarrying capacity of nanotubes makes them equally as attractive for highperformance computing applications. Furthermore, there is an application space that to date is uncharted by commercial integrated circuits: flexible and/or transparent electronics. With nearly perfect transparency to visible light, high mechanical flexibility, and complete substrate independence, nanotubes lend themselves to a

1010

High-power applications Standard applications Low-power applications

?

108 107 106

100

Power Dissipation

# Transistors on a Chip

109

FEATURED PROJECT

with each innovation, the fundamental shortcomings of Si have become more apparent and increasingly more difficult to resolve. Consider the plot of power dissipation in the inset of Figure 1. We’ve reached the point where the static power (when a transistor is in the off-state) has become more costly than dynamic (on-state) power; this phenomenon is known as a leaky transistor and is largely a result of losing control over the current in a device at extremely small dimensions. For CNTs, where the channel body thickness is only approximately one nanometer (10 atoms), the transistor gate can control the current in the channel much more effectively, even when dimensions are aggressively downsized. This benefit can make for a more promising future trend in dynamic and static power dissipation, potentially lowering both curves seen in the Figure 1 inset.

105 104

1

Dynamic

0.01 -104

Static 2000

103 1970

1980

1990

2000

2010 Year

2010

? 2020

2020

Year Figure 1: Number of transistors on a chip versus year of introduction, with transistor count doubling approximately every two years (known as Moore’s Law). Each data point denotes a particular chip technology. Inset shows how the normalized total power dissipation scales with technology generations, yielding a serious power problem.

myriad of exotic applications that simply could not be realized with bulk semiconductors like Si. IBM’s Efforts Toward a CNT Technology All of the promising attributes of a future CNT digital technology do not come without some substantial challenges. Foremost of the obstacles is the difficulty of placing nanotubes in precise locations with a consistent pitch. Attention to this problem has grown in the past few years, but much work remains to reach the goal of at least 100 CNTs per micron. Second is the need for improved material quality control. Because nanotubes can be semiconducting or metallic, obtaining material that is as close to 100 percent semiconducting as possible is a must (at IBM, we can reach 99.3 percent and counting). Finally, there is the need for improvements in the CNT transistor itself: optimized contacts, self-aligned gate structure, appropriate passivation layers, et cetera.

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Despite the work that remains, it is amazing that CNT transistors have come so far in just over 13 years. Tremendous advancements have been made in both controlling the material and understanding/improving the device. Comparing the progress in CNT technology to that of the early bulk semiconductors is rather remarkable, as shown in Figure 2. Early development of transistor technology was a completely uncharted path, relying on the unpredictable advancements that occurred in the field. When Moore’s Law came along, progress in the integrated circuit world began its march on a predetermined path. Since 1998, this path has been devised by a group called the International Technology Roadmap for Semiconductors (ITRS), which maps out the needed deliverables (e.g., device dimensions, performance) for technologies that are up to 15 years out [3]. Therefore, CNT transistors can’t just be better than the current Si MOSFETs; rather, they must work

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PROJECT Bulk Semiconductor

Early Integration

1947

1958

2001

2011

Carbon Nanotubes

At the IBM T. J. Watson Research Center, we are uniquely staffed and equipped to take on the remaining hurdles to a CNT technology. In-house, we synthesize, purify, and isolate large quantities of semiconducting CNTs. Strategies for improving precision in placement of the nanotubes onto 200 mm wafers are under intense study. We also continue to improve our understanding of CNT transistor performance and scaling limits, including the optimization of a technologically viable device structure. Does all of this mean we guarantee CNTs on the integrated circuit roadmap in the next few years? No. But what it does guarantee is that we will soon have a definitive answer regarding whether or not a CNT transistor technology is possible and practical enough to drive the next revolution in digital computing.

Early Transistor

FEATURED PROJECT

significantly better than any achievable Si device in order to justify the overhead cost of transitioning to a new platform. This is what we are working to determine right now at IBM.

Figure 2: Early development of bulk semiconductor transistor technology compared to development in carbon nanotube technology. Pictures of the first demonstrated transistor (1947) and one of the first demonstrated integrated circuits (1958) are from http://www. computerhistory.org. Scanning electron microscope images of CNT devices are from work at IBM (the bright lines are CNTs), showing how far integration of nanotubes has come from random dispersion (2001) to parallel alignment (2011). The bottom right images are of fully integrated ring oscillators with multiple nanotube channels in each transistor.

References [1] http://www.nytimes. com/2011/08/01/science/01chips. html?pagewanted=1&_ r=2&ref=science [2] http://newsroom.intel. com/docs/DOC-2032 [3] http://www.itrs.net/ â– 

Figure 3: Schematic image of carbon nanotube transistor with multiple channels.

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Get the Datasheet and Order Samples http://www.intersil.com

Low-Noise 24-bit Delta Sigma ADC ISL26132, ISL26134

Features

The ISL26132 and ISL26134 are complete analog front ends for high resolution measurement applications. These 24-bit Delta-Sigma Analog-to-Digital Converters include a very low-noise amplifier and are available as either two or four differential multiplexer inputs. The devices offer the same pinout as the ADS1232 and ADS1234 devices and are functionally compatible with these devices. The ISL26132 and ISL26134 offer improved noise performance at 10Sps and 80Sps conversion rates.

• Up to 21.6 Noise-free bits.

The on-chip low-noise programmable-gain amplifier provides gains of 1x/2x/64x/128x. The 128x gain setting provides an input range of ±9.766mVFS when using a 2.5V reference. The high input impedance allows direct connection of sensors such as load cell bridges to ensure the specified measurement accuracy without additional circuitry. The inputs accept signals 100mV outside the supply rails when the device is set for unity gain.

• On-chip temperature sensor (ISL26132)

• Low Noise Amplifier with Gains of 1x/2x/64x/128x • RMS noise: 10.2nV @ 10Sps (PGA = 128x) • Linearity Error: 0.0002% FS • Simultaneous rejection of 50Hz and 60Hz (@ 10Sps) • Two (ISL26132) or four (ISL26134) channel differential input multiplexer • Automatic clock source detection • Simple interface to read conversions • +5V Analog, +5 to +2.7V Digital Supplies • Pb-Free (RoHS Compliant) • TSSOP packages: ISL26132, 24 pin; ISL26134, 28 pin

Applications

The Delta-Sigma ADC features a third order modulator providing up to 21.6-bit noise-free performance.

• Weigh Scales

The device can be operated from an external clock source, crystal (4.9152MHz typical), or the on-chip oscillator.

• Temperature Monitors and Controls

The two channel ISL26132 is available in a 24 Ld TSSOP package and the four channel ISL26134 is available in a 28 Ld TSSOP package. Both are specified for operation over the automotive temperature range (-40°C to +105°C).

• Pressure Sensors

• Industrial Process Control

CAP

AVDD

DVDD

INTERNAL CLOCK

EXTERNAL OSCILLATOR

XTALIN/CLOCK XTALOUT

AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3-

SDO/RDY INPUT MULTIPLEXER

PGA 1x/2x/64x/ 128x

ADC SCLK

ISL26134 Only AIN4+ AIN4PWDN

SPEED

A0

A1/TEMP AGND

GAIN0 GAIN1

CAP

DGND

VREF+

VREF-

DGND

DGND

NOTE for A1/TEMP pin: Functions as A1 on ISL26134; Functions as TEMP on ISL26132

FIGURE 1. BLOCK DIAGRAM

September 9, 2011 FN6954.1

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2011 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.


F E AT U R E D P R O D U C T S Silicon Laboratories Inc., a leader in high-performance, analog-intensive, mixed-signal ICs, introduced a family of digital isolators that offers the highest channel count, performance and data rate for demanding applications with isolation ratings up to 5 kV. The new Si86xx 3.75 kV and 5 kV digital isolators replace optocouplers in target applications requiring robust operation and high levels of insulation protection such as industrial automation and drives, motor control and medical systems. With its 5 kV rating, the Si86xx family offers an ideal isolation solution for systems powered from 220 Vac mains supplies such as isolated ac-dc and dc-dc power supplies, as well as solar panel microinverters, data communications systems and hybrid electric vehicles (HEVs).system reliability. The IGBTs are co-packaged with a low forward-voltage high peak current soft forward-recovery diode optimized for resonant zero current turn-on operation. For more information, please visit: http://www.silabs.com/pr/isolation

Signal Generator up to 40 GHz Rohde & Schwarz has enhanced its analog R&S SMB100A mid-range signal generator by adding new frequency options. The R&S SMBB120/B120L and R&S SMB-B140/B140L options (L versions without step attenuator) enable the generator to cover the frequency range from 100 kHz to 20 GHz and 40 GHz, respectively. The R&S SMB100A can now handle everything from analog RF to microwave applications. In the new frequency ranges, the R&S SMB100A still offers a very wide dynamic range of -120 dBm to +14 dBm as standard. New high power options – the R&S SMB-B31 (for the 20 GHz model) and the R&S SMBB32 (for the 40 GHz model) – make it possible to achieve an output power of max. +25 dBm. The new options allow users to skip the practice of looping in an external amplifier to achieve higher output power. For more information, please visit Rohde & Schwartz.

iPad Spectrum Analyzer for 2.4GHz ISM Band Oscium unveiled a breakthrough product line for the iOS Test industry that enables iPad, iPod touch, and iPhone to now become either a spectrum analyzer or a dynamic power meter…or both. Oscium’s first-to-market product, iMSO-104, successfully merged a mixed signal oscilloscope and the iOS family of products using the 30-pin dock connector. The contribution was so significant that Cypress Semiconductor Corp heralded the product as ‘revolutionary’. Oscium’s new product line, called WiPry, is the next installment in modular test equipment. This new category of test equipment has the potential to change the benchtop dominated landscape by establishing the touchscreen-based iPad (or iPhone, iPod touch) as the new user interface. This platform presses the refresh button on the antiquated buttons and knobs of benchtop instruments while at the same time offering mobility that PC-based instruments can’t match. For more information, please visit: http://www.oscium.com/

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FEATURED PRODUCTS

Six-Channel 5 kV Digital Isolators


Zero Power

Wireless Sensors Using Energy Processing Steve Grady VP Marketing

The Evolution of Sensor Networks Sensors networks are gaining widespread use in factories, industrial complexes, commercial and residential buildings, agricultural settings, and urban areas, serving to improve manufacturing efficiency, safety, reliability, automation, and security. These networks perform a variety of useful functions including factory automation, measurement, and control— control of lighting, heating, and cooling in residential and commercial buildings— structural health monitoring of bridges, commercial buildings, aircraft, and machinery— tire pressure monitoring systems (TPMS), tank level monitoring, and patient monitoring in hospitals and nursing homes. To date, almost all sensor networks use wired connections for data communications and power. The cost of installing a sensor network using copper wire, conduit, along with the support infrastructure, has become extremely cost-prohibitive. There are new emerging solutions using various wireless protocols

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such as ZigBee Green Power, Bluetooth LE, and 6LowPAN to network sensor devices and eliminate the data communications wiring. However, the wireless sensors still need to be powered. Using batteries such as AA cells has been used as a solution. But these batteries wear out and changing them out is often an expensive proposition. OnWorld Research has estimated that this battery change-out cost will approach $1 Billion in 2013. What is needed is a solution that harvests the ambient energy around the wireless sensor device and we can cut the power cord forever. Zero Power Wireless Sensors are the Solution Wireless Sensor Networks (WSNs) is the term that is used for wireless sensor and control networks that use batteries or Energy Harvesting techniques to power the device. With the availability of low cost integrated circuits to perform the sensing, signal processing, communication, and data collection functions, coupled with the versatility that wireless networks afford, we can

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TECHNICAL ARTICLE 4. A microcontroller or variant thereof, to receive the signal from the sensor, convert it into a useful form for analysis, and communicate with the radio link.

One drawback to moving toward a wireless network installation has been the poor reliability and limited useful life of batteries needed to supply the energy to the sensor, radio, processor, and other electronic elements of the system. This limitation has, to some extent, curtailed the proliferation of wireless networks. The legacy batteries can be eliminated through the use of Energy Harvesting techniques which use an energy conversion transducer tied to an integrated rechargeable power storage device. This mini “power plant� lasts the life of the wireless sensor.

5. A radio link at the sensor node to transmit the information from the processor on a continuous, periodic, or eventdriven basis to a host receiver and data collection point.

A Zero Power Wireless Sensor as shown in Figure 1 typically consists of five basic elements: 1. A sensor to detect and quantify any number of environmental parameters such as motion, proximity, temperature, pressure, pH, light, strain, vibration, and many others. 2. An energy harvesting transducer that converts some form of ambient energy to electricity. 3. An Energy Processor to collect, store, and deliver electrical energy to the electronic or electro-mechanical devices resident at the sensor node. Light Heat Motion

Transducer

Photovoltaic Thermoelectric Piezoelectric Inductive RF

Traditional power sources for wireless sensors have typically been a primary (i.e., non-rechargeable) battery such as AA or AAA alkaline cells, lithium thionyl chloride, lithium coin cells, or a host of other chemistries. But there is another way of providing the power source: harvesting the ambient energy surrounding the sensor device. Energy Harvesting delivers the necessary power and energy to operate the sensor node and, further, does not require battery maintenance during the operational life of the sensor node. In effect, Energy Harvesting enables perpetual sensors. Energy Harvesting transducers are a source of power that is regularly or constantly available. This power source could come in the form of a temperature differential, a vibrational source such as an AC motor, a radiating or propagating electromagnetic wave, or a light source, as examples. Any of these power sources can be converted to useful electrical energy using transducers designed to convert one of those forms of power to electrical power.

Microcontroller and Radio Link Ultra Low Power RF Wireless Optimized Protocol

EZ430-RF2500

Sensor

EM Field

Energy Processor

Power Conversion Energy Storage Power Management

Solid State Energy Storage

Figure 1: Zero Power Wireless Sensor Diagram

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TECHNICAL ARTICLE

move away from fixed, hard-wired network installations in both new construction as well as retrofits of existing installations.


TECHNICAL ARTICLE Typical Voltage

Typical Power Output

Conform to small surface area: wide input voltage range

Varies with light input - Low kΩ to 10s of kΩ

DC: 0.5V to 5V (Depends of # of cells in array)

10uW-15mW (Outdoors: 0.15mW-15mW Indoors: <500uW)

Vibrational

Variability of vibrational frequency

Constant impedance 10s of kΩ to 100kΩ

AC: 10s of volts

1uW-20mW

Thermal

Small thermal gradients; efficient heat sinking

Constant impedance 1Ω to 100s of Ω

DC: 10s of mV to 10V

0.5mW-10mW (20ºC gradient)

Coupling and rectification

Constant impedance Low kΩs

AC: Varies with distance and power 0.5V to 5V

Wide range

Challenge

Light

RF & Inductive

TECHNICAL ARTICLE

Typical Electrical Impedance

Energy Source

Figure 2: Energy Harvesting Transducer Comparisons

The following transducers are the most common as shown in Figure 2: • Photovoltaic: also known as solar— converts light to electrical power • ElectroStatic or ElectroMagnetic: converts vibrations • Thermoelectric: converts a temperature differential to electrical power • Piezoelectric: converts a mechanical movement to electrical power • RF and Inductive: converts magnetic power to electrical power The efficiency and power output of each transducer varies according to transducer design, construction, material, operating temperature, as well as the input power available and the impedance matching at the transducer output. New Energy Processors and Solid State Batteries Are Now Available Zero Power Wireless Sensors require energy processing low power management circuitry to condition the transducer output power, store energy, and deliver power to the rest of the wireless sensor. In most environments, any of transducers producing power cannot be relied on under all circumstances to continuously supply power to the load. While each transducer delivers power at some amplitude and with some regularity, they do not

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store energy. Consequently, when that source of power is not present, there would be no power to supply the load in the absence of an energy storage device. Moreover, the transducers typically do not deliver power at the proper voltage to operate the electronic system. Therefore, conditioning of transducer power is essential to making the power useful in operating the sensor, processor, and transmitter. In particular, without an energy storage device, it would be difficult or impossible to deliver the pulse current necessary to drive the wireless transmitter. Traditional rechargeable energy storage devices such as supercaps and coin cell batteries have severe limitations with respect to charge/ discharge cycle life, self-discharge, and charge current and voltage requirements. An Energy Processor, such as Cymbet’s EnerChip™ EP CBC915, provides all of the energy conversion, energy storage, and load power management for the Zero Power Wireless Sensor. In order to produce high-efficiency transducer energy conversion, the Energy Processor performs maximum peak power tracking by emulating the impedance of the transducer. The Energy Processor also coordinates all the power up sequencing even from a dead start with no charge in the system. The Energy Processor also provides power and energy status information to the Microcontroller so the system can be made “Energy Aware.” Figure 3 shows the EnerChip EP Energy Processor and EnerChip solid state batteries on the EVAL-09 Universal Energy Harvesting kit. This kit interfaces to any type of EH transducer, converts and

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TECHNICAL ARTICLE

Zero Power Wireless Sensor Evaluation Kits Figure 3: Cymbet EVAL-09 EnerChip EP Universal Energy Harvesting Kit

stores the harvested energy, and provides a regulated output voltage to a target system. The Energy Processor performs several useful â&#x20AC;&#x153;Energy Awareâ&#x20AC;? functions, including handshaking features for communication with the microcontroller. A detection circuit determines whether enough power is available from the transducer to operate the system. If so, the microcontroller receives a signal indicating that the power module is operating normally. If insufficient power is available, a signal alerts the microcontroller to go into a low power mode and, if so programmed, send a signal to the wireless radio to alert the access point accordingly. There is also a control line that allows the user to disconnect the EnerChip from the circuit in order to use all available input power to operate the system, rather than diverting some of the power to the EnerChip to charge the cell. Microcontroller, Sensor, and Wireless Radio The output of the sensor is typically connected to a microcontroller that processes the signal created from measuring the parameter of interest (e.g., temperature, pressure, and acceleration) and converts it to a form that is useful for data transmission, collection, and analysis. Additionally, the microcontroller usually feeds this information to the radio and controls its activation at some prescribed time interval or based on the occurrence of a particular event. It is important that the microcontroller and radio are operating in low power modes whenever possible in order to maximize the power source lifetime. Depending on the quiescent current of the radio and microcontroller, the transmitter power and duty cycle, and the complexity and duration of any signal processing required, the drain on the power source can be dominated by steady state or active power consumption. Power consumption can

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All of the elements described in the previous sections have been combined into autonomous perpetual wireless sensor evaluation kits. Figure 3 shows the EVAL09 kit and Figure 4 shows the new Cymbet EnerChip CC Solar Energy Harvesting EVAL-10 kit combined with the Texas Instruments eZ430-RF2500 wireless evaluation kit to create a solar-based EH wireless temperature sensor. In this case, the on-board EnerChip CC CBC3150

Figure 4: Cymbet EVAL-10 Solar EH Kit with TI eZ430RF2500 Wireless Kit

provides the energy processing functions and the solid state battery energy storage. Conclusion Wireless sensor systems are becoming more prevalent due to the rising installation costs of hard-wired sensor systems, availability of low cost sensor nodes, and advances in sensor technology. Energy Harvestingbased autonomous wireless sensor nodes are a costeffective and convenient solution. The use of Energy Harvesting removes one of the key factors limiting the proliferation of wireless nodesâ&#x20AC;&#x201D;the scarcity of power sources having the characteristics necessary to deliver the energy and power to the sensor node for years without battery replacement. Significant economic advantages

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also be reduced through microcontroller firmware algorithms that efficiently manage power up and power down sequences, analog-to-digital conversions, and event-driven interrupts.


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About the Author Steve Grady is responsible for all strategic messaging, product roadmap, CRM, e-initiatives, collateral and

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lead generation at Cymbet. He has more than two decades of domestic and international experience in marketing, sales, business development, product management, engineering, and general management in the networking, hardware, and software industries. Steve has been in both startup and large company environments with global scope. Prior to joining Cymbet, Steve held senior management and technical positions at ADC, Marconi, TimeSys, Reltec, and AT&T Bell Labs. He holds BSEE and MSEE degrees from the University of Illinois Champaign-Urbana. â&#x2013; 

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are realized when Zero Power Wireless Sensors are deployed versus hard-wired solutions. Additional savings are realized by removing the significant costs of battery replacement. Combining Energy Harvesting transducers, an Energy Processing Power Module, low power sensor, an energy-aware Microcontroller, and an optimized RF Radio link delivers the reality of long life, maintenance-free Zero Power Wireless Sensor Networks.


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Is Your FPGA Design Reusable? A DESIGN CHECKLIST

Phil Simpson

Sr. Manager, SW Product Planning

D

esign and intellectual property (IP) reuse can improve the quality of your FPGA design, shorten your design and verification cycle and allow faster time-to-market. However, creating IP for design reuse comes at a cost: there is extra effort involved in making a design reusable. If design engineers do not see the value that design reuse provides, why expend the effort in making a design block reusable? Formal development policies within a company can help to establish a design reuse methodology across a company. After the initial challenges in implementing a design reuse process on the first project, the benefits will become apparent on future projects. The following checklist is a good starting point for creating a design reuse policy and can be used as a reference by engineering teams developing reusable FPGA designs. 1. The IP specification lists the requirements and details the feature set, performance expectations, size, usage model, etc. Not all design blocks need to be reusable, the specification must

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state whether a design is being architected as a reusable block. 2. The specification has been officially reviewed by all interested parties. This increases the likelihood that the design block can be reused elsewhere in the company. 3. Existing libraries of components have been reviewed to identify if existing IP with similar functionality already exists, i.e. practice reuse in the development process. 4. The IP core name follows your companyâ&#x20AC;&#x2122;s naming conventions. The name of the core should be description of designs function, e.g. AXI4 Clock Crossing Bridge. 5. Signal and parameter naming conventions are followed. Signal and parameter names should be descriptive of the functionality. This makes it easier for end users to understand the impact of these parameters and signals on the design block.

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7. The IP uses standard interfaces. Adopt a common interface protocol on all of IP. The use of standard interfaces simplifies the interconnection and management of functional blocks that make up a design. It ensures compatibility between IP blocks from different design teams, simplifies the integration of individual design blocks into a full system design and enables “plug and play” interoperability of IP. 8. The IP core meets the timing specification and all timing violations have been addressed. The IP core includes a full set of timing constraints. 9. The IP passes LINT tests per your company’s established coding rules. It is recommended that you invest in a LINT to enforce coding guidelines and that it is fully integrated with version control/ design check in process. 10. The verification of the IP meets the functional, assertion, and line coverage goals as specified in the test plan. Note that the test plan should be developed at the same time as the functional specification for the design. 11. The IP is adequately tested to cover the parameterization space and both expected and unexpected data patterns. Users of IP tend to be suspicious of other peoples design. There’s nothing gained in debugging someone else’s code. 12. Provide a user interface and/or script for end users to instantiate the IP in their design. The interface should make it easy for the user to understand any applicable constraints. At a minimum, the IP should come with a documented command-line script that enables users to pass values to the parameters in the IP. Ideally it should come with a simple graphical user interface (GUI) to help users get started (see Figure 1).

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13. Design files and all packaging files adhere to your company’s standard version-control directory structure. If users know where the applicable files are located, it provides the user with confidence that the designer of the IP has thought through the process of reuse. 14. Testbench and reference designs are available for use with the core. This is a “nice to have” feature that provides new users an easy way to get started with a design. 15. IP cores, example designs and test benches can be simulated in company simulators. Users should be able to run the scripts and see the basic functionality of the design. 16. Release notes detail all supported devices, FPGA device families, and versions of the EDA tools used on the design. Now ask yourself, is your FPGA design reusable? Further details on creating reusable FPGA designs are available in the book FPGA Design: Best Practices for Team-Based Design by Phil Simpson. Springer Publishing, 2010. About the Author Phil Simpson is Altera’s senior manager for software technical marketing, product planning, and EDA relationships. In this role, he is responsible for Altera’s Quartus II software and third-party EDA interfaces product planning and the creation of the Altera design flow software roadmap. Prior to joining Altera in 1997, Phil held several engineering roles at various EDA and semiconductor companies, including EDA Solutions, Data I/O, and Graseby Microsystems. He holds a B.S. (with honors) in Electrical & Electronic Engineering from City University, London and an M.S.C. (with distinction) in system design from the University of Central England, Birmingham, England. Phil is a published book author on team-based FPGA design. In addition he has written and had published numerous technical articles on topics related to his experience. ■

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6. The IP core has default parameter values. Parameters provide the simplest way to create reusable design blocks. IP features, ports and functionality can all be parameterized for maximum flexibility. The default values should be the most common usage model for the design block.


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EEWeb Pulse - Volume 13