Program Sessions: Thursday, May 28, 8:00 a.m. - 11:40 a.m. Session 13: 3D Integration, TSV, and Reliability
Session 14: Flip Chip: Bonding, ChipPackage Interaction, and Electromigration
Session 15: 3D Technology: Materials and Reliability
Committee: Advanced Packaging
Committee: Interconnections
Committee: Applied Reliability
Room: Harbor Island 1
Room: Harbor Island 2
Room: Harbor Island 3
Session Co-Chairs: Rozalia Beica - Yole Developpement John Knickerbocker - IBM Corporation
Session Co-Chairs: Bernd Ebersberger - Intel Mobile Communications Lou Nicholls - Amkor Technology, Inc.
Session Co-Chairs: Keith Newman – Hewlett-Packard Donna M. Noctor - Siemens Industry, Inc.
1. 8:00 a.m. - An Alternative Approach to Backside Via Reveal (BVR) for a Via-Middle Through-Silicon Via (TSV) Flow Jengyi Yu, Stefan Detterbeck, CheePing Lee, Prashant Meshram, Tom Mountsier, Lai Wei, Qing Xu, Sanjay Gopinath, Praveen Nalla, Matthew Thorum, and Joe Richardson – Lam Research Corporation
1. 8:00 a.m. - Development and Electrical Investigation of Novel Fine-Pitch Cu/Sn Pad Bumping Using Ultra-Thin Buffer Layer Technique in 3D Integration Yu-Sheng Hsieh, Yao-Jen Chang, and Kuan-Neng Chen – National Chiao Tung University
1. 8:00 a.m. - Size Effect on Ductile-toBrittle Transition in Cu-Solder-Cu MicroJoints Yaodong Wang, Igor M. De Rosa, and K. N. Tu – University of California, Los Angeles
2. 8:25 a.m. - Development of Chip-onWafer (CoW) Stacked Chip Packaging for High-End CIS Application T. Ni, L. Lien, N. Chen, K. Y. Huang, W. Chang, K. W. Chung, W. Huang, R. Wang, M. J. Chen, A. Liu, S. C. Hsu, J. Lin, C. C. Chang, and J. Tsai – Powertech Technology Inc.
2. 8:25 a.m. - Evaluation of Sn Based Microbumping Technology for Hybrid IR Detectors, 10µm Pitch to 5µm Pitch Philippe Soussan and Bivragh Majeed – IMEC; Pascal Le Boterf and Pierre Bouillon – Sofradir
2. 8:25 a.m. - High Strain Rate Properties of SAC305 Leadfree Solder at High Operating Temperature After Long-Term Storage Pradeep Lall, Di Zhang, and Jeff Suhling – Auburn University
3. 8:50 a.m. - Monolithic Integration of III-V HEMT and Si-CMOS Through TSV-less 3D Wafer Stacking K. H. Lee, D. Kohen, C. C. Huang, and K. E. K. Lee – Singapore-MIT Alliance for Res. & Tech.; S. Bao and C. S. Tan – Singapore-MIT Alliance for Res. & Tech.; Nanyang Technological University; E. Fitzgerald – Singapore-MIT Alliance for Res. & Tech.; Massachusetts Institute of Technology
3. 8:50 a.m. - A High Throughput and Reliable Thermal Compression Bonding Process for Advanced Interconnections Ming Li, DeWen Tian, YiuMing Cheung, Lei Yang, and John H. Lau – ASM Pacific Technology, Ltd.
3. 8:50 a.m. - Reduction of Thermal Expansion Coefficient of Electrodeposited Copper Kazuo Kondo, Shingo Mukahara, Taro Hayashi, and Masayuki Yokoi – Osaka Prefecture University; Jin Onuki – Ibaragi University
Refreshment Break: 9:15 a.m. - 10:00 a.m. Pavilion, in Exhibit Hall
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4. 10:00 a.m. - Physicochemical Effects of Seed Structure and Composition on Optimized TSV Fill Performance J. Chen, K. Fujita, D. Goodman, J. Chiu, and D. Papapanayiotou – TEL-NEXX Inc.
4. 10:00 a.m. - FC Cu Pillar Package Development for Broad Market Applications Robert Cheng, Mark Wang, Roger H. O. Kuo, Elson Chen, I. C. Chuang, Benjamin Pai, Jenny Chang, and Calvin Cheung – Advanced Semiconductor Engineering, Inc.
4. 10:00 a.m. - Reliability of Copper Wirebonds over Through-Silicon Vias for SiGe Power Amplifiers Jeff Gambino, Rich Graf, Bill Guthrie, Jim Salimeno, and Jerry Nuzback – IBM Corporation
5. 10:25 a.m. - A Comprehensive Reliability Study on a CoWoS 3D IC Package Ganesh Hariharan, Raghunandan Chaware, Inderjit Singh, Jeff Lin, Laurene Yip, Kenny Ng, and S. Y. Pai – Xilinx, Inc.
5. 10:25 a.m. - Quantifying Impact of Design Parameters on Ultra-Low K ILD Reliability in Fine Pitch Cu Bump Interconnect Structures Andy Bao, Tong Cui, Ahmer Syed, Lily Zhao, and Steve Bezuk – Qualcomm Technologies, Inc.
5. 10:25 a.m. - Effect of Cu Grain Boundary Sliding on TSV Extrusion Chenglin Wu, Tengfei Jiang, Jay Im, Rui Huang, and Paul Ho – University of Texas, Austin
6. 10:50 a.m. - TSV Residual Cu Step Height Analysis by White Light Interferometry for 3D Integration Daniel Smith, Yudesh Ramnath, Mohamed Rabie, Dingyou Zhang, and Luke England – GLOBALFOUNDRIES; Sanjeev Singh – Nanometrics, Inc.
6. 10:50 a.m. - Electromigration Immortality of Purely Intermetallic Micro-Bump for 3D Integration Hsiao-Yun Chen, C. H. Tung, Y. L. Hsiao, J. L. Wu, T.C. Yeh, Larry L. C. Lin, and Douglas C. H. Yu – Taiwan Semiconductor Manufacturing Company; Chih Chen – National Chiao Tung University
6. 10:50 a.m. - First Demonstration of Copper-Plated Through-Package-Via (TPV) Reliability in Ultra-Thin 3D Glass Interposers with Double-Side Component Assembly Kaya Demir, Saumya Gandhi, Raghu Pucha, Vanessa Smet, Venky Sundaram, P. Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Tomonori Ogawa – Asahi Glass Company
7. 11:15 a.m. - Fine Pitch 3D-TSV Based High Frequency Components for RF MEMS Applications Wolfgang Vitale, Montserrat Fernández-Bolaños, and Adrian Ionescu – École Polytechnique Fédérale de Lausanne; Reinhard Merkel, Josef Weber, and Peter Ramm – Fraunhofer EMFT; Amin Enayati, Ilja Ocket, and Walter De Raedt – IMEC
7. 11:15 a.m. - The Impact and Performance of Electromigration on Fine Pitch Cu Pillar with Different Bump Structure for Flip Chip Packaging Kuei Hsiao (Frank) Kuo, Cindy Mao, Katch Wang, Jason Lee, F. L. Chien, and Rick Lee – Siliconware Precision Industries Co., Ltd.
7. 11:15 a.m. - Through Glass Vias (TGV) and Aspects of Reliability Matthew Lueck and Alan Huffman – RTI International; Aric Shorey – Corning, Inc..