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ATMEL AVR MICROCONTROLLER PRIMER: PROGRAMMING AND INTERFACING
SPI Control Register - SPCR SPIE SPE DORD MSTR 7 SPI Status Register - SPSR SPIF
WCOL
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7
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CPOL CPHA
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SPR1
SPR0 0
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SPI2X 0
SPI Data Register - SPDR MSB
LSB
7
0
FIGURE 2.6: SPI registers.
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Data Order (DORD) allows the direction of shift from master to slave to be controlled. When the DORD bit is set to 1, the least significant bit (LSB) of the SPDR is transmitted first. When the DORD bit is set to 0, the Most Significant Bit (MSB) of the SPDR is transmitted first. The Master/Slave Select (MSTR) bit determines if the SPI system will serve as a master (logic 1) or slave (logic 0). The Clock Polarity (CPOL) bit allows determines the idle condition of the SCK pin. When CPOL is 1, SCK will idle logic high, whereas when CPOL is 0, SCK will idle logic 0. The Clock Phase (CPHA) determines if the data bit will be sampled on the leading (0) or trailing (1) edge of the SCK. The SPI SCK is derived from the microcontroller’s system clock source. The system clock is divided down to form the SPI SCK. The SPI Clock Rate Select (SPR[1:0]) bits and the Double SPI Speed (SPI2X) bit are used to set the division factor. The following divisions may be selected using SPI2X, SPR1, and SPR0: { 000: SCK = system clock/4 { 001: SCK = system clock/16 { 010: SCK = system clock/64 { 011: SCK = system clock/1284 { 100: SCK = system clock/2 { 101: SCK = system clock/8