Introduction Computer is basically an electronics device, though a bunch of devices are connected to it, which operate on other modes. The central processing unit within a computer is an IC chip. The primary memory components within the system are also integrated combination circuits. Besides, all such components are placed on a main circuit board, called motherboard, which integrates the functions of the resident components. In this module we will review the use and operations basic electronic components we have studied in our school days. We need to learn and review the behavioral aspects, rather than the circuit details.
Unit 1:PASSIVE AND ACTIVE COMPONENTS
The basic electronic components can be classified as passive components and active components. Active Components: Those devices or components which required external source to their operation is called Active Components. Examples of active components are Includes transistors (all types), integrated circuits (all types), TRIACs, SCRs, LEDs. A diode is an active component where, after connecting the diode to a power supply, the voltage across it needs to be at least 0.7V for the diode to start working. Passive Components: Those devices or components which do not required external source to their operation is called Passive Components. Typical passive components are resistors, capacitors, inductors and diodes. Passive Components do not require external source to their operation. Like a Diode, Resistor does not require 0.3 0r 0.7 V. I.e., when we connect a resistor to the supply voltage, it starts work automatically without using a specific voltage. In other words, those devices or components which produce energy in the form of Voltage or Current are called as Active Components. Those devices or components which store or maintain Energy in the form of Voltage or Current are known as Passive Components. Active Components are energy donor whereas passive components energy acceptors.
Resistors The first and most common electronic component is the resistor. There is virtually no working circuit that doesn't use them. There are three main parameters for resistors.
Resistance - the value of resistance, measured in Ohms. This is the primary parameter, and determines the current flow for any applied voltage. Power - The amount of power the resistor can handle safely. Large resistors generally have a higher power rating than small ones, and this is always specified by the manufacturer. Excess power will cause the resistor to overheat and fail, often in a spectacular manner. Voltage - Rarely specified, but this is the maximum voltage that may appear across a resistor. It has nothing to do with power rating, which may be exceeded at rated voltage. It is a measure of the maximum voltage that may appear across any value of resistance for this style without breakdown.
The resistance value is specified in ohms, the standard symbol is "R" or Ω. Resistor values are often stated as "k" (kilo, or times 1,000) or "M", (Meg, or times 1,000,000) for convenience. If resistor has a value of 2,200 Ohms, this may be shown as any of these - 2,200 Ohms/ 2,200 Ω/ 2,200R/ 2.2k/ 2.2k Ω/ 2k2. The schematic symbols for resistors are either of those shown below. I use the Euro version of the symbol exclusively.
Figure 1 - Resistor Symbols
The basic formula for resistance is Ohm's law, which states that... R = V / I Where V is voltage, I is current, and R is resistance The other formula you need with resistance is Power (P) P = V2 / R P = I2 * R Resistors have the same value for AC and DC - they are not frequency dependent within the normal audio range. Even at radio frequencies, they will tend to provide the same value, but at very high frequencies other effects become influential. Capacitors Capacitors are the second most common passive component, and there are few circuits that do not use at least one capacitor. A capacitor is essentially two conductive plates, separated by an insulator (the dielectric). To conserve space, the assembly is commonly rolled up, or consists of many small plates in parallel for each terminal, each separated from the other by a
thin plastic film. A capacitor also exists whenever there is more than zero components in a circuit - any two pieces of wire will have some degree of capacitance between them, as will tracks on a PCB, and adjacent components. Capacitance also exists in semiconductors (diodes, transistors), and is an inescapable part of electronics. There are two main symbols for capacitors, and one other that is common in the US, but rarely seen elsewhere. Caps (as they are commonly called) come in two primary versions - polarized and non-polarized. Polarized capacitors must have DC present at all times, of the correct polarity and exceeding any AC that may be present on the DC polarizing voltage. Reverse connection will result in the device failing, often in a spectacular fashion, and sometimes with the added excitement of flames, or high speed pieces of casing and electrolyte (an internal fluid in many polarized caps).
Figure 2 - Capacitor Symbols
Capacitors are rated in Farads, and the standard symbol is "C" or "F", depending upon the context. A Farad is so big that capacitors are most commonly rated in micro-Farads (ď F). Because of the nature of capacitors, they are also rated in very much smaller units than the micro-Farad. Inductors An inductor is most commonly a coil, but in reality, even a straight piece of wire has inductance. Winding it into a coil simply concentrates the magnetic field, and increases the inductance considerably for a given length of wire. Although there are some very common inductive components (such as transformers, which are a special case), they are not often used in audio. Small inductors are sometimes used in the output of power amplifiers to prevent instability with capacitive loads. An inductor, also called a coil or reactor, is a passive two-terminal electrical component which resists changes in electric current passing through it. When a current flows through it, energy is stored temporarily in a magnetic field in the coil. When the current flowing through an inductor changes, the time-varying magnetic field induces a voltage in the conductor, according to Faraday‘s law of electromagnetic induction, which opposes the change in current that created it. An inductor is characterized by its inductance, the ratio of the voltage to the rate of change of current, which has units of henries (H). Along with capacitors and resistors, inductors are one of the three passive linear circuit elements that make up electric circuits. Inductors are widely used in alternating current (AC) electronic equipment, particularly in radio equipment. They are used to
block the flow of AC current while allowing DC to pass; inductors designed for this purpose are called chokes.
Figure.3 Inductor Symbols
P N Junction Diodes P-N junction is a boundary or interface between two types of semiconductor material, P type and N type, inside a single crystal of semiconductor. It is created by doping P-N junctions are elementary building block of most semiconductor electronic devices such as diodes, transistors, solar cells, LEDs, and integrated circuits; For example, a common type of transistor, the bipolar junction transistor, consists of two p–n junctions in series, in the form n–p–n or p–n–p. Joining p-type and n-type semiconductors, electrons from the n region near the p–n junction tend to diffuse into the p region. As electrons diffuse, they leave positively charged immobile (fixed) ions in the n region. Likewise, holes from the p-type region near the p–n interface begin to diffuse into the n-type region, leaving fixed ions with negative charge. The regions nearby the p–n junction lose their neutrality and become charged, forming the space charge region or depletion layer The diode can be biased in two ways, forward bias and Reverse bias Forward bias In forward bias, the p-type is connected with the positive terminal and the n-type is connected with the negative terminal of the power supply A P-N junction connected in a Forward bias condition is shown in Fig.4.
Fig. 4. Forward biasing voltage
Fig. 5. Forward I-V characteristics of a P-N junction diode.
With a battery connected this way, the holes in the P-type region and the electrons in the N-type region are pushed toward the junction. This reduces the width of the depletion zone. The positive charge applied to the P-type material repels the holes, while the negative charge applied to the N-type material repels the electrons. As electrons and holes are pushed toward the junction, the distance between them decreases. This lowers the barrier in potential. With increasing forward-bias voltage, the depletion zone eventually becomes thin enough that the zone's electric field cannot oppose charge carrier motion across the p–n junction, as a consequence reducing electrical resistance. The electrons that cross the p–n junction into the P-type material (or holes that cross into the N-type material) will diffuse in the near-neutral region. The application of a forward biasing voltage on the junction diode results in the depletion layer becoming very thin and narrow which represents a low impedance path through the junction thereby allowing high currents to flow. The point at which this sudden increase in current takes place is represented on the static I-V characteristics curve above as the "knee" point. Reverse bias Connecting the P-type region to the negative terminal of the battery and the N-type region to the positive terminal corresponds to reverse bias. If a diode is reversebiased, the voltage at the cathode is higher than that at the anode. Therefore, no current will flow until the diode breaks down. Reverse-bias usually refers to how a diode is used in a circuit.
Fig. 6. Reverse biased P-N junction
Because the p-type material is now connected to the negative terminal of the power supply, the 'holes' in the P-type material are pulled away from the junction, causing the width of the depletion zone to increase. Likewise, because the N-type region is connected to the positive terminal, the electrons will also be pulled away from the junction. Therefore, the depletion region widens, and does so increasingly with increasing reverse-bias voltage. This increases the voltage barrier causing a high resistance to the flow of charge carriers, thus allowing minimal electric current to cross the p–n junction. The increase in resistance of the p–n junction results in the junction behaving as an insulator. The PN junction When the N and P-type semiconductor materials are first joined together a very large density gradient exists between both sides of the junction so some of the free electrons from the donor impurity atoms begin to migrate across this newly formed junction to fill up the holes in the P-type material producing negative ions.
Fig. 7. A P-N junction
However, because the electrons have moved across the junction from the Ntype silicon to the P-type silicon, they leave behind positively charged donor ions ( ND ) on the negative side and now the holes from the acceptor impurity migrate across the junction in the opposite direction into the region where there are large numbers of free electrons. As a result, the charge density of the P-type along the junction is filled with negatively charged acceptor ions ( NA ), and the charge density of the N-type along the junction becomes positive. This charge transfer of electrons and holes across the junction is known as diffusion. This process continues back and forth until the number of electrons which have crossed the junction have a large enough electrical charge to repel or prevent any more charge carriers from crossing over the junction. Eventually a state of equilibrium (electrically neutral situation) will occur producing a "potential barrier" zone around the area of the junction as the donor atoms repel the holes and the acceptor atoms repel the electrons. Since no free charge carriers can rest in a position where there is a potential barrier, the regions on either sides of the junction no become completely depleted of any more free carriers in comparison to the N and P type materials further away from the junction. This area around the junction is now called the Depletion Layer.
Light Emitting Diodes Light Emitting Diodes or LED´s, are among the most widely used of all the different types of semiconductor diodes available today. They are the most visible type of diode that emit a fairly narrow bandwidth of either visible light at different coloured wavelengths, invisible infra-red light for remote controls or laser type light when a forward current is passed through them. A "Light Emitting Diode" or LED as it is more commonly called, is basically just a specialized type of PN junction diode, made from a very thin layer of fairly heavily doped semiconductor material. When the diode is forward biased, electrons from the semiconductors conduction band recombine with holes from the valence band releasing sufficient energy to produce photons which emit a monochromatic (single colour) of light. Because of this thin layer a reasonable number of these photons can leave the junction and radiate away producing a coloured light output. Then we can say that when operated in a forward biased direction Light Emitting Diodes are semiconductor devices that convert electrical energy into light energy.
Fig 9. a Light Emitting Diode
LED Construction Surprisingly, an LED junction does not actually emit that much light so the epoxy resin body is constructed in such a way that the photons of light emitted by the junction are reflected away from the surrounding substrate base to which the diode is attached and are focused upwards through the domed top of the LED, which itself acts like a lens concentrating the amount of light. This is why the emitted light appears to be brightest at the top of the LED. All LEDs have their cathode, ( K ) terminal identified by either a notch or flat spot on the body, or by one of the leads being shorter than the other, ( the Anode, A ). The advantage of LEDs are they do not generate heat with the light, unlike normal ‗light bulbs‘. Because LEDs are solid-state devices, they can be extremely small and durable and provide much longer lamp life than normal light sources.
Light Emitting Diode Colours Light Emitting Diodes are made from exotic semiconductor compounds such as Gallium Arsenide (GaAs), Gallium Phosphide (GaP), Gallium Arsenide Phosphide (GaAsP), Silicon Carbide (SiC) or Gallium Indium Nitride (GaInN) all mixed together at different ratios to produce a distinct wavelength of colour. Different LED compounds emit light in specific regions of the visible light spectrum and therefore produce different intensity levels. By mixing together a variety of semiconductor, metal and gas compounds, different color LEDs can be produced. Some of them are: • Gallium Arsenide (GaAs) - infra-red • Aluminium Gallium Arsenide Phosphide (AlGaAsP) - high-brightness red, orange-red, orange, and yellow • Zinc Selenide (ZnSe) - blue The point where conduction begins and light is produced is about 1.2V for a standard red LED to about 3.6V for a blue LED. Transistors The transistor is the fundamental building block of modern electronic devices. A transistor is a semiconductor device used to amplify and switch electronic signals and electrical power. Transistor are of two types PNP and NPN, in PNP holes are majority carriers and in NPN electrons are the minority carriers. NPN transistors are faster than PNP because mobility of the electrons is faster than holes. It is composed of semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Today, some transistors are packaged individually, but many more are found embedded in integrated circuits. We all know that transistor works in three regions 1. Cut-Off Region: In the cut-off region transistor will be get off and in saturation region transistor will get on. This regions are mainly used in switching conditions. 2. Active Region: In the active region transistor will be on. The collector to emitter voltage (Vce) will be in between cut-off and saturation regions. Transistor can amplify the small changes in voltage at base which is given to the collector. Transistor requires only 0.7V to work completely in saturation mode.
3. Saturation Region: In the active region collector current (Ic) is proportional to the base current (Ib) by a constant multiplier called β if we denoted the above sentence in equation that will be Ic= βIb. By this we can easily use transistor as a linear amplifier in active region. The current flowing between emitter and collector of a transistor is much greater than that flowing between base and emitter. So a small base current is controlling the much larger emitter collector current. The ratio of the two currents, ICE / IBE is constant, provided that the collector emitter voltage VCE is constant. Therefore, if the base current rises, so does collector current. This ratio is the CURRENT GAIN of the transistor and is given the symbol hfe. A fairly low gain transistor might have a current gain of 20 to 50, while a high gain type may have a gain of 300 to 800 or more. The spread of values of hfe for any given transistor is quite large, even in transistors of the same type and batch.
Fig. 12. Output Characteristics of a typical transistor
Fig. 6.3 (right) shows the OUTPUT CHARACTERISTIC whose slope gives the value of output conductance (and by implication output resistance). The near horizontal parts of the graph lines show that a change in collector emitter voltage VCE has almost no effect on collector current in this region, just the effect to be expected if the transistor output had a large value resistor in series with it. Therefore the graph shows that the output resistance of the transistor is high. The above characteristic graphs show that, for a silicon transistor with an input applied between base and emitter, and output taken between collector and emitter (a method of connection called common emitter mode) one would expect;
Low input resistance (from the input characteristic). Fairly high gain (from the transfer characteristic). High output resistance (from the output characteristic).
Fig. 13. Mutual Characteristics of a transistor
The mutual characteristic shows a graph of Mutual Conductance IC/VBE and illustrates the change in collector current which takes place for a given change in base emitter voltage, (i.e. input signal voltage). This graph is for a typical silicon power transistor. Notice the large collector currents possible, and the nearly linear relationship between the input voltage and output current. The characteristics described on this page are those relating to a typical power transistor connected in the "common emitter" mode. Bipolar Junction Transistor (BJT) Bipolar transistors are named because they conduct by using both majority and minority carriers. The bipolar junction transistor, is a combination of two junction diodes, and is formed of either a thin layer of p-type semiconductor sandwiched between two n-type semiconductors (N-P-N transistor), or a thin layer of n-type semiconductor sandwiched between two p-type semiconductors (P-N-P transistor). This construction produces two p-n junctions: a base–emitter junction and a base– collector junction, separated by a thin region of semiconductor known as the base region The BJT has three terminals, an emitter, a base, and a collector. In an NPN transistor operating in the active region, the emitter-base junction is forward biased and electrons are injected into the base region. Because the base is narrow, most of these electrons will diffuse into the reverse-biased base-collector junction into the collector. By controlling the number of electrons that can leave the base, the number of electrons entering the collector can be controlled. Collector current is approximately β (common-emitter current gain) times the base current. It is typically greater than 100 for small-signal transistors. A BJT is represented by a numerical code which signifies whether it is an NPN or PNP transistor, current gain, its max to min voltage rating, current rating, temperature, frequency ,power etc .We can illustrate with an example a transistor
having numerical code BC107. By searching for this code in data manual or internet we will find its terminal details, that it is a silicon NPN transistor with current gain of 100-300, max collector current 100mA etc.Similarly the details of any transistor can be found from its code number. Transistor as a switch Transistors are commonly used as electronic switches, both for high-power applications such as switched-mode power supplies and for low-power applications such as logic gates. The switching action of a transistor can be demonstrated using the circuit shown in the figure1.2.85, an increase in the base voltage makes the emitter and collector currents to rise exponentially. This base voltage makes the transistor to turn on and bulb connected to the collector is turned ON. This state is called saturation .When in saturation condition the switch is said to be ON. Similarly when the base voltage is reduced (grounded) the transistor is turned OFF which will make the bulb to turn Off. This condition of transistor is called Cut-off, where, the switch is said to be in OFF condition. Applications The transistor acting as a switch is common in digital circuits where only "ON" and "OFF" values is considered. Moreover, a transistor can be used to increase the strength of weak signals. Various configurations of single transistor amplifier, such as, common emitter configuration, common base configuration and common collector configuration are used for providing current gain or voltage gain or both. From mobile phones to televisions, a vast numbers of products use amplifiers for sound reproduction, radio transmission, and signal processing. Field-effect transistor (FET) The field-effect transistor, is called a unipolar transistor, uses either electrons (in N-channel FET) or holes (in P-channel FET) for conduction. The four terminals of the FET are named source, gate, drain, and body (substrate). In most FETs, the body is connected to the source inside the package. In a FET, the drain-to-source current flows in a conducting channel that connects the source region to the drain region. The conductivity is varied by the electric field that is produced when a voltage is applied between the gate and source terminals; hence the current flowing between the drain and source is controlled by the voltage applied between the gate and source.
FETs are divided into two families: junction FET (JFET) and insulated gate FET (IGFET) or metal–oxide–semiconductor FET (MOSFET), reflecting its original construction from layers of metal (the gate), oxide (the insulation), and semiconductor. Unlike IGFETs, the JFET gate forms a P-N diode with the channel which lies between the source and drain. Also, both have a high input impedance, and both conduct current under the control of an input voltage. Application of Field Effect Transistors In integrated circuits, the MOSFETs are used for digital circuits. Discrete MOSFETs can be applied in transistor applications such as analog circuits, voltage regulators, amplifiers, power transmitters and motor drivers. Photo transistor A phototransistor is a device whose conduction depends on the intensity of light falling on the junction of the transistor. Thus the conductivity of the transistor is controlled by the light falling on it.
MOSFET(Metal Oxide Semiconductor Field Effect Transistor) MOSFET reflects its original construction from layers of metal (the gate), oxide (the insulation), and semiconductor. Here the gate is insulated by a shallow layer of insulator. MOSFET can operate in three different modes: Cutoff Mode, Triode Mode and Saturation Mode, Figure given below is a summary of the three Operation Modes of an n-Channel Enhancement Mode MOSFET. The MOSFET is very important in electronics. They are used especially as Amplifiers in analog circuit and Electronic Switches in digital circuit. Questions 1. Differenciate passive and active components with examples. 2. What you mean by depletion region in pn junction diode? 3. Explain forward and reverse bias operation of pn junction diode with neat diagrams. 4. Explain the working of transistor as a switch. 5. What are the differences between FET and BJT? 6. What is the significance of the regions of operation of a transistor? Explain. 7. Plot the characteristics of pn junction diode and transistor.
UNIT 2: ELECTRONIC CIRCUITS Rectifier A rectifier is a circuit which converts the Alternating Current (AC) input power into a Direct Current (DC) output power. The input power supply may be either a singlephase or a multi-phase supply with the simplest of all the rectifier circuits being that of the Half Wave Rectifier. The power diode in a half wave rectifier circuit passes just one half of each complete sine wave of the AC supply in order to convert it into a DC supply. Half Wave Rectifier Circuit
Fig 10. A half-wave rectifier; Input & Output waveforms
During each "positive" half cycle of the AC sine wave, the diode is forward biased as the anode is positive with respect to the cathode resulting in current flowing through the diode. Since the DC load is resistive (resistor, R), the current flowing in the load resistor is therefore proportional to the voltage (Ohm´s Law), and the voltage across the load resistor will therefore be the same as the supply voltage, Vs (minus Vf), that is the "DC" voltage across the load is sinusoidal for the first half cycle only so Vout = Vs. During each "negative" half cycle of the AC sinusoidal input waveform, the diode is reverse biased as the anode is negative with respect to the cathode. Therefore, NO current flows through the diode or circuit. Then in the negative half cycle of the supply, no current flows in the load resistor as no voltage appears across it so therefore, Vout = 0. Very often when rectifying an alternating voltage we wish to produce a "steady" and continuous DC voltage free from any voltage variations or ripple. One
way of doing this is to connect a large value capacitor across the output voltage terminals in parallel with the load resistor as shown below. This type of capacitor is known commonly as a "Reservoir" or Smoothing Capacitor. Half-wave Rectifier with Smoothing Capacitor When rectification is used to provide a direct voltage power supply from an alternating source, the amount of ripple can be further reduced by using larger value capacitors but there are limits both on cost and size. For a given capacitor value, a greater load current (smaller load resistor) will discharge the capacitor more quickly (RC Time Constant ) and so increases the ripple obtained. Then for single phase, halfwave rectifier circuits it is not very practical to try and reduce the ripple voltage by capacitor smoothing alone, it is more practical to use "Full-wave Rectification" instead. In practice, the half-wave rectifier is used most often in low-power applications because of their major disadvantages being. The output amplitude is less than the input amplitude, there is no output during the negative half cycle so half the power is wasted and the output is pulsed DC resulting in excessive ripple. To overcome these disadvantages a number of Power Diodes are connected together to produce a Full Wave Rectifier The Full Wave Rectifier A full wave rectifier uses both half-cycle of the input voltage instead of alternate half-cycle. Like the half wave circuit, a full wave rectifier circuit produces an output voltage or current which is purely DC or has some specified DC component. Full wave rectifiers have some fundamental advantages over their half wave rectifier counterparts. The average (DC) output voltage is higher than for half wave, the output of the full wave rectifier has much less ripple than that of the half wave rectifier producing a smoother output waveform. In a Full Wave Rectifier circuit two diodes are now used, one for each half of the cycle. A multiple winding transformer is used whose secondary winding is split equally into two halves with a common centre tapped connection, (C). This configuration results in each diode conducting in turn when its anode terminal is positive with respect to the transformer centre point C producing an output during both half-cycles, twice that for the half wave rectifier so it is 100% efficient as shown below. Full Wave Rectifier Circuit
Fig 11. Full wave rectifier and output waveform
The full wave rectifier circuit consists of two power diodes connected to a single load resistance (RL) with each diode taking it in turn to supply current to the load. When point A of the transformer is positive with respect to point C, diode D1 conducts in the forward direction as indicated by the arrows. When point B is positive (in the negative half of the cycle) with respect to point C, diode D2 conducts in the forward direction and the current flowing through resistor R is in the same direction for both half-cycles. As the output voltage across the resistor R is the phasor sum of the two waveforms combined, this type of full wave rectifier circuit is also known as a "bi-phase" circuit. As the spaces between each half-wave developed by each diode is now being filled in by the other diode the average DC output voltage across the load resistor is now double that of the single half-wave rectifier circuit and is about 0.637Vmax of the peak voltage, assuming no losses.
, where VMAX is the maximum peak AC voltage in one half of the secondary winding and one of the diodes, and VRMS is the corresponding rms value.
The Full Wave Bridge Rectifier This type of single phase rectifier uses four individual rectifying diodes connected in a closed loop "bridge" configuration to produce the desired output. The main advantage of this bridge circuit is that it does not require a special centre tapped transformer, thereby reducing its size and cost. The single secondary winding is connected to one side of the diode bridge network and the load to the other side as shown below.
Common Emitter RC Coupled Amplifier: Common emitter RC coupled amplifier is basic and simple amplifier. The circuit of RC coupled amplifier is shown below.
Fig. 14. A Common Emitter RC coupled amplifier
The capacitor C1 is a filter which is used to block the Dc voltage and allow only the variations in the voltage to the transistor. The Resistor R1, R2 is used as biasing network which will keep the transistor in active region. If we don‘t use the biasing the voltage from capacitor is directly given to the transistor. We all know that transistor will get on for 0.7v. Normally we will give more voltage to the transistor (> 0.7v), with this voltage transistor will easily go to the saturation mode and act as a closed loop circuit. Proper biasing network will keep the transistor in active region.
Resistors R3 and R4 is used to drop the voltage of Vcc. R3 is the collector resistor and R4 is the emitter resistor which is selected in such a way that both should drop the Vcc voltage by 50%. R3 should drop around 40% and remaining 10% is dropped by R4. The capacitor c2 and R4 will make negative feedback which makes the circuit stable. Oscillators An oscillator provides a source of repetitive A.C. signal across its output terminals without needing any input (except a D.C. supply). The signal generated by the oscillator is usually of constant amplitude. The wave shape and amplitude are determined by the design of the oscillator circuit and choice of component values. The frequency of the output wave may be fixed or variable, depending on the oscillator design. Types of Oscillator Oscillators may be classified by the type of signal they produce.
SINE WAVE OSCILLATORS produce a sine wave output. RELAXATION OSCILLATORS and ASTABLE MULTIVIBRATORS produce Square waves and rectangular pulses. SWEEP OSCILLATORS produce saw tooth waves.
Sine wave oscillators can also be classified by frequency, or the type of frequency control they use. RF (radio frequency) oscillators working at frequencies above about 30 to 50 Hz use LC (inductors and capacitors) or Crystals to control their frequency. These may also be classified as HF, VHF, and UHF oscillators, depending on their frequency. LF (low frequency) oscillators are generally used for generating frequencies below about 30 Hz and are usually RC oscillators, as they use resistors and capacitors to control their frequency. Square wave oscillators such as relaxation and astable oscillators may be used at any frequency from less than 1Hz up to several GHz and are very often implemented in integrated circuit form.
Sine Wave Oscillators
Fig. 15. Frequency Control Networks
These circuits ideally produce a pure sine wave output having a constant amplitude and stable frequency. The type of circuit used depends on a number of factors, including the frequency required. For this reason a combination of R and C is used to a control frequency. The circuit symbols used for these frequency control networks are shown in Fig. 10 LC oscillators Inductors and capacitors are combined in a resonating circuit that produces a very good shape of sine wave and has quite good frequency stability. That is, the frequency does not alter very much for changes in the D.C. supply voltage or in ambient temperature, but it is relatively simple, by using variable inductors or capacitors, to make a variable frequency (tuneable) oscillator. LC oscillators are extensively used in generating and receiving RF signals where a variable frequency is required. RC (or CR) oscillators At low frequencies such as audio the values of L and C needed to produce a resonating circuit would be too large and bulky to be practical. Therefore resistors and capacitors are used in RC filter type combinations to generate sine waves at these frequencies, however it is more difficult to produce a pure sine wave shape using R and C. These low frequency sine wave oscillators are used in many audio applications and different designs are used having either a fixed or variable frequency. Crystal oscillators At radio frequencies and higher, whenever a fixed frequency with very high degree of frequency stability is needed, the component that determines the frequency of oscillation is usually a quartz crystal, which when subjected to an alternating voltage, vibrates at a very precise frequency. The frequency depends on the physical dimensions of the crystal, therefore once the crystal has been manufactured to specific dimensions, the frequency of oscillation is extremely accurate. Crystal oscillator designs can produce either sine wave or square wave signals, and as well as being
used to generate very accurate frequency carrier waves in radio transmitters, they also form the basis of the very accurate timing elements in clocks, watches, and computer systems. Relaxation oscillators These oscillators work on a different principle to sine wave oscillators. They produce a square wave or pulsed output and generally use two amplifiers, and a frequency control network that simply produces a timing delay between two actions. The two amplifiers operate in switch mode, switching fully on or fully off alternately, and as the time, during which the transistors are actually switching, only lasts for a very small fraction of each cycle of the wave, the rest of the cycle they "relax" while the timing network produces the remainder of the wave. An alternative name for this type of oscillator is an "astable multivibrator", this name comes from the fact that they contain more than one oscillating element. Sweep oscillators A sweep waveform is another name for a saw-tooth wave. This has a linearly changing (e.g increasing) voltage for almost the whole of one cycle followed by a fast return to the wave‘s original value. Sweep oscillators often consist of a ramp generator that is basically a capacitor charged by a constant value of current. Keeping the charging current constant whilst the charging voltage increases, causes the capacitor to charge in a linear fashion rather than its normal exponential curve. At a given point the capacitor is rapidly discharged to return the signal voltage to its original value. These two sections of a saw-tooth wave cycle are called the sweep and the fly-back. Multivibrator A multivibrator is an electronic circuit used to implement a variety of simple twostate systems such as oscillators, timers and flip-flops. It is characterized by two amplifying devices (transistors, electron tubes or other devices) cross-coupled by resistors or capacitors. The name "multivibrator" was initially applied to the freerunning oscillator version of the circuit because its output waveform was rich in harmonics. There are three types of multivibrator circuits depending on the circuit operation:
Astable, in which the circuit is not stable in either state —it continually switches from one state to the other. It functions as a relaxation oscillator.
Monostable, in which one of the states is stable, but the other state is unstable (transient). A trigger pulse causes the circuit to enter the unstable state. After entering the unstable state, the circuit will return to the stable state after a set time. Such a circuit is useful for creating a timing period of fixed duration in response to some external event. This circuit is also known as a one shot.
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Bistable, in which the circuit is stable in either state. It can be flipped from one state to the other by an external trigger pulse. This circuit is also known as a flip flop. It can be used to store one bit of information.
Multivibrators find applications in a variety of systems where square waves or timed intervals are required.
Astable multivibrator An astable multivibrator is a regenerative circuit consisting of two amplifying stages connected in a positive feedback loop by two capacitive-resistive coupling networks. The amplifying elements may be junction or field-effect transistors, vacuum tubes, operational amplifiers, or other types of amplifier. The example diagram shows bipolar junction transistors.
Fig. 16. An Astable multivibrator circuit
The circuit is usually drawn in a symmetric form as a cross-coupled pair. Two output terminals can be defined at the active devices, which will have complementary states; one will have high voltage while the other has low voltage, (except during the brief transitions from one state to the other). Monostable multivibrator circuit In the monostable multivibrator, the one resistive-capacitive network (C2-R3 in figure 1) is replaced by a resistive network (just a resistor). The circuit can be thought as a 1/2 astable multivibrator. Q2 collector voltage is the output of the circuit (in contrast to the astable circuit, it has a perfect square waveform since the output is not loaded by the capacitor). When triggered by an input pulse, a monostable multivibrator will switch to its unstable position for a period of time, and then return to its stable state. The time period monostable multivibrator remains in unstable state is given by t = ln(2)R2C1. If repeated application of the input pulse maintains the circuit in the unstable state, it is called a retriggerable monostable. If further trigger pulses do not affect the period, the circuit is a non-retriggerable multivibrator. Bistable multivibrator circuit
In the bistable multivibrator, both the resistive-capacitive network are replaced by resistive networks (just resistors or direct coupling). This latch circuit is similar to an astable multivibrator, except that there is no charge or discharge time, due to the absence of capacitors. Hence, when the circuit is switched on, if Q1 is on, its collector is at 0 V. As a result, Q2 gets switched off. This results in more than half +V volts being applied to R4 causing current into the base of Q1, thus keeping it on. Thus, the circuit remains stable in a single state continuously. Similarly, Q2 remains on continuously, if it happens to get switched on first.
Fig. 17. A Monostable multivibrator circuit
Switching of state can be done via Set and Reset terminals connected to the bases. For example, if Q2 is on and Set is grounded momentarily, this switches Q2 off, and makes Q1 on. Thus, Set is used to "set" Q1 on, and Reset is used to "reset" it to off state. 555 timer IC
Fig.18.1. NE555 from Signetics in dual-in-line package
Fig. 18.2. Internal block diagram
The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse generation, and oscillator applications. The 555 can be used to provide time delays, as an oscillator, and as a flip-flop element. Introduced in 1971 by Signetics, the 555 is still in widespread use due to its ease of use, low price, and stability. It is now made by many companies in the original bipolar and also in low-power CMOS types. Depending on the manufacturer, the standard 555 package includes 25 transistors, 2 diodes and 15 resistors on a silicon chip installed in an 8-pin mini dual-in-line package (DIP-8). It has been hypothesized that the 555 got its name from the three 5 k立 resistors used within Low-power versions of the 555 are also available, such as the 7555 and CMOS TLC555. The 7555 is designed to cause less supply noise than the classic 555 and the manufacturer claims that it usually does not require a "control" capacitor and in many cases does not require a decoupling capacitor on the power supply. Pins
Fig. 19. Pinout diagram
The connection of the pins for a DIP package is as follows: Pin Name Purpose 1
GND
Ground reference voltage, low level (0 V)
2
TRIG
The OUT pin goes high and a timing interval starts when this input falls below 1/2 of CTRL voltage (which is typically 1/3 of VCC, when CTRL is
open). This output is driven to approximately 1.7 V below +VCC or GND.
3
OUT
4
A timing interval may be reset by driving this input to GND, but the RESET timing does not begin again until RESET rises above approximately 0.7 volts. Overrides TRIG which overrides THR.
5
CTRL
Provides "control" access to the internal voltage divider (by default, 2/3 VCC).
6
THR
The timing (OUT high) interval ends when the voltage at THR is greater than that at CTRL (2/3 VCC if CTRL is open).
7
DIS
Open collector output which may discharge a capacitor between intervals. In phase with output.
8
VCC
Positive supply voltage, which is usually between 3 and 15 V depending on the variation.
Pin 5 is also sometimes called the CONTROL VOLTAGE pin. By applying a voltage to the CONTROL VOLTAGE input one can alter the timing characteristics of the device. In most applications, the CONTROL VOLTAGE input is not used. It is usual to connect a 10 nF capacitor between pin 5 and 0 V to prevent interference. The CONTROL VOLTAGE input can be used to build an astable with a frequency modulated output.
Modes The 555 has three operating modes:
Monostable mode: In this mode, the 555 functions as a "one-shot" pulse generator. Applications include timers, missing pulse detection, bounce free switches, touch switches, frequency divider, capacitance measurement, pulsewidth modulation (PWM) and so on.
Astable (free-running) mode: The 555 can operate as an oscillator. Uses include LED and lamp flashers, pulse generation, logic clocks, tone generation, security alarms, pulse position modulation and so on. The 555 can be used as a simple ADC, converting an analog value to a pulse length. E.g. selecting a thermistor as timing resistor allows the use of the 555 in a temperature sensor: the period of the output pulse is determined by the temperature. The use of a microprocessor based circuit can then convert the pulse period to temperature, linearize it and even provide calibration means. Bistable mode or Schmitt trigger: The 555 can operate as a flip-flop, if the DIS pin is not connected and no capacitor is used. Uses include bounce-free latched switches.
Questions 
List different types of rectifiers.  Explain the working of half wave and full wave rectifier with neat diagrams. 3. With neat circuit diagram, explain the working of RC coupled amplifier? 4. What are the types of oscillators? Explain the functions of each. 5. Explain working of monostable multivibrator with circuit diagram. 6. Explain working of astable multivibrator with circuit diagram. 7. Identify various applications where each circuit can be used.
Module II
Number Systems
Unit III Number systems
Introduction Computers are basically devices which operate on data represented as numbers. But the numbers shall use only two digits 0 and 1. All information input to a computer- let it be numbers, text, picture, sound or video- will be converted to codes in binary form before storing and processing. The processor and memory can deal with binary numbers only. Actually all information are stored as combinations of two voltage levels. 0 and 1 were the symbols used to model the voltages within the memory and processor. Now data in all forms of storage devices use the same notations. The number system with base 2 which uses only two digits is called binary number system. We are all familiar with decimal number system, using ten different symbols, called digits, to represent the values. Hence we have to learn how to use binary number system. In this module we will familiarize binary number system and learn how to convert decimal numbers to binary and vice versa. You will be able to do basic arithmetic with binary numbers after learning this module. We will also familiarize some other number systems like octal and hexadecimal. Number System Bases We are well familiar with the decimal number system. As we know the number system uses 10 digits to represent values, and we say the base of the system is 10. The digits in each position of a decimal number possess a position value in powers of 10, increasing from right to left. Hence the number 563 can be evaluated as 3 x 1 + 6 x 10 + 5 x 102. Now think of a number system with a different base, say 5. Then probably you will be using the digits 0,1,2,3,4 to represent the values. Then the number 432 in your number system can be evaluated as 2 x 1 + 3 x 5 + 4 x 52 ( = 117 in decimal!).
Like this we can form number systems with any base. Computers use binary number system, a number system with base 2, to represent data within. In computer programming, some representations use another number system called hexadecimal, which is base -16. In the following sections we will learn how to represent and use numbers these forms. Binary number system AS we have already seen, binary number system is a base-2 number system. It uses only two digits 0 and 1. A binary digit is usually called a bit. A series of 4 bits is called a nibble. When there are 8-bits in a number it is called a byte. The number 1011 is an example of nibble and 11001001 form a byte.
Binary numbers will be having position values in the powers of 2. See figure 2.1 showing the numbers written in binary. Binary
Decimal
0
0
1
1
10
2
11
3
100
4
101
5
110
6
111
7
1000
8
1001
9
1010
10
1011
11
1100
12
1101
13
1110
14
Figure 1. Numbers in binary and decimal
Converting between decimal and binary How can we convert a decimal number to a binary number? How can we find the decimal equivalent when we get a binary number? Let us see. First let us see how to generate a binary equivalent of a decimal number. The process is very simple. Continuously divide the number by 2, until we get a 1 at last. But, don‘t leave the remainders in between, because they form our answer! e.g. consider the number 25. First let us divide the number by 2. 2
25
1
2
12
0
2
6
0
2
3
1
1 Now, stack the reminders from bottom up. We get 11001. This is our answer. i.e., 11001 is the binary equivalent of 25. We write 2510 = 110012 See more examples. 47610 = 1110111002
255 = 111111112
2
476 0
2
255 1
2
238 0
2
127 1
2
119 1
2
63
1
2
59
1
2
31
1
2
29
1
2
15
1
2
14
0
2
7
1
2
7
1
2
3
1
2
3
1
1
1
Now, it is more easy to convert a binary number to decimal, just multiply each digit with its position value, in powers of 2. The digit at rightmost position have a position value of 1 (20). e.g. 110012 = 1 x 1 + 0 x 21 + 0 x 22 + 1 x 23 + 1 x 24 = 1+8+16 = 2510
Let us summarize what we learned in a different way. Look at the table below. (LSB means Least significant bit-the right most bit, and, MSB means the most significant bit- the left most bit in a number.
8 individual bits in a set forms us a byte. Obviously, binary numbers can be larger than a simple byte. However, the byte is the most basic representation of data. The 'Bit Set' row is for our binary digits, either 0 or 1. Here they are all 1. The 'Exponent Value' row is how we arrive mathematically at the 'Decimal Value' row. An exponential value such as 23 means 2 x 2 x 2 = 8. By the way, any number with an exponent of 0 ALWAYS equates to 1 (20 = 1 and 4000 also = 1). The 'Decimal Value' row represents positionally the decimal value of the binary digit in question. 128
64
32
16
8
4
2
1
See more examples. 110010012
= 1 x 1 + 0 x 2 1 + 0 x 2 2 + 1 x 23 + 0 x 24 + 0 x 2 5 + 1 x 26 + 1 x
27 = 20110 If you closely observe the results, you can see that odd numbers always ends with a 1 and even numbers ends with a 0 in binary. In general, to convert a number from a given base into base 10, all we need to do is treat each place as a power of the given base times the value of the digit in that place. Note that customarily for a given base, only digits from 0 to the base minus one are used. For instance, in decimal, we only use the digits 0 through 9. That's because we don't need any more digits to express every possible number. Hexadecimal number system At some levels, computer scientists represent data in base -16 format using 16 different symbols (digits). This number system is called hexadecimal number system. Numbers with bases greater than 10 will require more than 10 possible digits. For instance, the number 11 in base ten can be expressed in base 16 with only a single digit because the ones place in base 16 can range from 0 to 15. Since we only
have 10 digits, the letters A through F are used to stand for the "digits" 10 through 15. So, the digits in hexadecimal numbers are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E and F. For instance, the hexadecimal number B stands for the decimal number 11. Figure 2 shows a set of numbers in hexadecimal with their equivalents in decimal. Hexadecimal Decimal 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A 10 B 11 C 12 D 13 E 14 F 15 10 16 11 17 12 18 13 19 14 20 15 21 16 22 17 23 18 24 19 25 1A 26 1B 27 1C 28 1D 29 1E 30 1F 31 90 144 AE 174 FF 255 100 256 10F 271 A0F 2571
Conversion between hexadecimal and other systems We have seen how to covert a binary number to decimal and vice versa. The procedure for conversion between hexadecimal and decimal is the same. First let us try some examples on decimal numbers to convert to hexadecimal. e.g. Let us convert 10A16 to decimal. 10A
= A x 1 + 0 x 16 + 1 x 162 = 10 x 1 + 0 + 256
//the digit ‗A‘ is replaced with its decimal value
10. = 26610 Now, 2C3D = D x 1 + 3 x 16 + C x 162 + 2 x 163 = 13 x 1 + 3 x 16 + 12 x 256 + 2 x 4096 = 7229 Coversion from decimal to hexadecimal Here also we use the same procedure for decimal to binary, but the division shall be by 16. Let us find the hexadecimal for 1020 16 1020 12 C
So, 1020 = 3CF16
16
63 15 F 3
See more examples.
16 7223 7 16 16
451 3 28 12 C 1
7223 = 1C3716
Conversion from hexadecimal to binary Replace each hex digit by the 4 equivalent bits. (use the table above) for example, A3C516 = 1010 0011 1100 01012 102A16 = 0001 0000 0010 10102 Now, we can learn an alternate method for converting from hexadecimal to decimal which will help us to reduce the heavy multiplications by powers of 16. Step 1: convert the hexadecimal to binary. Step 2 : Convert from binary to decimal. Conversion from Binary to Hexadecimal Starting from the right-most bit (least-significant bit), replace each group of 4 bits by the equivalent hex digit (pad the left-most bits with zero if necessary), for examples,
10010010102 = 0010 0100 10102 = 24A16 100010110010112 = 0010 0010 1100 10112 = 22CB16
Now, we can find a second method for converting from decimal to hexadecimal. Step 1: Convert from decimal to binary. Step 2: Replace each 4-bit combination with its equivalent hexadecimal digit. e.g.
300
= 1001011002 = 1 0010 11002 = 1 2 C16
See, here the rightmost 4-bit group 1100 turns to C (12) , next 4-bit 0010 turns to 2, and finally there is only one bit , 1. It is important to note that hexadecimal number provides a compact form or shorthand for representing binary bits.
Questions 1. Can you define a new number system with base 3? 2. Convert the following numbers to binary: i. 255 (ii) 63 (iii) 511 What is common to all? Can you explain why? 3. Convert the following binary numbers to decimal: i. 11011101 (ii) 10000000110 4. On seeing a binary number, how can we identify whether it is odd or even? 5. What will be the decimal value of the highest binary number with, say, n digits? [The highest decimal number with n digits is 10n -1] 6. Convert the following hexadecimal numbers to binary and decimal. i. 10A0 ii. 356 iii. 1101
Unit IV Binary Arithmetic In this section we will learn how to do arithmetic operations on binary numbers. Addition First let us see how to add two binary numbers. Its just like what we do with decimal numbers. Add the digits in same positions, if there is a carry, add it to the next position. Note: 1 + 0 = 0 + 1 = 0;
1 + 1 = 10. Here the 1 turns to be carry bit.
0+0 = 0, 1+0 = 1, 0+1 = 1, 1+1 = 0, and you carry a 1.
with with with
no no no
carry, carry, carry,
Also, 1 + 1 + 1 = 11(equal to 3 in decimal).
e.g.
1100110 + 10010 =
1 1101010 + 0010010 1111100
Let us see more examples. 111 111101 + 100100 1100001
111 1111 + 10010 100001
Experiment more with your own examples. Subtraction Subtraction too is similar to what we do in decimal, but be a bit more careful.
0 - 0 = 0 0 - 1 = 1,
and borrow 1 from the next more significant bit
1 - 0 = 1 1 - 1 = 0
For example, 00100101 - 00010001 = 00010100 0 - 0
0 0
0 1 10 0 1
0 0
1 0
0 0
1 1
borrows = 37(base 10) = 17(base 10)
0
0
0 1
0
1
0
0
= 20(base 10)
0 - 0
0 0
0 10 1 1 0 1
1 0 10 0 1
1 1
1 0
borrows = 51(base 10) = 22(base 10)
0
0
0 1
1 1
0
1
= 29(base 10)
00110011 - 00010110 = 00011101
But this is our way of doing subtraction. Computers use a different method! Let us see. Complements Complement of a binary digit is the other one. i.e, complement of 1 is 0 and that of 0 is 1. Now let us see how to get the complement of a number. There are two ways for getting it – 1s complement and 2‘s complement. 1’s complement To get the 1s complement of a number, just negate each of its bits. E.g. , 1s complement of 10 is 01. See more examples. 10011110 01100001 1111110 0000001 = 1 2’s complement To calculate the 2's complement of an integer, invert the binary equivalent of the number by changing all of the ones to zeroes and all of the zeroes to ones (simply taking the 1‘s complement), and then add one.
For example, 0001 0001(binary 17)
1110 1111(two's complement -17)
NOT(0001 0001) = 1110 1110 1110 1110 + 0000 0001 = 1110 1111
(Invert bits) (Add 1)
2's Complement Addition Two's complement addition follows the same rules as binary addition. For example, 0000 0101 = +5
5 + (-3) = 2
+ 1111 1101 = -3 0000 0010 = +2
2's Complement Subtraction Two's complement subtraction is the binary addition of the minuend to the 2's complement of the subtrahend (adding a negative number is the same as subtracting a positive one).
For example, 0000 0111 = +7
7 - 12 = (-5)
+ 1111 0100 = -12 1111 1011 = -5
Multiplication Multiplying unsigned numbers in binary is quite easy. Multiplication can be performed done exactly as with decimal numbers, except that you have only two digits (0 and 1). The only number facts to remember are that 0*1=0, and 1*1=1 (this is the same as a logical "and").
0 x 0 = 0 0 x 1 = 0 1 x 0 = 0
1 x 1 = 1,
and no carry or borrow bits
For example, 00101001 × 00000110 = 11110110
0 × 0
0 0
1 0
0 0
1 0
0 1
0 1
1 0
= =
41(base 10) 6(base 10)
0
0 0
0 0 1
0
0
1
0 1 0
0 0 1
0 1 0
0 0 0
0 0 1
0 1
0
1
1
1
0
1
1
0
=
246(base 10)
00010111 Ă— 00000011 = 01000101
0 Ă— 0
0 0
0 0
1 0
0 0
1 0
1 1
1 1
1 0 0
1 0 1
1 1 0
1 0 1
1 1 1
1 1
1
0
0 0
0
0
1
0
0
0
1
0
1
= =
23(base 10) 3(base 10) carries
=
69(base 10)
Multiplication is different than addition in that multiplication of an n bit number by an m bit number results in an n+m bit number. Let's take a look at an example where n=m=4 and the result is 8 bits Decimal
10 x6 60
Binary 1010 x0110 0000 1010 1010 +0000 0111100
In this case the result was 7 bit, which can be extended to 8 bits by adding a 0 at the left. When multiplying larger numbers, the result will be 8 bits, with the leftmost set to 1, as shown. Decimal
13 x14 182
Binary 1101 x1110 0000 1101 1101 +1101 10110110
Questions 1. What is the importance of finding complements? 2. Can you explain a way to find complements of decimal numbers? 3. Do the following operations: (i)
110110 + 1000111
(ii) 11011 – 101110
(iii) 1111 x 10001
4. Subtract the following number using 1s complement form and then 2s complements. (i)
11011 – 101110
(ii) 1001111 - 110011
5. Multiplication can be done as a series of addition. Illustrate with two binary numbers.
Unit V Coding schemes Computers use different forms of binary codes to represent information at different context. In this section we will look into the popular coding schemes like BCD. Binary-coded decimal (BCD) is a way of encodings decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Special bit patterns are sometimes used for a sign or for other indications. In BCD each decimal digit is replaced using a 4-bit binary number. BCD's main advantage is the ease of conversion into human-readable representations, in comparison to binary positional systems. BCD's principal drawbacks are a small increase in the complexity of the circuits needed to implement basic arithmetics and a slightly less dense storage. BCD was used in many early decimal computers. Although BCD is not as widely used as in the past, decimal fixed-point and floating-point formats are still important. Coding in BCD is vey simple. The decimal digits are replaced by its corresponding binary value, but as a four bit pattern. This is also called "8421" encoding. Decimal Digit
BCD 8421
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
As most computers deal with data in 8-bit bytes, it is possible to use one of the following methods to encode a BCD number:  Uncompressed: each numeral is encoded into one byte, with four bits representing the numeral and the remaining bits having no significance.  Packed: two numerals are encoded into a single byte, with one numeral in the least significant nibble (bits 0 through 3) and the other numeral in the most significant nibble (bits 4 through 7). As an example, encoding the decimal number 91 using uncompressed BCD results in the following binary pattern of two bytes:
Decimal:
9
1
Binary : 0000 1001 0000 0001
In packed BCD, the same number would fit into a single byte:
Decimal:
9
1
Binary : 1001 0001
Hence the numerical range for one uncompressed BCD byte is zero through nine inclusive, whereas the range for one packed BCD is zero through ninety-nine inclusive. To represent numbers larger than the range of a single byte any number of contiguous bytes may be used. For example, to represent the decimal number 12345 in packed BCD, using big-endian format, a program would encode as follows:
Decimal:
1
2
3
4
5
Binary : 0000 0001 0010 0011 0100 0101
Note that the most significant nibble of the most significant byte is zero, implying that the number is in actuality 012345. Also note how packed BCD is more efficient in storage usage as compared to uncompressed BCD; encoding the same number in uncompressed format would consume 100 percent more storage.
ASCII We have seen that computers can receive only binary codes. The American Standard Code for Information Interchange (ASCII) is a character-encoding scheme originally based on the English alphabet that encodes 128 specified characters - the numbers 0-9, the letters a-z and A-Z, some basic punctuation symbols, some control codes that originated with Teletype machines, and a blank space - into the 7-bit binary integers. ASCII codes represent text in computers, communications equipment, and other devices that use text. Most modern character-encoding schemes are based on ASCII, though they support many additional characters. ASCII developed from telegraphic codes. ASCII includes definitions for 128 characters: 33 are non-printing control characters (many now obsolete) that affect how text and space are processed and 95 printable characters, including the space. In short, whatever key we type on the keyboard a binary code will be transmitted to the computer. ASCII is the most widely accepted and used coding sheet for such conversion.
Floating point representation We have seen that characters are represented using ASCII codes and integers can be represented using binary converted numbers. But in case of floating point numbers, we need a different form of representing data, since a point floats in between the digits. It is infeasible to store the point within the number in binary form. Now let us remember the normalized number representation scheme studies in our schools. The number 406. 07 can be written as 4.0607 x 102 Similarly,
0.003205 35000
ďƒ 3.205 x 10-3 ďƒ 3.5 x 104
Here every number is expressed in mantissa-exponent form. In the above cases the mantissa and exponent parts are, 4.0607 and 2 3.205 and -3 3.5 and 4. So if we know the values 40607 and 2 we can reconstruct the number 406.07. We have converted the floating point to fixed point, placed after the first non-zero digit in the number. Hence we need not store the point!
This method is used for storing floating numbers in binary form. See examples in the following table. Number 11001.00011 0.0001001 1100.0
Mantissa 1100100011 1001 11000
Exponent 100 (4) -100 (-4) 11 (3)
There are two standard representations from IEEE (Institute of Electrical and Electronic Engineers) for representing floating point numbers, namely, Singleprecision format and double-precision format. Single-precision format Single precision format uses 4 bytes for data storage. The single precision format has 23 bits for significant, 8 bits for exponent and 1 bit for sign. For example, the rational number 9÷2 can be converted to single precision float format as following, 9(10) ÷ 2(10) = 4.5(10) = 100.1(2) The result said to be normalized, if it is represented with leading 1 bit, i.e. 1.001(2) x 22. (Similarly when the number 0.000000001101(2) x 23 is normalized, it appears as 1.101(2) x 2-6). Omitting this implied 1 on left extreme gives us the mantissa of float number. The implied most significant bit can be used to represent even more accurate significant (23 + 1 = 24 bits) bits. The floating point numbers are to be represented in normalized form. In other words, the above result can be written as 1.001(2) x 22 which yields the integer components as s = 0, b = 2, significand (m) = 1.001, mantissa = 001 and e = 2. The corresponding single precision floating number can be represented in binary as shown below,
Where the exponent field is supposed to be 2, yet encoded as 129 (127+2) called biased exponent. The exponent field is in plain binary format which also represents negative exponents with an encoding (like sign magnitude, 1‘s compliment, 2‘s complement, etc.). The biased exponent is used for representation of negative exponents. The biased exponent has advantages over other negative representations in performing bitwise comparing of two floating point numbers for equality.
A bias of (2n-1 – 1), where n is the number of bits used in exponent, is added to the exponent (e) to get biased exponent (E). So, the biased exponent (E) of single precision number can be obtained as E = e + 127 The range of exponent in single precision format is -126 to +127. Other values are used for special symbols. Double Precision Format: The double precision format uses 8-bytes, with 52 bits for significant (1 represents implied bit), 10 bits for exponent and 1 bit for sign. All other definitions are same for double precision format, except for the size of various components. Format Signbit Exponent Mantissa Single precision 1 8 23+1 Double precision 1
11
52+1
Precision: The smallest change that can be represented in floating point representation is called as precision. The fractional part of a single precision normalized number has exactly 23 bits of resolution, (24 bits with the implied bit). This corresponds to log(10) (223) = 6.924 = 7 (the characteristic of logarithm) decimal digits of accuracy. Similarly, in case of double precision numbers the precision is log(10) (252) = 15.654 = 16 decimal digits. Questions 1. 2. 3. 4.
Compare the use and scope of ASCII, BCD and base-2 representations of data. Can you justify the reason for ASCII codes being 8-bit? What are the standard schemes for representing floating point numbers? Why do we need to convert floating-point numbers to normalized exponent form before storing in memory? 5. Write a detailed note on various coding schemes used in computers.
Module III
Boolean Algebra
Unit VI Basic Functions The English mathematician George Boole (1815-1864) codified several rules of relationship between mathematical quantities limited to one of two possible values: true or false, 1 or 0. His mathematical system became known as Boolean algebra 1. Basic functions A logic gate is a basic building block of a digital circuit. The logic gates generally have two inputs but it can be more than two inputs. The input can be one of the two binary values ‗0‘ or ‗1‘. These binary values are also represented by the terms, ‗low‘ or ‗false‘ for ‗0‘ and ‗high‘ or ‗true‘ for ‗1‘. In most digital circuits, these low and high states are represented by a voltage difference, like, 0V for ‗low‘ state and +5 V for ‗high‘ state. There are seven different logic gates: OR, AND, NOT, NOR, NAND, XOR and XNOR, which will be discussed in the following sections. 1.1 AND, OR and NOT operators We use the symbol ‗.‘ or ‗*‘ for the AND and ‗+‘ for the OR connectives which we call Boolean operators. The NOT operator, which is unary, is denoted with a post fix prime, eg A‘ means NOT A. AND operator: The AND has two inputs A and B and gives an output of ‗1‘ only when both inputs are ‗1‘. In the other three cases, the output is 0‘. The truth table and symbol for AND gate is given below:
OR operator: The OR gate receives two inputs A and B. The output of the OR gate is 1, when either of the input value is ‗1‘. When both inputs have value of ‗0‘, the output is ‗0‘. The truth table and symbol for an OR gate is given below:
NOT operator: NOT operator is a unary operator which has only one input. If the input is ‗0‘, the output is ‗1‘ and if the input is ‗1‘, the output is ‗0‘. The truth table and symbol for NOT gate is given below:
Any Boolean Operation is carried out by their order of precedence. The following tables gives the precedence of operation for the above three operators Boolean Operator
Precedence
NOT
HIGHEST
AND
MIDDLE
OR
LOWEST
Combinational Logic &Laws of Boolean algebra A Combination Logic is used in a Combinational circuit which is defined as a digital circuit whose output depends on different combinations of the binary input values. The Combinational Logic circuits operate on the following Laws of Boolean algebra: Annulment Law - A term AND´ed with a "0" equals 0. A term OR´ed with a "1" equals 1. a) A . 0 = 0,
A variable AND'ed with 0 is always equal to 0.
b) A + 1 = 1,
A variable OR'ed with 1 is always equal to 1.
Identity Law - A term OR´ed with a "0" or AND´ed with a "1" will always equal that term. a) A + 0 = A, A variable OR'ed with 0 is always equal to the variable. b) A . 1 = A,
A variable AND'ed with 1 is always equal to the variable.
Idempotent Law - An input AND´ed with itself or OR´ed with itself is equal to that input. a) A + A = A,
A variable OR'ed with itself is always equal to the variable.
b) A . A = A,
A variable AND'ed with itself is always equal to the variable.
Complement Law - A term AND´ed with its complement equals "0" and a term OR´ed with its complement equals "1". a) A . A‘ = 0,
A variable AND'ed with its complement is always equal to 0.
b) A + A‘ = 1,
A variable OR'ed with its complement is always equal to 1.
Commutative Law - The order of application of two separate terms is not important. a) A . B = B . A,
The order in which two variables are AND'ed makes no
difference. b) A + B = B + A,
The order in which two variables are OR'ed makes no
difference. Double Negation Law - A term that is inverted twice is equal to the original term. (A‘)‘= A,
A double complement of a variable is always equal to the
variable. de Morgan´s Theorem - There are two "de Morgan´s" rules or theorems, 1. Two separate terms NOR´ed together is the same as the two terms inverted (Complement) and AND´ed for example, (A+B)‘ = A‘. B‘. 2. (Two separate terms NAND´ed together is the same as the two terms inverted (Complement) and OR´ed for example,( A.B)‘ = A‘ +B‘. Other algebraic laws not detailed above include: Distributive Law - This law permits the multiplying or factoring out of an expression.
(a) A (B+C) =AB+AC (b) A + (B C) = (A + B) (A + C) Absorptive Law - This law enables a reduction in a complicated expression to a simpler one by absorbing like terms. Associative Law - This law allows the removal of brackets from an expression and regrouping of the variables. (a) (A+B)+C=A+(B+C) (b) (A B) C = A (B C)
2.1 Venn Diagrams Venn diagram is a graphical representation of different Boolean functions/operations. The theorems, properties and logical expressions can be verified through Venn diagrams. The universe is represented by a square. Any set in this space is denoted by a square or circle or ellipse. In the following cases, the sets or the inputs are represented by a circle. As the Boolean expression can have only two different outputs which are ‗0‘ and ‗1‘, the Venn diagrams consists of a circle or any other shape which is shaded or not shaded. A shaded area represents the value of ‗1‘ and a non-shaded area represents a value of ‗0‘. Venn diagram for OR operator The OR representation of Venn diagram is as follows. A OR B means, either A OR B is included. Every area which is part of A or part of B is included in the output. A OR B
A OR B OR C
Venn diagram for AND operator The AND representation of Venn diagram is as follows. In ‗AND‘ operation between A and B, the output will be the area which is common to both A and B. Similarly, the output will the area common to both A and B and C. A AND B
A AND B AND C
Venn diagram for NOT operator The NOT representation of Venn diagram is as follows.Any area in the diagram which is A and not part of B is included for the operation A NOT B. Similarly, for B NOT A, the area of B, which excludes any area of A, is the output. A NOT B
B NOT A
Mixed operators with and without Parenthesis (A AND B) OR C
A AND B OR C
Other Boolean functions NAND A NAND gate is an inverted AND gate. It is equivalent to an AND gate followed by a NOT gate at its output. The symbol for NANDgate is an ANDgate with a bubble at its end. The truth table and the symbol for NAND gate is given below: A
B
R
(Input)
(Input)
(Output)
0
0
1
0
1
1
1
0
1
1
1
0
NOR A NOR gate is an inverted OR gate. If the outputs from a normal OR gate is subjected to a NOT operation, we obtain the NOR gate. The symbol for NOR gate is an OR gate with a bubble at its end. The truth table and symbol for NOR gate is as follows: A (Input)
B (Input)
R (Output)
0
0
1
0
1
0
1
0
0
1
1
0
XOR XOR or Exclusive-OR gate is a digital logic gate which outputs a high when only one of the inputs is high. So if both the inputs are same, either low (‗0‘) or high (‗0‘), the output will be low or ‗0‘. The output of an XOR gate is true only when exactly one of its inputs is true or ‗1‘. The truth table and symbol for a XOR gate is given below:
A (Input)
B (Input)
R (Output)
0
0
0
0
1
1
1
0
1
1
1
0
XNOR A XOR gate with a NOT gate at its output gives a XNOR gate. The output of the XNOR gate is equivalent to that of XOR gate with its output values inverted. The truth table and symbol for a XNOR gate is given below: A
B
R
(Input)
(Input)
(Output)
0
0
1
0
1
0
1
0
0
1
1
1
A B
R = NOT (AXOR B)
A A B B
A
B
B
Examples a) Implement XOR gate using NAND gate R = A XOR B = NOT [NOT {AANDNOT (AANDB)} ANDNOT {BANDNOT (AANDB)}] A R A B B
A
A
B
B
B
b)
Implement XOR gate using basic gates(OR,NOT,AND) i)
R = A XOR B = (đ??€đ?? + đ?? đ??€) ={A AND (NOT B)} OR {B AND (NOT A)}
ii)
R = A XOR B =(đ??€ + đ?? ) đ??€đ?? = (A OR B) AND NOT (A AND B)
Questions 1. Draw the symbols and truth tables for basic gates. 2. State and prove DeMorgan‘s theorem. 3. Using truth tables show that A (B+C) =AB+AC 4. Using truth table prove double negation law. 5. Using truth table prove associative law. 6. Explain the use of Venn diagram with suitable examples. 7. State and illustrate the laws of Boolean algebra.
Unit VII Flip-flops and latches Flip-flops and latches are the basic elements of a memory, which is storing information. One flip-flop or latch can store one bit of information. Flip flop and latches are different in the way their output changes. In a flip-flop, the output changes with input change only during the rising/falling edge of the enable signal, which is usually a clock signal. After or before the rising/falling edge of the enable signal, the output won‘t change, even if the input is changed. In a latch, unlike the flip-flops, the output will change whenever the input is changing provided an enable signal is present. As long as the enable signal is present, output of a latch will change with varying input. But if the enable signal is removed, the output will not change. There are four different types of latches and flip-flops: SR, D, JK and T. SR Latch/Flip-flop
The SR or Set-Reset flip-flops maintains a stable output even after the inputs are turned off. It has two inputs, the S or set input and R or reset input. The output Q of the SR flip-flop is high when a signal is applied at the set input and the output becomes low when an input is applied at the reset input. One of the disadvantages of SR flip-flop is that when S=R=0, the output becomes unstable. This problem is solved in JK flip-flops. S
R
Q(t)
Q(t+1)
0
0
0
1
0
0
1
1(after S=1, R=0)
0
1
0
0
0
1
1
0 (after S=0, R=1)
1
0
0
1
Logic diagram using NAND gates A logical realization of the SR flip-flops using NAND gates is shown above. Q and Q‘ show the current and next state of the outputs. This NAND gate flip-flop works normally with 1s in their inputs unless the state of the flip-flop need to be changed. A 0 applied momentarily to the set input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1. This condition should be avoided in normal operation. This is achieved through a clocked SR flip-flop. Clocked SR flip-flop The clocked SR flip-flop shown below consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.
a) Logic diagram of Clocked SR flip-flop
b) Truth table
D Latch/Flip-flop A D flip-flop or a ‗data‘ or ‗delay‘ flip-flop tracks the input and changes the value of output based on the input. During the rising or falling edge of a clock signal, the input value is captured and the output Q becomes this input value. During other times of the clock signal, the output remains unchanged. This flip-flop is also called a memory unit since it stores the value at its input. The D flip-flops can be rising edge triggered flip-flops or falling edge triggered flip-flops. In rising edge triggered flip-flops, the output changes with input at the rising edge of the clock signal and the latter version, the output changes during the falling edge of the clock signal. The symbol and a NAND gate realization of the D-flip-flop is shown below:
Fig. D flip-flop D
Q(t)
Q(t+1)
Operation
0
0
0
Reset
0
1
0
Reset
1
0
1
Set
1
1
1
Set
Fig. Truth table
Fig. Logical diagram The above figure shows a D flip-flop using a NAND gate. If the input is 1, the flipflop switches to the set state and if the input is 0, the output is switched to the clear state.
JK flip-flops As the name indicates, this flip-flop has two inputs, J and K. When JK=00, the flip flop resets. When JK = 01, the flip flop resets. When JK = 10, the flip flop sets. When JK = 11, the flip flop toggles. These flip-flops are used for minimization purposes.
Fig. JK Flip-flop J
K
Q(t)
Q(t+1)
Operation
0
0
0
0
Hold
0
0
1
1
Hold
0
1
0
0
Reset
0
1
1
0
Reset
1
0
0
1
Set
1
0
1
1
Set
1
1
0
1
Toggle
1
1
1
0
Toggle
Fig. Truth table
Fig. Logical diagram A JK flip-flop is a combination of a D and T flip-flop. T flip-flops
The T stands for toggle in this flip-flops. It is equivalent to a JK flip-flop with its input tied together. Thus it is a single input version of the JK flip-flop. The output of the T flip-flop toggles with each clock pulse, that is, if the output is 0 and at the trigger of the clock pulse, output becomes 1 and again due to the next trigger, output is 0 and so on.
Fig. T Flip-flop T
Q(t)
Q(t+1)
Operation
0
0
0
Hold
0
1
1
Hold
1
0
1
Toggle
1
1
0
Toggle
Fig. Truth table
Fig. Logic diagram Questions 1. Is there any difference between a flip flop and a latch? 2. Can you find specific uses for each flip flop? 3. We need a cell which can retain a bit as itself, until we change it externally. Which is the model suited? 4. Differentiate SR flip flop and clocked SR? 5. Draw the truth table and symbol diagram for each flip flop.
Unit VIII Realizing Boolean Functions: Two dual canonical forms of any Boolean function are a "sum of minterms" and a "product of maxterms." The term "Sum of Products" or "SoP" is a disjunction (OR) of minterms. "Product of Sums" or "PoS" is a conjunction (AND) of maxterms. Sum-of-products form (SOP) Boolean expression consisting of a sum of terms where each term is a ―product ―containing exactly one instance of every variable, e.g., F1 (A,B,C) = A‘BC + A‘BC + ABC‘ Here a function is expressed using variables that yield a function value of 1. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F(A,B,C) 0 1 0 0 1 0 0 1
F‘(A,B,C) 1 0 1 1 0 1 1 0
Fig. Truth table for SOP expression F = A‘B‘C+AB‘C‘+ABC =∑m (1, 4, 7) 001
100
111
Minterms A minterm is a product of literals or variables, in which each input variable appears only once. So a function with ‗n‘ input variables has 2đ?‘› minterms. A minterm is represented by đ?‘šđ?‘— . For example, function with two input variables f(a,b) has 22 = 4 minterms. A function with three input variables, f(a,b,c) has 22 = 8 minterms.
The 8 minterms of f(A,B,C) are given by đ??´â€˛đ??ľâ€˛đ??śâ€˛, đ??´â€˛đ??ľâ€˛đ??ś , đ??´â€˛đ??ľđ??śâ€˛, đ??´â€˛đ??ľđ??ś, đ??´đ??ľâ€˛đ??śâ€˛, đ??´đ??ľâ€˛đ??ś, đ??´đ??ľđ??śâ€˛, đ??´đ??ľđ??ś. Each of these minterms are true for only one combination of inputs. The first minterm đ??´â€˛ đ??ľ ′ đ??ś ′ represented by đ?‘š0 is true only for đ??´ = 0, đ??ľ = 0, đ??ś = 0. The fifth minterm đ??´đ??ľ ′ đ??ś ′ represented by đ?‘š4 is true only for đ??´ = 1, đ??ľ = 0, đ??ś = 0. Similarly the last or eighth minterm đ??´đ??ľđ??ś represented by đ?‘š7 is true only for đ??´ = 1, đ??ľ = 1, đ??ś = 1. In a truth table, the minterms represent the combination of input variables where the output is ‗1‘. In the above truth table, the function F and F‘ can be represented as a sum of minterms: đ??š = đ??´â€˛ đ??ľ ′ đ??ś + đ??´đ??ľ ′ đ??ś ′ + đ??´đ??ľđ??ś = đ?‘š1 + đ?‘š4 + đ?‘š7 =
đ?‘š(1,4,7)
đ??š ′ = đ??´â€˛ đ??ľ ′ đ??ś ′ + đ??´â€˛ đ??ľđ??ś ′ + đ??´â€˛ đ??ľđ??ś + đ??´đ??ľ ′ đ??ś + đ??´đ??ľđ??ś ′ = đ?‘š0 + đ?‘š2 + đ?‘š3 + đ?‘š5 + đ?‘š6 =
đ?‘š(0,2,3,5,6)
Here F‘ contains all the minterms not in F. Product of Sum (POS) Boolean expression consisting of a product of terms where each term is a ―sum‖ containing exactly one instance of every variable, e.g., F2(A,B,C) = (A‘+B+C) (A+B‘+C) (A‘+B‘+C) A
B
C
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
F(A,B,C ) 0 1 0 0 1 0 0 1
F‘(A,B, C) 1 0 1 1 0 1 1 0
Fig. Truth table F(A,B,C)=(A‘+B‘+C)(A+B‘+C‘)(A+B+C) = � M(2,4,7) 001
100
111
Maxterms A maxterm is a sum of literals or variables, in which each input variable appears only once. So a function with ‗n‘ input variables has 2đ?‘› maxterms. A maxterm is represented byđ?‘€đ?‘— . For example, function with two input variables f(a,b) has 22 = 4 maxterms. A function with three input variables, f(a,b,c) has 22 = 8 maxterms. The 8 maxterms of f(A,B,C) are given by (đ??´ + đ??ľ + đ??ś), (đ??´ + đ??ľ + đ??ś ′ ), (đ??´ + đ??ľ ′ + đ??ś), (đ??´ + đ??ľ ′ + đ??ś ′ ), (đ??´â€˛ + đ??ľ + đ??ś), (đ??´â€˛ + đ??ľ + đ??ś ′ ), (đ??´â€˛ + đ??ľ ′ + đ??ś), (đ??´â€˛ + đ??ľ ′ + đ??śâ€˛). Each of these maxterms are false for only one combination of inputs. The first maxterm (đ??´ + đ??ľ + đ??ś) represented by đ?‘€0 is false only for đ??´ = 0; đ??ľ = 0; đ??ś = 0. The fourth maxterm đ??´ + đ??ľ ′ + đ??ś ′ represented by đ?‘€3 is false only for đ??´ = 0; đ??ľ = 1; đ??ś = 1. Similarly the second-last or seventh maxterm (đ??´â€˛ + đ??ľ ′ + đ??ś) represented by đ?‘€6 is false only for đ??´ = 1; đ??ľ = 1; đ??ś = 0. In a truth table the maxterms represent the combination of input variables where the output is ‘0’. In the above truth table, the function F and F‘ can be represented as a product of maxterms: đ??š = đ??´ + đ??ľ + đ??ś đ??´ + đ??ľ ′ + đ??ś đ??´ + đ??ľ ′ + đ??ś ′ đ??´â€˛ + đ??ľ + đ??ś ′ đ??´â€˛ + đ??ľ ′ +đ??ś
= đ?‘€0 đ?‘€2 đ?‘€3 đ?‘€5 đ?‘€6 =
đ?‘€(0,2,3,5,6)
đ??š ′ = đ??´ + đ??ľ + đ??ś ′ đ??´â€˛ + đ??ľ + đ??ś đ??´â€˛ + đ??ľ ′ + đ??ś ′ = đ?‘€1 đ?‘€4 đ?‘€7 =
đ?‘€(1,4,7)
Here F‘ contains all the maxterms not in F.
Karnaugh maps A Karnaugh map or K-map is used to simplify a Boolean expression. It is a grid-like representation of the truth table and has 1 or 0 values at different positions. This representation allows easy grouping of terms that can be combined together. Thus expressions with common factors will be grouped together and unwanted variables will be eliminated. The following figure shows the truth table and K-map for a twovariable problem. The values in the K-map are from the output section of the truth table. ‗A‘ and ‗B‘ has values or co-ordinates as 0 and 1, and A is along the top, while
B along the columns. The values of the variables a, b, c and d are given in the second figure.
(a)
(b)
Example 1: Consider the Boolean expression: đ?‘‹ = đ??´đ??ľ + đ??´đ??ľ This expression can be plotted using K-maps as follows:
ďƒ˜ As explained above, the two 1‘s are plotted in the above chart. ďƒ˜ Since the two 1‘s are in the same column, they are grouped together. ďƒ˜ This pair contains, B as ‗0‘ and B as ‗1‘ and A as ‗1‘. Since B has both 0 and 1 values, B is cancelled and what is left is A (since the value of A is 1). ďƒ˜ So the expression is simplified as X = AB + AB = A
Algebraically, if we solve, 
X = AB + AB = A B + B = A
Example 2: Consider the Boolean expression đ?‘‹ = đ??´đ??ľ + đ??´đ??ľ + đ??´đ??ľ The K-map for this expression is given below:
ďƒ˜ Now the 1‘s in same row and column are grouped together as two pairs. ďƒ˜ In the pair I, A has values 0 and 1, while B has value 0. So A will be cancelled and what is remaining is B(since the value of B is 0). ďƒ˜ In the pair II, A has value 0, and B has its true(‗1‘) and false(‗0‘) values. So B is cancelled here and since the corresponding A value for this pair is ‗0‘, what remains is A. ďƒ˜ So the final expression is X = AB + AB + AB = A + B
4-variable K-maps The following example will show the four variable K-map. The variables can be written in any order. In the above example, the A is written on top along the columns and B is on bottom along the rows. It can be the other way too. In the following example, the variable combination AB is written on bottom along the rows and CD is written on top along the columns. Example: 4-variable K-maps đ?‘‹ = đ??´đ??ľđ??ś đ??ˇ + đ??´đ??ľđ??śđ??ˇ + đ??´đ??ľđ??ś đ??ˇ + đ??´đ??ľđ??ś đ??ˇ + đ??´đ??ľđ??śđ??ˇ + đ??´đ??ľđ??śđ??ˇ + đ??´đ??ľ đ??śđ??ˇ + đ??´đ??ľ đ??śđ??ˇ
Fig. Drawing K-map
Fig. Grouping terms in the K-map The first group(lablelled as AB) has four 1‘s and here both C and D has values of 0 and 1. So they cancel each other. Thus we get only AB. In the second group (labelled as BD), the four 1‘s is in a square pattern, and C has both 0 and 1 values, thus C is cancelled. D has only one value of ‗1‘, so it remains. A has values 0 and 1 , but B has only value 1. Thus A is cancelled and B remains. This grouping gives BD. In the last group, D and B has values 0 and 1; they are cancelled. What remains is AC. Thus the simplified expression is: đ?‘‹ = đ??ľđ??ˇ + đ??´đ??ś + đ??´đ??ľ The Quine-McCluskey Method The Quine-McCluskey method is used for finding the prime implicants or a minimum-cost Sum-of-Products (SOP) implementation of Boolean function. It is used
instead of K-maps when the number of variables are very large. The QuineMcCluskey method basically consists of two steps: a) Finding the Prime implicants: These are the terms resulting from applying xy + xy ′ = x to the given Boolean expression. b) Creating the Prime implicant table: Using this table, the prime implicants are reduced and solved to obtain the reduced logical expression. Finding prime implicants The functions which are given in minterms form, that is, sum of min terms are reduced using �� + �� ′ = �. A B'C D' + A B'C D = A B'C 1010 |___| X Y
+1011 |___| X Y'
= 1 0 1 - (dash indicates missing variable) |___| X
In the above case, first three variables are taken as x and the last variable is taken as y. Example: Find đ?‘“ đ?‘Ž, đ?‘?, đ?‘?, đ?‘‘ = 
đ?‘š(0,1,2,5,6,7,8,9,10.14)
Group the terms based on number of ‗1‘ Group 0 - (0) Group 1 - (1, 2, 8) Group 2 - (5, 6, 9, 10) Group 3- (7, 14)

This function is represented by the following minterms, and is used to find the prime implicants.
Fig. Determining Prime implicants – step 1
Fig. Determining Prime implicants – step 2
Fig. Determining Prime implicants – step 3 From the above prime implicants we get the expression: f = a′ c ′ d + a′ bd + a′ bc + Corresponding to: (2,6,10,14)
(1,5)
(5,7)
b′ c ′
+
(6,7)
b′ d′ (0,1,8,9)
+
cd′ (0,2,8,10)
The following is the Prime implicant chart:
Fig. Prime implicants chart Questions 1. Write short notes on sum of products and product of sums forms. 2. Write examples for sum of product and product of sums expressions. 3. Inspect each of these Boolean expressions, and determine whether each one is a sum of products, or a product of sums:
(B + C + D)( A
A B C+ A
+ B)
BC
(X +Y +Z )( Y + Z)(X
+ Y)
4. What are max terms and minterms? 5. Practice drawing Karnaugh maps of various Boolean functions. 6. Simplify the Product-Of-Sums Boolean expression below, providing a result in SOP form.
Module IV
Digital Circuits
UNIT IX
DIGITAL CIRCUITS Multiplexer A multiplexer is a combinational digital logic switching device that has multiple inputs and one output. In addition to the input and output lines, the multiplexer has data select lines through which the data passed from an input line to the output line is determined . Following Fig. 1 shows the general idea of a multiplexer with n input signal, m control signals and one output signal;where N=2^M.
Fig. 1. N-input multiplexer [1]
A 2:1 Mux and its truth table is shown below in fig.2 ,showing 2 inputs (A and B),1 output and one select line(sel).If sel=1, A is connected to out and if sel=0, then B is connected to out.
A 0 0 1 1 0 0 1 1
B 0 1 0 1 0 1 0 1
se1 0 0 0 0 1 1 1 1
out 0 0 1 1 0 0 1 1
Fig.2. (a) A 2:1 Multiplexer (b) Truth table [1]
4:1MUX using gates The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output bit. Fig.3. shows a 4:1 multiplexer and its truth table. The four input bits are D0,D1,D2 and D3. Only one of this is transmitted to the output Y. The output depends on the value of AB which is the control input. The control input determines which of the input data bit is transmitted to the output. For instance, as shown in fig. when AB = 00, the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit D0 is transmitted to the output, giving Y = Do.
A 0 0 1 1
B 0 1 0 1
Y D0 D1 D2 D3
Fig. 3. (a) 4:1 Multiplexer (b) Truth table [1] Demultiplexer Demultiplexer means one to many. A demultiplexer is a circuit with one input and many output. By applying control signal, we can steer any input to the output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer. Following figure illustrate the general idea of a demultiplexer with 1 input signal, m control signals, and n output signals.
Fig. 4. A ‗n‘ input demultiplexer
1:4 Demultiplexer The 1-to-4 demultiplexer has 1 input bit, 2 control bit, and 4 output bits. The input bit is labelled as Data D. This data bit is transmitted to the data bit of the output lines. This depends on the value of AB, the control input. When AB = 01, the upper second AND gate is enabled while other AND gates are disabled. Therefore, only data bit D is transmitted to the output, giving Y1 = Data.
If D is low, Y1 is low. IF D is high,Y1 is high. The value of Y1 depends upon the value of D. All other outputs are in low state. If the control input is changed to AB = 10, all the gates are disabled except the third AND gate from the top. Then, D is transmitted only to the Y2 output, and Y2 = Data.
Fig. 5. A 1:4 Demultiplexer
Adders Half Adder: is a combinational circuit that performs the addition of two bits, This circuit needs two binary inputs and two binary outputs. 1-bit adder can be easily implemented with the help of EXOR Gate for the output ‗SUM‘ and an AND Gate for the carry.
A 0 0 1 1
B 0 1 0 1
Sum 0 1 1 0
Carry 0 0 0 1
Fig. 6. (a) Half-adder (b) Truth table (c) Schematic symbol of half adder Full adder
Fig. 7 A 1-bit Full adder The main difference between a half-adder and a full-adder is that the fulladder has three inputs and two outputs. The first two inputs are A and B and the third
input is an input carry designated as CIN. The output carry is designated as COUT and the normal output is designated as S. A
B
Cin
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Fig. 8 Truth table for a Full-adder
Fig. 9. Schematic of a full adder [1]
Decoders and Displays A decoder is a combinational type logical circuit which converts the binary data into an equivalent decimal code. An n-to-2n decoder has an n-bit input and produces 2n output lines. Based on the input, the decoder receives; it activates only one line of the 2n output lines and all the other output lines will be deactivated. Some common decoder configurations are 2-to-4, 3-to-8, 4-to-16 decoders. 2-to-4 Binary Decoder A 2-to-4 binary decoder is shown in Fig. 10 This decoder takes 2 inputs and converts it into the corresponding decimal code. Since these ‗decode‘ the binary input, they are also called Address decoders.
A
B
D0
D1
D2
D3
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
Fig. 10 (a) A 2-to-4 decoder (b) Symbol of the decoder (c) Truth table [1] Here, there are two inputs A and B and can have four combinations of the input data or 2-bits. This decoder is constructed using AND gates. Depending on the binary input, any one line D is selected as output. The line which is at a logical HIGH
is the selected output line among D0 to D3. All the other lines will be at LOW state. The line which is high represents the decimal code for the corresponding binary input. In the truth table, for each set of input, only one line is HIGH or activated. When A=0 and B=1, only D1 is activated. 7-Segment Display A 7-segment display is shown in Fig. 11These are made of a common anode or cathode display LEDs. By displaying the 7 diodes in different patterns, numbers or letters can be formed on this display.
Fig.11. A 7-segment display [1] Individual segments a x x x x x x x x x
b x x x x x
x x x x
c x x x x x x x x x x x
x x x x
x
d x
e x
x x
x
x x x x x x x x
x x x x x x x x
f x
x x x x x x x x x x
g
x x x x x x x x x x x x
Display 0 1 2 3 4 5 6 7 8 9 A b C d E F
Fig. 12. A truth table showing the display patterns of a 7-segment display for different numbers and letters (b) numbers with labels of which elements are displayed [1]
The truth table in Fig. 12, shows which of the seven diodes needs to be activated for a particular letter. For example, the letter 1 can be displayed using the diodes b and c. If all the seven diodes are displayed, it is number 8. Thus, different letters and numbers can be formed by illuminating different diodes. BCD to 7-Segment Display decoder BCD to 7-segment display encoder converts the binary coded input signal into a 7 line output enough to describe which diodes needs to be illuminated. The following Fig 13 shows a BCD to 7-segment display decoder.
Fig. 13 A 4-bit BCD to 7-segment decoder [1]
This decoder takes a 4-bit BCD signal and converts it into an output which is used for activating the diodes ‗a’ to ‗g’. For example, if the input ABCD = 0100 (which is binary equivalent of 4), the decoder decodes this input and ‗abcdefg’ = 0110011. So ‗b‘, ‗c‘, ‗f‘, ‗g‘ are activated and a number 4 is displayed on the 7-segment display. This decoder can convert numbers from 0 to 9 for displaying in the 7-segment display.
Encoders – Priority encoders A Digital encoder or binary encoder takes in multiple input data and converts them into a single encoded output based on the active input line. An ‗n-bit‘ binary encoder has 2n input lines and ‗n-bit‘ output lines. Some of the common encoder configurations are 4-to-2, 8-to-3, 16-to-4 encoders. 4-to-2 bit binary encoder Here, four input lines are encoded to give a 2-bit output. This does the exact opposite of what a 2-to-4 bit decoder does. The following Fig.14& 15 shows a 4-to-2 bit binary encoder and its truth table. Four input lines are present from D0 to D3 which are encoded to give two output bits Q0 and Q1.
Fig. 14. A 4-to-2 bit encoder
Inputs
Outputs
D3
D2
D1
D0
Q1
Q0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
x
x
Fig. 15. Truth table for a 4-to-2 bit encoder Here, four different cases are present, where in each one, only one of the input lines are active. Depending on which of the D lines are active, the value of output Q varies between the four possible values. When no lines are active at the input, it is an
invalid condition. Also if more than one input lines are active, it is an invalid condition. This problem is solved in Priority encoders.
Priority encoders Priority encoder is the encoder in which there are multiple lines as active inputs. A disadvantage with the above binary encoder is that, if more than one input lines are active at any given time, there is an error. Priority encoder solves this problem by allocating a priority level to each input. A priority encoder encodes the output corresponding to the active input line with the highest priority. If two or three lines are active at the same time, only the line which has the highest priority is encoded and the rest of the input lines are ignored. The following truth table for a 2-to-4 bit priority encoder is shown in Fig. 16.Here, if D3 and D1 are on at the same time, then it encodes D3 or the last case in the truth table since D3 has the highest priority. Since D3 has the highest priority, when D3 is active, even if all of the other input lines are active, it doesn‘t affect the output. This is a good advantage compared to the binary encoders. Inputs
Outputs
D3
D2
D1
D0
Q1
Q0
0
0
0
1
0
0
0
0
1
x
0
1
0
1
x
x
1
0
1
x
x
x
1
1
Fig. 16. A 4-to-2 bit priority encoder (D0 is the lowest priority and D3 is the highest priority) Keyboard encoder A keyboard encoder is a type of priority encoder used to generate a code based on the keys pressed in a keyboard for the computer or attached device to identify, which key is being pressed. When a key or keys are pressed, these inputs are given to the keyboard encoder which converts these inputs into an 8-bit ASCII code. All the keys in a keyboard are fed into the encoder as individual input lines. Each key has two states, HIGH or LOW. When a key is pressed this input line toggles from 0 to 1 or from 1 to 0. This change is encoded by the encoder and converted into an ASCII code. For a 104 key keyboard, 7 bit encoder is needed, since it can accommodate 2 7=128 input lines.
Comparator A digital comparator or magnitude comparator is a device which compares two numbers at its input. The numbers at input are in the binary form and the comparator determines whether one number is greater than, less than or equal to the other number. Comparators are used in a central processing units (CPU) and microcontrollers. Digital comparators are a combination of AND, OR and NOT gates. A digital comparator can be of two types: Identity comparator, which has only one output terminal which gives HIGH when both inputs equal to ‗1‘ and LOW when both inputs are equal to ‗0‘. In a magnitude comparator, there are three output terminals for checking equality, greater than and less than. 1 bit comparator A 1-bit comparator constructed using NOT, AND and XOR gates is shown in Fig 17 Three different conditions are checked using this circuit and works based on the truth table given below. Only one bit of data is compared against another one bit of data. A and B can have values of ‗0‘ or ‗1‘.
Input
Output
A
B
A>B
A=B
A<B
0
0
0
1
0
1
0
1
0
0
0
1
0
0
1
1
1
0
1
0
Fig. 17 (a) A 1-bit comparator (b) Truth table [1]
4-bit Magnitude comparator
Following in Fig. 18is a 4-bit comparator where the input data can be up to four bits. The comparator checks for the relation between the two inputs by comparing their Least Significant Bits (LSB) to Most Significant Bits (MSB).
Fig. 18. A 4-bit Magnitude Comparator [1]
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ď&#x201A;ˇ
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Counters A Counter is a digital sequential circuit which counts the pulses. Counter contains a set of flip-flops with a clock signal. Counters are generally divided into two types: Asynchronous and Synchronous counters. In Asynchronous counters, the clock pulse is applied to the flip-flops individually. In Synchronous counters, all the flipflops receive the same clock pulses simultaneously. Counters are widely used in
frequency counters, analog to digital converters, digital clock, frequency divider circuits etc. Modulus: Counters consists of flip-flops which are connected or cascaded together. The number of stages of the counter determine what type the counter is. A binary counter with ‗n‘ counter stages form a ‗divide-by-n‘ counter or Modulus. The Modulus or MOD refers to one complete cycle of the counter or the number of output states the counter goes through before returning a zero value. A counter which has ‗n‘ flip-flops will count from 0 to (2n -1). Thus a counter with three flip-flops or a 3-bit counter will count from 0 to 7 or 23 - 1. A 3-bit binary counter is called modulo-8 or MOD-8 counter (23=8). A 4-bit binary counter is called modulo-16 or MOD-16 counter (24=16). Similarly, an 8-bit counter is called modulu-256 or MOD-256 counter (28=256). Asynchronous counters In asynchronous counters, the clock pulses will be different for different flipflops and are not applied simultaneously. Asynchronous counters are implemented using ‗divide-by-n‘ counter circuits. The output of any flip-flops in this counter depends on the previous flip-flop‘s output. Asynchronous counters are also called ripple counters since the data appears to ripple from output of one flip-flop to the input of the next till it reaches the output. Asynchronous counters can be made from T or D type flip-flops. 2-bit ripple counter The counter is made using Toggle or T flip-flops. For 2-bit, as explained earlier, 2 flip-flops are needed. The CLK signal is given to the first flip-flop and for second flip-flop, the clock signal is the output of the first flip-flop. This is shown in Fig. 19.
Fig. 19. A 2 bit asynchronous ripple counter [3]
Here at the initial stage, both flip-flops are in the reset conditions.So QA=QB=0.These flip-flops are negative edge triggered flip-flops and are activated or toggle at the negative edge of a clock pulse. At the positive edge, the flip-flop is unaffected. Counter output Clock Initially
QA
Decimal counter output
0
0
-
0
st
0
1
1
1
nd
1
0
2
2
rd
1
1
3
3
th
0
0
4
0
1 2
QB
State number
3
4
Fig. 20 Truth table for a 2-bit ripple counter [3]
After one negative clock edge, the FFA will toggle and QA=1. Since QA is connected to the clock of FFB, a change of 0 to 1 is effected at the clock of FFB, but since this is a positive transition, the FFB is unaffected. So after the first clock pulse, QBQA= ‗01‘. At the second negative clock edge, FFA toggles and now QA=0. This changes the clock of FFB from 1 to 0, which is a negative transition. This triggers FFB and now QB=1. So after second clock pulse, QBQA = 10 At 3rd negative clock edge, FFA toggles and QA =1. This is passed to the clock of FFB, but a positive transition of the clock for FFB from 0 to 1 doesn‘t affects its output. So QBQA = 11 At 4th negative clock edge, FFA toggles again and now QA =0. This triggers the clock of FFB and thus FFB toggles and QB=0. Now after the fourth clock pulse, QBQA=00. The counter now stops counting as it came back to 0 and the truth table for this circuit is shown in Fig 20.
Synchronous counters
In synchronous counters,the clock pulse is given directly to all the flip-flops. So all the flip-flops simultaneously receive the clock pulse and triggers instantly. Since the clock pulse is fed in parallel to all the flip-flops, these counters are also called parallel counters. Synchronous counters have advantages over asynchronous counters: easier to design, overall faster operation, no propagation delay since clock pulses applied in parallel. Synchronous counters operate on the rising (positive) edge or the falling (negative) edge of the clock pulse. 2-bit up counter A 2-bit synchronous up counter is shown in Fig 21. JK flip-flops are used for this counter. The J and K inputs of FFA are tied to logic 1, so this flip-flop acts as a Toggle flip-flop. The J and K inputs of FFB are connected to the output of FFB. Here, the CLK or clock pulse is given simultaneously to both the flip-flops.
Fig. 21. A 2-bit synchronous up counter [3] Here, at the initial state, QBQA = 00. The flip-flops are negative edge triggered flipflops. At the first negative clock edge, FFA toggles and QA changes to 0 to 1. Even though this change is affected at JB and KB, but the output of FFB wonâ&#x20AC;&#x2DC;t change because at the instant of the negative edge pulse, JB=KB=0. So after first clock pulse, QBQA=01. At the second negative clock edge, FFA again toggles and QA changes from 1 to 0. This makes JB=KB=0 after this clock edge. But at the instant of clock pulse, JB =KB= 1 due to the first clock pulse. So this negative edge triggers FFB and now QB changes from 0 to 1. So after second clock pulse, QBQA=10 At the 3rd negative clock edge, FFA toggles and QA changes from 0 to 1 which is effected at JB and KB. Since at the instant of clock pulse, JB=KB=0, so FFB is not affected here. Now, QBQA=11
At the 4th negative clock edge, FFA again toggles and QA changes from 1 to 0. JB=KB=1 from the 3rd clock pulse and so QB changes from 1 to 0. Now QBQA=00. Thus when the counter reaches the zero state, the counting is done. Shift Registers The Shift Register is a sequential logic circuit which stores or transfers the binary data. It basically "shifts" the data out once every clock cycle, hence the name "shift register". Shift registers are constructed using D flip-flops or latches in a serial fashion such that, output of each D latch is the input to the next D latch. A Shift register IC is composed of several latches of these kinds based on the requirements. They have a SET or RESET switch which does the clear and reset functions respectively. The different types of shift registers are given below:
Serial-in to Parallel-out (SIPO): In this shift register, the input is given in a serial manner one bit at a time and the output is available in parallel form.
Serial-in to Serial-out (SISO): Here, both the input and output are shifted in a serial fashion at one bit per clock cycle.
Parallel-in to Serial-out (PISO): Here, the input data is given to the register in parallel or simultaneously but the output is available serially one bit at a time.
Parallel-in to Parallel-out (PIPO): In this shift register, the input data is applied simultaneously at the input of the register and the output bits are available at once after one duration of the clock pulse.
Serial input Parallel output (SIPO) Shift Register
A 4 bit SIPO shift register is shown in Fig 22. As explained above, the inputs are given in a serial fashion and the outputs are available at once, after one cycle of the clock pulse. The operation is as follows. Let‘s assume that all the flip-flops (FFA to FFD) have just been RESET (CLEARinput) and that all the outputs QA to QD are at logic level "0" i.e., no parallel data output. If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0.
Fig 22. A4-bit Serial Input Parallel output shift register [1]
Here, the initial state is that all the flip-flops are just cleared and the input is given. Now when there is no input, all the outputs Q will be ‗0‘. Suppose a 4-bit binary number ‗1011‘ is to be stored in this shift register. The first input is ‗1‘. After the first clock pulse, this ‗1‘ at the input of FFA is shifted to its output. So QA =1 and QB = QC = QD = 0. Let the second input is another ‗1‘. Now after the second clock pulse, this one is shifted to QA and the ‗1‘ which was present at QA or input of FFB is shifted to its output QB. The ‗0‘ already present in output of FFB is now shifted to FFC. And the ‗0‘ present at the output of FFC is shifted to FFD. So QC =QD = 0. Suppose the third input is ‗0‘. After the third clock pulse, QA =0, QB =1, QC = 1, QD = 0. If the fourth input is ‗1‘, the fourth clock pulse would result in QA =1, QB =0, QC =1, QD = 1. Thus each input is shifted through these flip-flops but the outputs are available simultaneously. After four clock pulses, the output ‗1101‘ is available at the outputs of four flip-flops. Serial-in to Serial-out (SISO) In this shift register, the inputs are send serially and the outputs are available in a serial manner one bit at a time. This is why it is called Serial-in serial-out shift register. In the fig.23, four flip-flops are present. The serial data is given through Data in and output can be seen at Data out.
Fig 23 4-bit Serial in Serial out shift register [1]
Suppose in the above shift register, a 4-bit data needs to be stored. This process is same as that of a SIPO shift register, the only difference is that, the outputs are not available simultaneously. Here the input 0101 is send from Data in, serially at the rate of one bit per clock pulse and after four clock pulses, the bits are stored at the output of the flip flops A to D. Now if this data needs to be used, it has to be shifted and each bit will come serially at the output. Parallel-in to Serial-out (PISO) The Parallel input Serial output shift register has parallel inputs and the outputs are available serially. This is opposite to the Serial input Parallel output shift registers. Here, all the inputs are available to each of the flip-flops at the same time. A 4-bit PISO shift register is shown in Fig 24. The main difference from the above two registers is that, no clock pulse is required to input the data, since it is available in parallel to all the inputs. But a clock pulse is required to output the data out of the shift register.
Fig 24. A 4-bit Parallel in Serial out shift register.[6] In this shift register, the 4 bits of input data is made available to the flip-flops 1 to 4,, using a multiplexer at the input of every flip-flop. The 4-bit input is instantly available at all flip-flops. In order to unload this data, the four clock pulses are required to push or shift the data through each of the flip-flops so that each bit comes sequentially at the output.
Parallel-in to Parallel-out (PIPO) In this shift register, the inputs and outputs are available simultaneously at the inputs and outputs of the flip-flop. This shift register of the simplest of the four
configurations and has only three connections namely, the Clock pulse, parallel in and Parallel out. A 4-bit shift PIPO shift register is shown below in Fig. 25.
Fig. 25. A 4-bit Parallel-in to Parallel-out Shift Register [1] Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required. The inputs are given parallel to the flip flops. During the first clock pulse, all the inputs are passed to the outputs of the flip-flop and are available simultaneously. No shifting is required for the input of output.
Questions l. Explain 4:1 multiplexer. 2. Explain half adder and full adder circuits using XOR and AND gates. 3. Explain 2 bit magnitude comparator 4. Explain the working of 4 bit asynchronous counter. 5. Distinguish between synchronous and asynchronous counter. 6. Explain working of BCD to 7 segment display. 7. Distinguish between shift registers and counters. 8. Explain various types of shift registers. 9. Which shift register is known as universal shift register and give reason. 10. Explain keyboard encoder. 11.Explain 1:4 demux.
UNIT X DIGITL ICs Digital IC logic: There are three families of digital IC logic:
TTL (Transistor-Transistor Logic)
CMOS (Complementary Metal Oxide Semiconductor)
ECL (Emitter – Coupled Logic)
TTL family TTL came an improvement to the DTL (Diode-Transistor Logic) gates. The input of a TTL logic gate is characterized by a multi-emitter transistor. This multiemitter transistor can be of two or four inputs which is equivalent to two or four p-n diodes. The inputs are the emitters of the transistors. This circuit is also equivalent to a diode based AND gate.Transistors in a TTL circuit are saturated switches, so the speed of the device will be limited by how much minority carriers can be stored. The configurations of a TTL gate can be three types namely, Open-collector circuit, Totem-pole circuit, three state or Tristate output. The current day high speed systems use an Advanced Schottky Transistor-Transistor Logic. Following is an example for a TTL circuit.
Fig. 26. (a) A TTL circuit
In Fig. 26, as the gate contains a single stage inverting NPN transistor circuit (TR2) an output logic level "1" at Q is only present when both the emitters of TR 1 are connected to logic level "0" or ground allowing base current to pass through the PN junctions of the emitter and not the collector. The multiple emitters of TR1 are connected as inputs thus producing a NAND gate function. In standard TTL logic gates, the transistors operate either completely in the "cut off" region, or else completely in the saturated region, Transistor as a Switch type operation. CMOS family The TTL gates has limited operating speed when switching between ON and OFF states. The TTL gates uses bipolar transistors which are current operated devices and consume large amounts of power from the supply. These limitations are resolved in CMOS or Complementary MOS (Metal oxide semiconductor) devices which operate using FETs or Field Effect Transistors. CMOS logic gates use P and N-channel MOSFETs as their input devices and when there is no switching, the power consumption is almost zero, at the quiescent point. This makes them ideal for low powered battery circuits and it has high switching speeds of about 100 MHz. They are used in high frequency timing circuits. Fig. 27 shows an example of a CMOS circuit where, 3 N-channel MOSFETs are used, where two of them are for two inputs, and one is for the output. When both the inputs A and B are at logic level "0", FET1 and FET2 are both switched "OFF" giving an output logic "1" from the source of FET3. When one or both of the inputs are at logic level "1" current flows through the corresponding FET giving an output state at Q equivalent to logic "0", thus producing a NAND gate function.
Fig. 27. Basic CMOS logic gate
ECL family ECL or Emitter Coupled Logic is based on the use of current steering switch. In TTL, the saturation limit prevents the speed of the device. This can be improved using ECL, which makes it a non-saturated digital logic family. ECL is used in high speed circuits and its propagation rate is in the range of 1-2 ns. ECL internally switches or swings between two voltage levels but unlike other logic families, ECL don‘t have a large voltage swing. The voltage swing is less than 1 volts. ECL is powerful but it consumes a lot of power and noise immunity is worse. This is the reason why it is not popular unlike the CMOS or TTL gates. Advantages of ECL gates[5]
ECL gates produce both true and complemented outputs
ECL gates are fast since it the BJTs are always in forward active mode, and it only takes a few tenths of a volt to get the output to change states, hence reducing the dynamic power
ECL gates provide near constant power supply current for all states thereby generating less noise from the other circuits
A basic ECL circuit is show in Fig. 28. Two transistors are connected as differential pair and with a common emitter resistor. It has an inverting (OUT1) and non-inverting output (OUT2). he supply voltages forthis example areVCC = 5.0,VBB=4.0, andVEE=0 V, and the inputLOWandHIGHlevels are defined to be 3.6 and 4.4 V. This circuit actually produces outputLOWandHIGHlevels that are 0.6 V higher (4.2 and 5.0 V), but this is correctedin real ECL circuits. When VINisHIGH, as shown in the figure, transistorQ1is on, but notsaturated, and transistorQ2isOFF. This is true because of a careful choice ofresistor values and voltage levels. Thus, VOUT2is pulled to 5.0 V (HIGH) throughR2, and it can be shown that the voltage drop across R1is about 0.8 V, so thatVOUT1is about 4.2 V (LOW).
Fig. 28 (a) Basic ECL inverter with input HIGH (b) Basic ECL inverter with input LOW
Comparision of Logic families Fan-out: Fan-out of a logic gate represents the maximum number of digital inputs that the output of the logic gate can feed. The fan-out of TTL, CMOS and ECL are listed in the table in Fig ###. If the circuit needs to drive more ouputs, than the logic gates can feed, then a buffer is used at the output of the logic gate (eg. TTL) with greater fan-out. Noise Immunity: Noise immunity of a digital logic gate is the measure of the extent to which the logic circuit can tolerate the noise signals. Power per gate: This shows the power dissipation in the logic gate or is simply the power needed for the operation of the logic gate. More the power per gate, more is the
power dissipation and less economical the logic gate. ECL has the worst power consumption. Propagation time: It is the measure of the time for the logic circuit to change its output after an input is applied. This denotes the speed of the logic gate. More the propagation time, lesser the speed of the device. It is clear from the table, that ECL has high speeds or lower propagation time. Parameter
CMOS
TTL
ECL
Basic gate
NAND/NOR
NAND
OR/NOR
Power per gate (mW)
1 @ 1 MHz
1 – 22
4 – 55
Fan-out
>50
10
25
Noise immunity
Excellent
Very good
Good
1 – 200
1.5 – 33
1–4
Propagation time, t (ns)
Fig. 29. Comparision of logic families [5] Classification of Integrated Circuits (ICs) 1) Small Scale Integration or SSI – Contain up to 10 transistors or a few gates within a single package such as AND, OR, NOT gates 2) Medium Scale Integration or MSI – between 10 and 100 transistors or tens of gates within a single package and perform digital operations such as adders, decoders, counters, flip-flops and multiplexers. 3) Large Scale Integration or LSI – between 100 and 1,000 transistors or hundreds of gates and perform specific digital operations such as I/O chips, memory, arithmetic and logic units. 4) Very Large Scale Integration or VLSI – between 1,000 and 10,000 transistors or thousands of gates and perform computational operations such as processors, large memory arrays and programmable logic devices. 5) Super-Large Scale Integration or SLSI – between 10,000 and 100,000 transistors within a single package and perform computational operations such as microprocessor chips, micro-controllers, basic PICs and calculators.
6) Ultra-Large Scale Integration or ULSI – more than 1 million transistors - the big boys that are used in computers CPUs, GPUs, video processors, microcontrollers, FPGAs and complex PICs. Moore’s Law According to Moore‘s law, ―the number of transistors and resistors on a single chip will double every 24 months‖ . This law was an observation by Gordon Moore, co-founder of Intel corporation in 1965. At that time, on a single chip, there were about 60 transistor gates. After that, the number of transistors on a chip increased year by year approximately according to Moore‘s law. A good contrast of the transistor size given by Intel corp. is ―The original transistor built by Bell labs in 1947 was large enough that it was pieced together by hand. By contrast, today, more than 100 million transistors could fit into the head of a pin‖[source: www.intel.com]. Questions 1.Define Moore‘s law. 2.Compare TTL,CMOS and ECL families. 3.What are the various integration levels? 4.Explain working of TTL as AND gate. 5.Explain the working of a basic ECL inverter. References: [1] http://www.electronics-tutorials.ws/ [2] http://www.ddpp.com/DDPP4student/Supplementary_sections/ECL.pdf [3] http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm [4] http://www.allaboutcircuits.com/vol_4/chpt_3/6.html [5] http://mti.kvk.uni-obuda.hu/adat/tananyag/digit2/angolkepzes/dt_2_lecture09w.pdf [6] https://maxwell.ict.griffith.edu.au/yg/teaching/dns/dns_module3_p3.pdf