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Chapter 06 System Integration and Performance 1. A system bus connects computer system components, including the CPU, memory, storage, and I/O devices. a. True b. False
2. A system bus can be conceptually or physically divided into specialized subsets, including the data, address, control, and power buses. a. True b. False
3. With serial communication lines in a bus, each line carries only one bit value or signal at a time, and many lines are required to carry data, address, and control bits. a. True b. False
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4. Until the 2000s, system buses were always constructed with serial electrical lines. a. True b. False
5. Serial channels in buses are more reliable than parallel channels at very high speeds. a. True b. False
6. Performance is improved if storage and I/O devices can transmit data between themselves with explicit CPU involvement. a. True b. False
7. Peer-to-peer bus protocols are substantially less complex but more expensive than master-slave bus protocols. a. True b. False
8. The memory bus has a much higher data transfer rate than the system bus because of its shorter length, higher clock rate, and (in most computers) large number of parallel communication lines. a. True b. False
9. Secondary storage devices are much faster than the system bus. a. True b. False
10. Devices with low data transfer demand can use a single PCI bus lane, and devices with higher requirements can increase their available data transfer rate by using additional lanes. a. True Cengage Learning Testing, Powered by Cognero
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b. False
11. The CPU communicates with a peripheral device by moving data to or from an I/O port’s dedicated bus. a. True b. False
12. A PC usually transmits data one bit at a time over a wireless connection, and a laser printer prints an entire page at once. a. True b. False
13. A buffer for an I/O device is typically implemented on the sending computer. a. True b. False
14. During a write operation, a cache acts similarly to a buffer. a. True b. False
15. Data written to a cache during a write operation isn’t automatically removed from the cache after it’s written to the underlying storage device. a. True b. False
16. One way to limit wait states is to use an SDRAM cache between the CPU and SRAM primary storage. a. True b. False
17. Disk caching is common in modern computer systems, particularly in file and database servers. a. True Cengage Learning Testing, Powered by Cognero
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b. False
18. The OS is the best source of file access information because it updates information dynamically as it services file access requests. a. True b. False
19. A full-featured 64-bit CPU, even one with multiple ALUs and pipelined processing, typically requires fewer than 50 million transistors. a. True b. False
20. When multiple processors occupy a single motherboard, they share primary storage and a single system bus. a. True b. False
21. Multiple-processor architecture is not common in workstations. a. True b. False
22. Both multicore and multiple-processor architectures are examples of scaling up because they increase the power of a single computer system. a. True b. False
23. Until the 1990s, scaling up was almost always a more cost-effective strategy to increase available computer power because communication between computers was extremely slow compared with communication between a single computer’s components. a. True b. False
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24. The largest computational problems, such as those encountered in modeling three-dimensional physical phenomena, can be solved by a single computer as long as it has enough computing resources. a. True b. False
25. People routinely download megabytes or gigabytes of data via the Internet and store gigabytes of data on handheld devices, terabytes on desktop computers, and petabytes to exabytes in corporate and government data centers. a. True b. False
26. Reducing the size of stored or transmitted data can improve performance whenever there’s a dearth of processing power. a. True b. False
27. Zip files and archives are examples of lossless compression. a. True b. False
28. Lossless compression ratios higher than 50:1 are difficult or impossible to achieve with audio and video data. a. True b. False
29. Using data compression alters the balance of processor resources and communication or storage resources in a computer system. a. True b. False
30. MP3 compresses the audio data stream by discarding information about masked sounds or representing them with fewer bits. Cengage Learning Testing, Powered by Cognero
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a. True b. False
31. A ____ is a shared electrical or optical channel that connects two or more devices. a. trace b. bus c. Route d. connection
32. There are typically multiple storage and I/O devices connected to a computer, collectively referred to as ____. a. core devices b. peripheral devices c. perimeter devices d. companion devices
33. The ____ carries commands, command responses, status codes, and similar messages. a. bus clock b. command bus c. CPU d. control bus
34. Devices attached to a system bus coordinate and synchronize their activities with a common ____. a. bus clock b. control bus c. data bus d. system bus
35. The ____ governs the format, content, and timing of data, memory addresses, and control messages sent across the bus. a. bus clock b. bus size c. bus protocol Cengage Learning Testing, Powered by Cognero
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d. bus master
36. When the CPU is the focus of all computer activity, it’s also the ____. a. bus clock b. bus master c. bus slave d. bus protocol
37. When the CPU is the focus of all computer activity, all other devices are ____. a. bus masters b. bus primates c. bus limiters d. bus slaves
38. Under direct memory access, a device called a ____ is attached to the bus and to main memory. a. controller b. DMA master c. DMA controller d. DRM controller
39. In a ____, any device can assume control of the bus or act as a bus master for transfers to any other device. a. peer-to-peer bus b. star bus c. linear bus d. ring bus
40. A ____ is a simple processor attached to a peer-to-peer bus that decides which devices must wait when multiple devices want to become a bus master. a. bus master unit b. bus arbitration unit c. bus controller Cengage Learning Testing, Powered by Cognero
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d. bus interface
41. The ____ connects only the CPU and memory. a. storage bus b. local bus c. system bus d. memory bus
42. A ____ connects secondary storage devices to the system bus. a. memory bus b. storage bus c. system bus d. local bus
43. ____ is a family of bus standards found in nearly all small and midrange computers and many larger ones. a. Peripheral Component Interface b. Peripheral Connection Interface c. Peripheral Component Interconnect d. Peripheral Component Interchange
44. Data, address, and command bits are transmitted across PCI bus line subsets called “____.� a. lanes b. ports c. stripes d. bundles
45. A(n) ____ is a communication pathway from the CPU to a peripheral device. a. connection port b. I/O port c. device port d. block port Cengage Learning Testing, Powered by Cognero
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46. In most computers, an I/O port is a ____. a. system address b. memory block c. network device d. memory address
47. One task performed by a storage device controller is translating logical write operations into ____ write operations. a. stack b. bugger c. cache d. physical
48. If the CPU is idle while a device completes an access request, the CPU cycles that could have been (but weren’t) devoted to instruction execution are called ____. a. I/O channels b. I/O hooks c. I/O wait states d. I/O peers
49. A ____ is a reserved area of main memory accessed on a last-in, first-out (LIFO) basis. a. stack b. queue c. chain d. heap
50. The main goal of buffering and caching is to ____. a. control data channels b. improve I/O performance Cengage Learning Testing, Powered by Cognero
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c. improve overall system performance d. reduce system load
51. If a buffer isn’t large enough to hold and entire unit of data transfer, an error called a ____ occurs. a. buffer overflow b. buffer underflow c. heap overflow d. buffer fault
52. As buffer size increases above ____ bytes, CPU cycle consumption decreases at a linear rate. a. 4 b. 8 c. 12 d. 16
53. The ____ states that when multiple resources are required to produce something useful, adding more of a single resource produces fewer benefits. a. law of regression b. law of diminishing returns c. law of diminished value d. law of diversity
54. Most performance benefits of a cache occur during ____. a. write operations b. mixed operations c. buffered operations d. read operations
55. A ____ is a processor that guesses what data will be requested in the near future and loads this data from the storage device into the cache before it’s actually requested. Cengage Learning Testing, Powered by Cognero
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a. cache miss b. cache controller c. cache hit d. cache algorithm
56. When the data needed isn’t in the cache, the access is called a ____. a. cache hit b. cache fault c. cache miss d. cache pull
57. The ratio of cache hits to read accesses is called the cache’s ____. a. hit ratio b. efficiency c. Performanc e d. hit boundary
58. When three cache levels are in use, the cache farthest from the CPU is called a ____ cache. a. level zero b. level one c. level two d. level three
59. When three cache levels are in use, the cache closest to the CPU is called a ____ cache. a. level zero b. level one c. level two d. level three
60. Many computer system designers rely on ____ to implement disk caching. Cengage Learning Testing, Powered by Cognero
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a. the OS b. specialized disk controller hardware c. applications d. firmware
61. The latest trend in high-performance CPU design embeds multiple CPUs and cache memory on a single chip—an approach called ____. a. multiple-processor architecture b. multicore architecture c. multipath architecture d. partial execution architecture
62. ____ is a cost-effective approach to computer system design when a single computer runs many different application programs or services. a. Partial execution architecture b. Multipath architecture c. Multicore architecture d. Multiple-processor architecture
63. The phrase ____ describes approaches to increasing processing and other computer system power by using larger and more powerful computers. a. scaling out b. scaling up c. scaling down d. scaling wide
64. ____ is an approach that partitions processing and other tasks among multiple computer systems. a. Scaling up b. Scaling down c. Scaling out d. Scaling in
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65. ____ is a technique that reduces the number of bits used to encode data, such as a file or a stream of video images transmitted across the Internet. a. Compression b. Dispersion c. Randomization d. Coordination
66. A ____ is a mathematical compression technique implemented as a program. a. compression system b. compression routine c. compression utility d. compression algorithm
67. With ____ compression, any data input that’s compressed and then decompressed is exactly the same as the original input. a. lossy b. lossless c. perfect d. ideal
68. With ____ compression, data inputs that are compressed and then decompressed are different from, but still similar to, the original input. a. lossy b. lossless c. universal d. ideal
69. The term ____ describes the ratio of data size in bits or bytes before and after compression. a. compression value b. compression efficiency c. compression ratio d. compression ratio
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70. Lossy compression of audio and video can achieve compression ratios up to ____. a. 25:1 b. 50:1 c. 75:1 d. 100:1
71. The ____________________ transmits data between computer system components.
72. The ____________________ distributes electrical power to directly attached devices or their device controllers.
73. Computer system components coordinate their activities by sending signals over the ____________________.
74. In the simplest sense, a(n) ____________________ is just a set of communication lines.
75. In traditional computer architecture, the ____________________ is the focus of all computer activity.
76. ____________________ buses connect a subset of computer components and are specialized for these components’ characteristics and communication between them.
77. The ____________________ bus improves computer system performance by removing video traffic from the system bus and providing a high-capacity one-way communication channel optimized for video data.
78. A(n) ____________________ bus, such as a Universal serial Bus, connects one or more external devices to the system bus.
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79. ____________________ ports enable the CPU and bus to interact with a keyboard in the same way they interact with a disk drive or video display.
80. Storage and I/O devices are normally connected to the system bus or a subsidiary bus through a(n) ____________________.
81. When the CPU detects an interrupt, it executes a master interrupt handler program called the ____________________.
82. A portion of the CPU, separate from the components that fetch and execute instructions, monitors the bus continuously for interrupt signals and copies them to a(n) ____________________.
83. A special-purpose register called the ____________________ always points to the next empty address in the stack and is incremented or decremented automatically each time the stack is pushed or popped.
84. Mismatches in data transfer rate and data transfer unit size are addressed in part by ____________________, which consumes substantial CPU resources.
85. A(n) ____________________ is a small reserved area of main memory (usually DRAM or SRAM) that holds data in transit from one device to another and is required to resolve differences in data transfer unit size.
86. As single bits are transferred over the wireless connection, they’re added to the buffer in ____________________ order.
87. A(n) ____________________ can improve system performance when two devices have different data transfer rates, as when copying music files from a PC to an iPod via a USB 2.0 connection.
88. Like a buffer, a(n) ____________________ is a reserved area of high-speed memory (usually RAM) that improves Cengage Learning Testing, Powered by Cognero
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system performance.
89. When a read operation accesses data already contained in the cache, the access is called a(n) ____________________.
90. A cache miss requires performing a(n) ____________________ to or from the storage device.
91. ____________________ is a more traditional approach to multiprocessing that uses two or more processors on a single motherboard or set of interconnected motherboards.
92. Most compression algorithms have a corresponding ____________________ algorithm that restores compressed data to its original or nearly original state.
93. ____________________ compression is required in many applications, such as accounting records, executable programs, and most stored documents.
94. ____________________ compression is usually applied only to audio and video data because the human brain tolerates missing audio and video data and can usually “fill in the blanks.�
95. ____________________ is incorporated into all modern videoconferencing standards to reduce use of available data transfer capacity.
96. Discuss two ways to increase the maximum bus data transfer rate.
97. Explain why overall system performance is reduced in traditional computer architecture, using a bus master.
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98. How can a cache controller be implemented?
99. Explain lossless compression and provide an example.
100. Explain lossy compression and provide an example.
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