EEWeb PULSE Why don’t you give us a little background about XMOS as a company?
time capability into all the different applications.
The technology for XMOS came out of Bristol University here in the U.K. Although it was founded in 2005, the company was really funded, and really started getting going in 2007. The first products came out towards the end of 2009, so really the customer base has been ramping since early 2010.
From an architectural standpoint, how does your multi-core microcontroller differ from a typical microcontroller? Is it different because you have programmable logic inside it as well?
The products that the company has developed are really quite revolutionary and breakthrough technology. One of them is a new type of microcontroller, what we would call multi-core, which makes it sound very conventional. But actually, within that, the way that we build our multi-core products allows us to build a product that is very flexible, and allows us to program in the different interfaces that people might need, specific to their design, and also provide a solution that is much more responsive for I/O signals, has very low latency, and is really ideal for complex, real-time systems. What we really end up doing is making complex embedded systems much easier to design. We see this technology going into a broad number of applications, from consumer – we’ve been very successful in audio – but also expanding into a broad swathe of industrial applications. We are also starting to get design wins in automotive as well. We can really see that the way we’re going to build out the XMOS business is by expanding into a broad set of applications, really leveraging the flexibility we have in our products, and allowing people to get the benefits of the performance, and the responsiveness, and the real-
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Well, yes. Not in the traditional FPGA sense, but we have some logic on the pins, so we can make some logic decisions based on inputs at the pins. But the key difference is in the architecture of our high-performance 32-bit RISC processor. One of the challenges when you build a high-speed processor is that you typically need to have a pipeline, to be able to run the processor at high speeds. What that then means is you need to serve that pipeline. You typically end up having a cache to be able to keep the instruction pipeline full, and to hide the memory latency for your design. What we have done is come up with a very different type of architecture. Rather than having the pipeline process the next instruction in your program sequence, what our pipeline does is time-slice between different processor cores or logical cores. So what you’re effectively able to do is to interleave on this high-performance processor. It’s low in terms of silicon area, low in terms of cost. We interleave these different logical cores together. Each instruction operates in one instruction cycle, so we don’t need a cache either.. What you end up with is a processor which is very fast-responding, and very deterministic. You can write your code, and from that you can know exactly how fast your code
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is going to execute. We add to that connections to the pins, so rather than there being interrupts, we bring the I/O pins through some logic that is available. You have these banks of logic that are available and you can connect through the pins to make logic decisions. For example, you can timestamp inputs coming in, precisely ‘clock’ data out, or you
“What we ha is come up w very differen architecture than having pipeline pro next instruct program seq what our pip is time-slice different pro cores or logi can look for a particular address occurring on a bus, and then stop to process the data. Or you can timestamp signals coming in, or take a high-speed serial stream and deserialize that, and going back the other way, serialize a parallel stream into a high-speed serial stream. So you can talk to the outside world in all the different ways that you need to, and process and control that