Ics151 sq06 midterm solee205

Student ID: ____________

ICS 151 Midterm Spring 2006 Name

: _________________ , _________________ (Last Name) (First Name)

Student ID

: _______________

Signature

: ________________

Instructions: 1. Please verify that your paper contains 14 pages including this cover and five blank pages.

2. Write down your Student-ID on the top of each page of this exam.

3. This exam is closed book. No notes or other materials are permitted.

4. Total credits of this midterm are 80 points.

5. To receive the full credits, you must show your work clearly.

6. Calculators are NOT allowed.

SOLUTIONS ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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Student ID: ____________

Q1: Register Design

[10 points]

Design a 4-bit register with 2 control inputs s1 and s0, 4 data inputs I3..I0, and 4 data outputs Q3..Q0. If s1s0 = 00, it means maintain the present value, s1s0 = 01 means load, and s1s0 = 10 means clear. s1s0 = 11 means to rotate left by 1, so 0101 would become 1010 and 1000 would become 0001.

[HINT: use D-Flip Flops and Mux] Q2 0 I3 Q3 s1 s0

4x1 Mux

Q1 0 I2 Q2 s1 s0

4x1 Mux

Q0 0 I1 Q1 s1 s0

4x1 Mux

Q3 0 I0 Q0 s1 s0

4x1 Mux

D

D

D

D

clk Q

clk Q

clk Q

clk Q

Q3

Q2

Q1

Q0

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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Student ID: ____________

Q2: FSM Design

[20 points]

Design a state diagram for a recognizer that recognizes an input sequence 11101. It has an input X and output Y. The recognizer sets the output to 1 (Y = 1) for exactly one clock cycle if the last five values on the input X were 11101. a. For the given input sequence, define the output sequence; (2 points) X 1 Y 0

0 0

0 0

1 0

1 0

1 0

0 0

0 0

1 0

1 0

1 0

0 0

1 1

1 0

1 0

0 0

1 1

0 0

1 0

1 0

1 0

b. Capture the FSM. (8 points)

X’

X’

X’

X

X’ A Y=0

B X

Y=0

C X

Y=0

D X

Y=0

E X’

Y=0

F X

X X’

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

Page 3

Y=1

Student ID: ____________ c. Create the architecture (3 points)

X

Y Combinational Logic Circuit

s2

s1

s0

n0

n1 n2

State Register

d. Encode the states (2 points).

A = 000 B = 001 C = 010 D = 011 E = 100 F = 101 e. Create the state table (5 points).

Present State s2 s1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0

s0 0 0 1 1 0 0 1 1 0 0 1 1

Input X 0 1 0 1 0 1 0 1 0 1 0 1

Next State n2 0 0 0 0 0 0 1 0 0 1 0 0

n1 0 0 0 1 0 1 0 1 0 0 0 0

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

n0 0 1 0 0 0 1 0 1 0 1 0 1

Output Y 0 0 0 0 0 0 0 0 0 0 1 1

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Student ID: ____________

Q3: Circuit Design

[10 points]

Design a circuit that is activated on a “START” signal and outputs a signal “PULSE” on a regular interval as described below.

The circuit cycles through 16 clock cycle periods (0 through 15 cycles) and asserts “PULSE” on clock cycles 1, 7, 8, 15. Design this circuit using the following components:

• • •

4-bit Counter Decoder Logic gates

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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Student ID: ____________

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

Page 6

Student ID: ____________

Q4: Combinational Component Design

[10 points]

Design a combinational component that implements the following function: F(x,y) = if (3x>4y) 2x+5y else 2x-y Use the following components: z Adder z Subtractor z Shifter z Comparator z Multiplexer

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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Student ID: ____________

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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Student ID: ____________

Q5: ALU Design

[20 points]

We are going to design a 4-bit Arithmetic Unit (AU) with the following functional table:

M1 0 0 1 1

M0 0 1 0 1

Function Name Add A and B Subtract 2 times B from A Increment A Add 4 times B and A

F(A,B) A+B A-2*B A+1 A + 4*B

A and B are two 4-bit binary numbers a3a2a1a0 and b3b2b1b0.

M1, M0 are the control inputs to this AU. For doing this, the blocks labeled AE (Arithmetic Extender) and CE (Carry Extender) in the following block diagram should be designed:

a. Fill the following table for y3, y2, y1, y0 and c0 based on the inputs of the AU which are a3,a2,a1,a0, b3,b2,b1,b0, M1 and M0: (10 points) M1 0 0 1 1

M0 0 1 0 1

y3

y2

y1

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

y0

c0

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Student ID: ____________

b. Using the table that you reached in part (a), derive the logic equations for

y1,

y0and c0. (10 points)

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

Page 10

Student ID: ____________

Q6: Counter Design

[10 points]

Design a 4-bit counter using two 2-bit counters. You may use logic gates as well.

E is enable input. When E=1, it counts at every clock cycle. When E=0, it stops counting and output stays unchanged. clr is clear input. When clr=1, it starts counting from 0 from the next clock cycle if E=1.

E clr

E

2-bit counter Q1 Q0

clk

2-bit counter

clr

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

Q1 Q0

clk

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Student ID: ____________

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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Student ID: ____________

ICS 151 Digital Logic Design, Spring Quarter 2006, Midterm

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