Ece 205 digitaldesign fall2013 final v3

0 0 0 000 0 0 1 Final Solutions 1 Digital Design 001 0ECE 205 Name: 0 1 0 1 1 1 0 1 1 1 011 0 Q1 (15) Q2 (15) Q3 (15) Q4 (15) Q5 (20) 1 1 0 100 1 1 1 1 101 1 1 1 1 110 1 Question 1 (15 points): 1 1 1 111 1

0 000 001 --1 17 January 2014 1 010 1 011 Q6 (20) Bonus (20) 1 100 1 101 1 110 1 111

0 0 0 0 0 0 0 1 Total (100) 0 0 0 0 0 0 1 1

0 0 0 0 0 0 1 1

a) (11010.0101)2 = ( ? )10 b) Obtain 1’s and 2’s complement of (10000000) (a) xy + xy'the=following x(y + y') = x expression to a minimum number of literals c) Simplify Boolean

(b) (x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x (c) xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y (d) (A + B)'(A' + B') = (A'B')(A B) = (A'B')(BA) = A'(B'BA) = 0 (e) xyz' + x'yz + xyz + x'yz' = xy(z + z') + x'y(z + z') = xy + x'y = y (f) (x + y + z')(x' + y' + z) = xx' + xy' + xz + x'y + yy' + yz + x'z' + y'z' + zz' = = xy' + xz + x'y + yz + x'z' + y'z' = x y + (x z)' + (y z)' (a) ABC + A'B + ABC' = AB + A'B = B

Digital Design – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2007, All rights re

Question 2 (15 points): Implement the following circuit using only 2 input NAND gates. You can only use A, B, C, D, E, F for input signals. (Do not use A, B, C , D, E , F for inputs) .

Question 3 (15 points): Implement a full adder circuit by using: a) 3–to-8 Decoder (10pts) b) Using only one 4x1 multiplexor, one inverter, and three 2x1Multiplexers. (10pts)

Question 4 (15 points): Draw the logic diagram of a four-bit register with four D flip-flops and four 4x1 multiplexers with mode selection inputs s1 and so. The register operates according to the following function table.

S1 S0 Register Operation 0

0

No Shift

0

1

1’s complement and right shift

1

0

Clear register to 0

1

1

Load parallel data

Question 5 (20 points): A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: JA=x

KA=B

JB=x’

KB=A’

a) Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables b) Fill out the state table c) Draw the state diagram of the circuit

Question 6 (20 points): Design a counter which counts down, with the repeated sequence: (2, 1, 0, 2, 1, 0, …) when the input to the counter circuit is 1. The counter doesn’t count (stays at the same state) when the input is 0. The circuit is to be designed by treating the unused states as don’t care conditions. Fill out state transition table, and draw state diagram and your schematic for the design. Use positive edge T flip flops in your design.

D: ____________

Bonus Question (20 points):

TL Design

[30 points]

Using Verilog, we want to design a 4-bit up/down counter as shown in the following block diagram, which can count either up down.

It requires an up/down input signal dir toasindicate thethe count direction, an input signal ld to load TL design method, we or want to design a 4-bit counter shown in the input data from I [3:0], and an input signal clr to reset the counter. g block diagram, which can count either up or down. It requires an input signalWe’ll let “dir=0” mean to count up and “dir=1” to count down.signal If “ldld= to 1”,load it loads from data inputfrom dataII[i3..i0], [3:0] regardless of the value of dir. When dicate the countmean direction, an input the input “clr = 1”, it clears the output Q [3:0] regardless of the value of dir or put signal clr to reset the counter. We’ll let “dir=0” mean to count up and ld. Write a Verilog module to implement t4-bit up/down counter, which is described above. mean to count down. If “ld = 1”, it loads from input data I [i3..i0] regardless of of dir. When “clr = 1”, it clears the output Q [q3..q0] regardless of the value of I [i3..i0] 4 dir ld

4-bit up/down counter

clr 4 Q [q3..q0]

ure a high-level state machine

Digital Logic Design, Spring Quarter 2006, Final

(10 points)

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