Ece205 digitaldesign fall2014 final 1sted v4

ECE 205 – Digital Design FINAL Examination 1st Education January 12, 2015 Name: Student number: Honor pledge: I have neither received nor given any help in this exam.

Signature: Q1 (15)

Q2 (15)

Q3 (15)

Q4 (15)

Q5 (15)

Q6 (20)

Q7 (15)

Total (100)

Question 1 (15 points): Complete the following table of equivalent values. a) Binary Octal Decimal 11.1875

b) Use 8 bits Decimal

Signed Magnitude

Two’s complement

Hexadecimal

One’s Complement 11110100

c) For the following addition use 2’s complement representation.

S=A + B, where A=(+6)10 and B=(+5)10 Perform the addition using only 4 bits for A, B and S variables. Note that these varables have sign. Explain the problem with the result and suggest a solution to avoid this problem.

Question 2. (15 points) Design a circuit that finds out if a 3-bit unsigned binary number is even. a) Use only 4:1 decoders with enable and some gates. b) Using an appropriate size decoder and ROM.

Question 3. (10 points) For the following circuit, which contains a full adder (FA), one XOR gate, two inverters and one 4-to-1 Mux with all inputs and outputs active high, find the minterms of the output function f(a, b, c, d). Note that B port is the MSB of the select signals for 4-to-1 Mux.

Question 4. (15 points) The following circuit contains a D latch, a positive-edge triggered D flip-flop, and a negative-edge triggered D flip-flop. Complete the given timing diagram by drawing the waveforms of signals y1, y2, and y3.

Question 5. (15 points) Draw the state diagram of a circuit which recognizes the sequence 1101 in the input signal x. The output signal, z, becomes 1 whenever it detects this particular sequence. Sequence may overlap.

For example, x z

t=0 0 0

t=1 1 0

t=2 0 0

t=3 1 0

t=4 1 0

t=5 0 0

t=6 1 1

t=7 1 0

t=8 0 0

a) Draw the state diagram using Mealy model b) Draw the state diagram using Moore model

t=9 1 1

t=10 1 0

t=11 0 0

t=12 1 1

t=13 1 0

t=14 1 0

t=15 1 0

t=16 0 0

t=17 1 1

Question 6. (20 points) Design a Finite State Machine (FSM) that will convert a 40 MHz clock to a 10 MHz clock.

Remember that in a divide-by-N counter, the output Y is HIGH for one clock cycle out of every N. In other words, the output divides the frequency of the clock by N. The waveform and state transition diagram for a divide-by-3 counter is shown in the following.

a) Derive the state diagram of FSM (that will convert a 40 MHz clock to a 10 MHz clock) using Moore model. b) Fill out the state table and find the minimized next state and output functions. c) Draw the circuit schematic using D flip-flops.

Question 7 (20 points) a) The following schematic shows a Linear Feedback Shift Register (LFSR) that generates 1 bit output, z, at every clock cycle using 8 bit shift registers. Write a Verilog code to implement this module. Although it is not shown in the figure, use an asynchronous, active low reset signal named Rst_n. If there is a reset signal, you should initialize the shift register to 8’b10101010. Use positive edge triggered FlipFlops. This module should have Clock and Rst_n signals as input and z as an output.