Csp susan li from istfa 2002 seminar

Failure Analysis Challenges for Chip Scale Packages ISTFA Seminar, Phoenix Nov. 9 & 10, 2002 Susan Xia Li Advance Micro Devices 1

Outline • • • • •

Chip Scale Package Overview Chip Scale Package Applications FA Challenges and Solutions Future Development Summary

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Chip Scale Package Overview CSP: A package about 1.2x the dimension (1.5x the area) of the die. Within this definition, CSP have many variations

SCSP or MCP: Stacked CSP or Multi-Chip Package is a package by stacking two or more dice on top of a BGA substrate with an insulating strip between them.

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Chip Scale Package Overview 3 Die Stacked CSP

“Stacked” BGA FBGA

Flip Chip CSP

uBGA Bare Die KGD 4

Chip Scale Package Overview

48 Ball Fortified-BGA

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Chip Scale Package Overview Mold Compound

Gold Bond Wire Die Attach

1.4 mm MAX 1.2 mm MAX

DIE

BT Resin Substrate

Solder Mask

Punch or Drill VIA 0.4mm (Fortified-BGA) 0.22mm (FBGA)

Solder Ball Pad

FBGA Package 6

Chip Scale Package Overview

Same Die Stacking

SRAM/Flash Stacking

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Chip Scale Package Overview Mold Compound

Gold Bond Wire

Adhesive

Die1 Die2

Die Attach

Solder Mask

Cu Trace

Two Die Stacking MCP 8

Chip Scale Package Applications • FBGA – High Board Level Reliability – Small Form Factor – Ideal for PDA, Cell Phones, most Portables and Hand-helds

• Fortified-BGA – Superior Board Level Reliability – Easy Routing – Ideal for Telecom, Network, Automotive Engine Controls and Automotive Navigation System 9

Chip Scale Package Applications • MCP – – – – – – –

Integration and PCB Optimization Baseband/bus in a Chip Reduce Power and Increase Performance Most Cost Effective Lighter Weight, Smaller Systems Increase Manufacturing Throughput Add more Features and Customer Flexibility

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Failure Analysis Challenges • Package Level Analysis • Die Level Analysis • MCP Analysis

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Failure Analysis Challenges • Package Level Analysis – Reliability Stressing Failures • • • • •

Package and/or Die cracks Cu Trace Cracks Through hole Via Crack Wire Bond Cracks Solder Ball Cracks

Similar Type Failures Seen on PBGA Packages, but with much Smaller Scales 12

Failure Analysis Challenges Cu Trace Crack

Flash Die

Cu Trace Crack

Cu Trace Crack 13

Failure Analysis Challenges Bad Via

Through Hole Via Crack 14

Failure Analysis Challenges

Wire Bond Crack

Wire Bond Crack 15

Failure Analysis Challenges

Solder Ball Crack 16

Failure Analysis Challenges • Die Level Analysis – New Challenges • High Temp and Precision Decapsulation • Very Thin Die • Special Test Socket • Backside Inaccessibility Device handling is the biggest challenge for CSP analysis due to its die size almost the same as the package 17

Failure Analysis Challenges • Decapsulation – High Temp Decapsulation • FBGA requires >200 C decapsulation temperature using fuming H2SO4 • Solder Melting at 183 C – Package needs to be air or liquid cooled after decap – No shaking of the package immediately after decapsulation

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Failure Analysis Challenges • Decapsulation (cont’d) – Precision Decapsulation • Precise etching window for decap gaskets – Rubber gaskets deterioration – Rubber gaskets expansion • Over-etch will cause: – Package damage on PCB substrate – Broken Cu trace in the package – Lifted bond wires from bond pads No electrical testing and diagnostic can be done if package is damaged during decapsulation 19

Failure Analysis Solutions

Good Decapsulation

Bad Decapsulation

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Failure Analysis Challenges • Device Handling – Very thin die • Silicon die in CSP is < 200um • Silicon die in MCP is <150um • Very easy to crack due to thermal/mechanical stress

– Special Test Sockets • Minimum stress applied to the package edges (after decap) • Apply even force to make good /solid contact for electrical test Inserting decapped device into socket for electrical testing is not a trivial task! Extra force will result in die crack and package damage 21

Failure Analysis Challenges • Backside Inaccessibility – Photon/Thermal Emission Analysis from Backside • Emission site covered by metal buses • Low level leakage at I/O pins or IccSSB Difficult to access the backside of device in FBGA due to solder ball arrays located at the backside of the PCB substrate

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Failure Analysis Challenges • MCP Analysis – Additional Challenges • Isolate failure to certain die by electrical testing and probing • Access to the failing die for fault isolation • Keep good electrical connectivity at the package level • Keep the bottom die intact for further analysis while removing top die or dice No room for errors during the decapsulation and testing.

Set up a good analysis strategy is the key for success 23

Failure Analysis Solutions • Failure Isolation to Certain Die – MCP combinations • SRAM/Flash • Flash/Flash • Two or more chips sharing same address and data pins

– Electrical testing and probing • Use CE (chip enable) pin for each die to distinguish failure to certain die (SRAM or Flash) through electrical testing • Shared power pins need to be separated for IccSSB failures No destructive analysis done until failing chip is isolated (except for IccSSB, which needs to separate power pins after decapsulation 24

Failure Analysis Solutions • Access to the Failing Die – Top Die Failing • Precision decapsulation to expose the top die • Perform analysis as normal single die device

– Bottom Die Failing • Precision decapsulation to expose the top die • Electrical testing or probing to confirm the failing die (bottom?)

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Failure Analysis Solutions • Access to the Failing Die (cont’d) – Bottom Die Failing • Remove the top die to expose the bottom die without damage – Chemical etching – Mechanical milling – Combine chemical and mechanical approach – Electrical connectivity needs to be preserved – No damage to the bottom die due to die crack or overetching • Perform analysis as normal single die device Top die removal while keeping the bottom die intact is the biggest challenge for MCP analysis 26

Failure Analysis Solutions

After Top Die Removal

Bottom Die Exposed w/o Damage 27

Future Development • Precision Decapsulation – Improved gaskets from current rubber gaskets – Less aggressive acid, such as a mixture of H2NO3 and H2SO4 – Special fixture design for repeatable precision decapsulation

• Special Test Socket – Flexible lid to apply minimum stress on decapped device

• Top Die Removal – Chemical approach (KOH, TMAH, etc. …)

– Mechanical approach • Polishing • Precision Milling Tools

– Chemical + Mechanical approach

• Backside Analysis 28

Summary • Introduction of Chip Scale Package definitions • Brief description of advantage of using CSP • Challenges encountered for CSP analysis: – Precision Decapsulation – Device Handling during testing and diagnostic work

• Additional Challenges for MCP analysis – Identify failing die or dice – Perform analysis on identified failing die with good package integrity for subsequent analysis

• Future development for the CSP analysis 29