SOLUTION MANUAL
SOLUTION MANUAL
Chapter 1 Computers and Digital Systems Chapter 2 Number Systems and Digital Codes Chapter 3 Logic Circuits and Boolean Algebra Chapter 4 Combinational Logic Circuit Design and Analysis Chapter 5 Introduction to Sequential Circuits Chapter 6 Synchronous Sequential Logic Circuit Analysis and Design Chapter 7 Asynchronous Sequential Circuit Analysis and Design Chapter 8 Programmable Digital Logic Devices Chapter 9 Design of Digital Systems
Digital Logic Circuit Analysis and Design Second Edition
Problem Solutions Manual
Victor P. Nelson Auburn University Bill D. Carroll University of Texas at Arlington H. Troy Nagle North Carolina State University J. David Irwin Auburn University
Contents Chapter 1 Number Systems and Digital Codes .......................................... 1 Chapter 2 Logic Circuits and Boolean Algebra ......................................... 27 Chapter 3 Combinational Logic Circuit Design and Analysis ................... 107 Chapter 4 Introduction to Sequential Circuits ....................................... 189 Chapter 5 Synchronous Sequential Circuit Analysis and Design ............. 215 Chapter 6 Asynchronous Sequential Circuit Analysis and Design ........... 265 Chapter 7 Programmable Digital Logic Devices ..................................... 303 Chapter 8 Design of Digital Systems ...................................................... 347
© 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
Digital Logic Circuit Analysis and Design, 2nd Edition
Chapter 1 – Number Systems and Digital Codes 1.1
Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of binary numbers. (a) 10101, 1011 1 1 1 + 1 0
× 1 0 0 1 0 1 1 1 1
1 0 1 0
1 1 0 0
1 0 1 1 0 0 1 0 0 0 1 0 0
1 0 1 1 1 0 0
1 0 1 0 0
0 10 0 10 1 0 1 0 1 ‒ 1 0 1 1 1 0 1 0
0 1 1 1 0 1 1
1 1 0 1 1 1 0 1 0 1 - 1 0 1 1 Remainder 1 0 1 0
1 0 1
(b) 1011010, 101111 1 1 1 + 1 0
1 0 1 0
1 1 0 0
1 1 1 1
1 0 1 0 1 1 1 0 0 1
1 0 1 1 0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 ×
0 10 0 1 0 1 ‒ 1 0 1 0
10 1 10 0 10 0 10 1 0 1 0 1 1 1 1 1 0 1 1
0 1 . 1 0 1 1 1 1 1 0 1 1 0 1 0 . 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 Remainder 0 1 1 1
1 1 0 0
0 1 1 0 1 1 1 1
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Digital Logic Circuit Analysis and Design, 2nd Edition
(c) 101, 1011
1
1 1 1 0 1 + 1 0 1 1 1 0 0 0 0
1 1 0 1 1 0 0 0 0 1 0 1 1 1 0 1
(1) Borrow
0 1 1 1 0 1 1
×
10 0 0 1 ‒ 1 0 1 0 0
0. 1 0 1 1 1 0 1. - 1 0 1 0 - 1 Remainder 0
1 1
(d) 10110110, 01011011 1 1 1 0 + 0 1 1 0 0
1 1 0 0
1 1 1 1
1 0 1 0
1 1 1 0 0 1 1 0 0 1
0 1 0 0 0 0 0 0 0
0
1
0
1 1 0 0 0 1 1 0 0 0 0
1
1
1 0 1 1 0 1 0 1
0
0 10 0 1 0 1 ‒ 0 1 0 0 1 0
1 0 1 0 0 1 0 0 1 0 0
× 0 0 1 0 0 0 0
10 0 1 1 1 0 0
1
1
0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0
1 0 1 1 1 0 0 1 0 0 1 0 0
1
1 0
1 0 1 1 0
1 0 1 1 1 1
1 0 0 1 1
10 10 0 10 0 0 10 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1
1 1 1 0
0
0 0 1 0 0 1
0 1 0
1
0
1
1
0
1 1
0 0
1 1
1 1
0 0
1 1
1 1
0
0
0
0
0
0
0
0
0
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Digital Logic Circuit Analysis and Design, 2nd Edition
(e) 1101011, 1010
1 1 1 0 1 + 1 1 1 1 0
× 1 0 0 1 1 0 1 0 0 0
1 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1 0 1 0 0 0 1 0
1 1 0
(f) 1010101, 101010 1 0 1 0 1 0 1 + 1 0 1 0 1 0 1 1 1 0 0 0 1 1 0 1 0 1 0 1 × 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 0 0 1 0
(g) 10000, 1001 1 0 1 1 1
+
× 0 0 0 1 0 0 1 0 0
1 0 1 1 0 0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0 1
0 0 0 0 0
1 1 1 0 0 0 1
0 0 0 1 0 0 0
0 0 0
1 1 0 1 0 1 1 ‒ 1 0 1 0 1 1 0 0 0 0 1
1 0 1 0 1 1 0 1 0 1 0 0 1 1 Remainder
0 10 0 10 1 0 1 0 ‒ 1 0 1 0 1 0 1
0 1 0 0
10 0 1 1
1 1 0 1 0 0
0 1 0 0 1 1 0 1 1 0 1 1 1
1 0 1
1 0 . 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 . 0 0 1 0 1 0 1 0 Remainder 0 1 0 0
1 1 1 0 10 10 10 10 1 0 0 0 0 ‒ 1 0 0 1 0 0 1 1 1
1 0 0 1 1 0 0 - 1 0 0 1 1 0
0 0 1 0 1 1
1 0 1 1 0 0 0
.1 1 .0 0 0 1 1 0
0 1
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Digital Logic Circuit Analysis and Design, 2nd Edition
Remainder
(h) 1011.0101, 110.11 1 1 1 1 0 1 + 1 1 1 0 0 1
× 0 1 0 1 0 1 1 0 1 1
1 0 1 1 1
1 0 1 0 0 1 0 0
0 1 0 0 1 0.
1 1. 0. 0
1 1. 1 1 1 1 0 0 0 1 0 0 1 0 1
1 1 0. 1 1 1 0 1 1. 0 1 1 0 1 1 0 0 1 1 1 0 Remainder 0 1 0
1.2
1 0 1 0 1 1 1 0 0 0 1
1. 1 1 0 1 0
0 1 0 1 0 1
0 0 0
0 10 1 0 1 ‒ 1 1 0 1 0
1 0. 1 0 0
0 1 1 1 0 1 1
0 1
1 1
1
0 10 1. 0 1 0 1 0. 1 1 0. 1 0 0 1
1 0 0 1 0 1 1 1
Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of octal numbers. (a) 372, 156 +
2 3 6
× 2 3 7 5
1 3 1 5
1 7 5 5
3 1 7 4 2 5
7 5 3 2
2 6 4
5
4
2 6 0
‒
1
5
6
3 3
3 1 2
7 3 3 3
Remainder
6 7 5 1
12 2 6 4
2. 2. 4 6 3 2 1
2 0
1 0
0 4 4 5 6
0 6 2
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Digital Logic Circuit Analysis and Design, 2nd Edition
(b) 704, 230 + 1
× 1 2
2 6 0
5 1 6
7 2 1
0 3 3
4 0 4
7 2 0 1 0 1
0 3 0 4
4 0 0
4
0
6 7 2 4
10 0 3 5
7 4 2 2
0 6 2 0 1 1
‒
2
3
0
Remainder
(c) 1000, 777
+
7 7
1 1
0 7 7
0 7 7
0 7 7
1 × 7 0 0 7
0 7 0 0 0 0
0 7 0 0
0 7 0
7
0
0
Remainder
7 0 7
7
0
7
1
0 7 0
× 3 3
2 1 4
5 6 4
4 6 2
2 5 7
3 1 4
4 6 4 3 2 2
2 5 2 7
3 1 3
1
3
‒ ‒
6
5
7 0
6 0
0 0 0 2 6
0 0 0
0 7 0
1. 0. 7 1 0
(d) 423, 651 + 1
2. 4. 0 4 5 7 5 1
7 7 10 10 10 0 0 0 7 7 7 0 0 1
0 1
‒
4 0 4
1
6 4 2
4 4
4 5 2 2
2 1 1 0
Remainder
0 0
0 0
1 0
0 7 0
0 7 0
0 7 1
11 1 3 6 0. 3. 1 1 6 2 2
5 0 5 3 5 5 3 1
1 0
3 0
0 1 7 7 7
0 3 5
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Digital Logic Circuit Analysis and Design, 2nd Edition
1.3
Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of hexadecimal numbers. (a) 2CF3, 2B +
1 5 7
2 × E 9 8
2
1 C
2
D
C E E C
F 2 7 6 D
F 1 0
1 F 0 F
(b) FFFF, 1000 + 1
F F
3 B E
3 B 1
2
1
D E
13 3 B 8
1 C B 1 1
0 F
B 3
F D 1
3 9 A
F 1 E
F 0 F
F 0 F
F 0 F
0
0
F F
F 0 F F
C
2
C
2 2 0
‒
0
B
Remainder
F 0 F
0 0 F F
F 1 0 0 0 F F
F 0 0 0 0
F 0 0 0
F 0 0
0
0
0
+ 1
9 D 6
A 1 B
5 7 C
× 4 9 6 3
9 D 3 A 1 E
A 1 8 5
5 7 3
D
3
1
‒ +
D
1
7
C D 9 3
11 1 A 7
9 8
A F A 9
Remainder
F. F. 0 F 0 F 0 F
F 0 F 0 F F
Remainder
(c) 9A5, D17
7 7
E F 2 C
2
‒
F 0 F
× 0 F F
F 2 1
F 0
F 0
0 0 0 0 0
0 0 0
7 5 2 0. 5. F 5 D 8 7
B 0 D 3 1 1 5 B
C 0
9 0
0 4 C C F
0 F 1
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Digital Logic Circuit Analysis and Design, 2nd Edition
(d) 372, 156 +
1 3 4
× 1 1 7 9
3 1 4 3 2 A
3 1 4
7 5 C
7 5 A A
2 6 C
4
C
2 6 8
‒
1
5
6
3 1 2
3 2
6 7 5 1
7 A C C
Remainder
12 2 6 C 2. 2. C 6 0 5 5
9 0
4 0
0 6 A 5 4
0 8 8
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Digital Logic Circuit Analysis and Design, 2nd Edition
1.4
Convert each of the following decimal numbers to binary, octal, and hexadecimal numbers. (a) 27 2 2 7 1 LSD 8 2 7 3 LSD 1 6 2 7 B LSD 2 1 3 1 8 3 3 MSD 1 6 3 1 MSD 2 6 0 0 0 (27)10 = (33)8 (27)10 = (1B)16 2 3 1 2 1 1 MSD 0 (27)10 = (11011)2 (b)
(c)
915 2 2 2 2
9 4 2 1 2 2 2
1 5 2 1 5 2 1 2 2 2
5 1 LSD 7 1 8 0 4 0 7 1 8 0 4 0 7 1 3 1 1 1 MSD 0 (915)10 = (1110010011)2
0.375 0.375 × 2 = 0.750 0.750 × 2 = 1.500 0.500 × 2 = 1.000
8 9 1 8 1 1 8 1 8
5 3 LSD 4 2 4 6 1 1 MSD 0 (915)10 = (1623)8
Or (915)10 = (1 110 010 011)2 = (1 6 2 3 )8
1 6 9 1 5 3 LSD 1 6 5 7 9 1 6 3 3 MSD 0 (27)10 = (393)16 Or (915)10 = (11 1001 0011)2 = (3 9 3 )16
0.375 × 8 = 3.000
0.375 × 16 = 6.000
(0.375)10 = (0.3)8
(0.375)10 = (0.6)16
.65 × 8 = 5.2 .2 × 8 = 1.6 .6 × 8 = 4.8 .8 × 8 = 6.4 .4 × 8 = 3.2 repeat
0.65 × 16 = 10.4 0.4 × 16 = 6.4 repeat
(0.375)10 = (0.011)2 (d)
0.65 .65 × 2 = 1.3 .3 × 2 = 0.6 .6 × 2 = 1.2 .2 × 2 = 0.4 .4 × 2 = 0.8 .8 × 2 = 1.6 repeat (0.65)10 = (0.101001)2
(0.375)10 = (0.A4)16
(0.65)10 = (0.51463)8
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Digital Logic Circuit Analysis and Design, 2nd Edition
(e)
174.25 Integer part: 2 1 7 4 0 LSD 2 8 7 1 2 4 3 1 2 2 1 1 2 1 0 0 2 5 1 2 2 0 2 1 1 0 (174)10 = (10101110)2 Fractional part: .25 × 2 = 0.5 .5 × 2 = 1.0 (0.25)10 = (0.01)2
8 1 7 8 2 8
4 6 LSD 1 5 2 2 MSD 0 (174)10 = (256)8
Or (174)10 = (10 101 110)2 = (2 5 6 )8
1 6 1 7 4 14 LSD 1 6 1 0 10 MSD 0 (174)10 = (AE)16 Or (174)10 = (1010 1110)2 =( A E )16
.25 × 8 = 2.0
0.25 × 16 = 4.0
(0.25)10 = (0.2)8
(0.25)10 = (0.4)16
Therefore, combining integer and fractional parts: (174.25)10 = (10101110.01)2 = (256.2)8 = (AE.4)16 (f)
250.8 Integer part: 2 2 5 0 0 LSD 1 1 2 5 1 2 6 2 0 2 3 1 1 2 1 5 1 2 7 1 2 3 1 2 1 1 0 (250)10 = (11111010)2
8 2 5 8 3 8
0 2 LSD 1 7 3 3 MSD 0 (250)10 = (372)8
Or (250)10 = (11 111 010)2 = (3 7 2 )8
Fractional part: .8 × 2 = 1.6 .6 × 2 = 1.2 .2 × 2 = 0.4 .4 × 2 = 0.8 repeats
.8 × 8 = 6.4 .4 × 8 = 3.2 .2 × 8 = 1.6 .6 × 8 = 4.8 repeats
(0.8)10 = (0.1100)2
(0.8)10 = (0.6314)8
1 6 2 5 0 10 LSD 1 6 1 5 15 MSD 0 (250)10 = (FA)16 Or (250)10 = (1111 1010)2 =( F A )16
0.8 × 16 = 12.8 repeats (0.8)10 = (0.C)16
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Digital Logic Circuit Analysis and Design, 2nd Edition
Therefore, combining integer and fractional parts: (250.8)10 = (11111010.1100)2 = (372.6314)8 = (FA.C)16 1.5
Convert each of the following binary numbers to octal, hexadecimal, and decimal numbers using the most appropriate conversion method. (a) 1101 001 101 1101 1 5 = (15)8 D = (D)16 23 + 22 + 20 = 8 + 4 + 1 = (13)10 (b) 101110 101 110 5 6 = (56)8
0010 1110 2 E = (2E)16
25 + 23 + 22 + 21 = 32 + 8 + 4 + 2 = (46)10 (c) 0.101 .101 .5 = (.5)8
.1010 .A = (.A)16
2-1 + 2-3 = .5 + .125 = (.625)10 (d) 0.01101 .011 010 .3 2 = (.32)8
.0110 1000 .6 8 = (.68)16
2-2 + 2-3+ 2-5 = .25 + .125 + .03125 = (.40625)10 (e) 10101.11 010 101.110 2 5 . 6 = (25.6)8
0001 0101 . 1100 1 5 . C = (15.C)16
24 + 22 + 20 + 2-1 + 2-2 = 16 + 4 + 1 + .5 + .25 = (21.75)10 (f) 10110110.001 010 110 110 . 001 2 6 6 . 1 = (266.1)8
1011 0110 . 0010 B 6 . 2 = (B6.2)16
27 + 25 + 24 + 22 + 21 + 2-3 = 128 + 32 + 16 + 4 + 1 + .125 = (181.125)10
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Digital Logic Circuit Analysis and Design, 2nd Edition
1.6
Convert each of the following octal numbers to binary, hexadecimal, and decimal using the most appropriate conversion method. (a) 65 (65)8 = (110 101)2 6 5 0011 0101 = (35)16 3 5 6 × 8 + 5 = 48 + 5 = (53)10 (b) 371 (371)8 = (011 111 001)2 3 7 1 1111 1001 = (F9)16 F 9 2 3 × 8 + 7 × 8 + 1 = 192 + 56 + 1 = (249)10 (c) 240.51 (240.51)8 = (010 100 000 . 101 001)2 2 4 0 5 1 1010 0000 . 1010 0100 = (A0.A4)16 A 0 A 4 2 -1 2 × 8 + 4 × 8 + 5 × 8 + 4 × 8-2 = 128 + 32 + .625 + .0156 = (160.6406)10 (d) 2000 (2000)8 = (010 000 000 000)2 2 0 0 0 0100 0000 0000 = (400)16 4 0 0 3 2 × 8 = 1024 = (1024)10 (e) 111111 (111111)8 = (001 001 001 001 001 001)2 1 1 1 1 1 1 1001 0010 0100 1001 = (9249)16 9 2 4 9 5 4 3 2 8 + 8 + 8 + 8 + 81 + 80 = 32,878 + 4,096 + 512 + 64 + 8 + 1 = (37,449)10 (f) 177777 (177777)8 = (001 111 111 111 111 111)2 1 7 7 7 7 7 1111 1111 1111 1111 = (FFFF)16 F F F F 5 4 3 2 8 + 7 × 8 + 7 × 8 + 7 × 8 + 7 × 8 + 7 = 32,768 + 28,672 + 3,584 + 448 + 56 + 7 = (65,535)10
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Digital Logic Circuit Analysis and Design, 2nd Edition
1.7
Convert each of the following hexadecimal numbers to binary, octal, and decimal using the most appropriate conversion method. (a) 4F (4F)16 = (0100 1111)2 4 F 001 001 111 = (117)8 1 1 7 4 × 16 + 15 = 64 + 15 = (79)10 (b) ABC (ABC)16 = (1010 1011 1100)2 A B C 101 010 111 100 = (5,274)8 5 2 7 4 10 × 162 + 11 × 16 + 12 = 2,560 + 176 + 12 = (2,748)10 (c) F8.A7 (F8.A7)16 = (1111 1000 . 1010 0111)2 F 8 A 7 011 111 000 . 101 001 110 = (370.516)8 3 7 0 5 1 6 15×16 + 8 + 10×16-1 + 7×16-2 = 240 + 8 + .625 + .027343750 = (240.6523438)10 (d) 2000 (2000)16 = (0010 0000 0000 0000)2 2 0 0 0 010 000 000 000 000 = (20,000)8 2 0 0 0 0 3 2×16 = (8,192)10 (e) 201.4 (201.4)16 = (0010 0000 0001 . 0100)2 2 0 1 4 001 000 000 001 . 010 = (1001.2)8 1 0 0 1 2 2 -1 2×16 + 1 + 4×16 = 512 + 1 + .25 = (513.25)10 (f) 3D65E (3D65E)16 = (0011 1101 0110 0101 1110)2 3 D 6 5 E 111 101 011 001 011 110 = (753,136)8 7 5 3 1 3 6 3×164 + 13×163+ 6×162+ 5×16 + 14 = 196,608+2,808+1,536+80+14 = (251,486)10
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Digital Logic Circuit Analysis and Design, 2nd Edition
1.8
Find the two's complement of each of the following binary numbers assuming n = 8 . (a) 101010
(b) 1101011
(c) 0
N = 00101010 11010101 - complement +1 - add 1 [N]2 = (11010110)2
N = 01101011 10010100 - complement +1 - add 1 [N]2 = (10010101)2 N = 00000000 11111111 - complement +1 - add 1 [N]2 = (00000000)2
(d) 11111111
N = 00000000 11111111 - complement +1 - add 1 [N]2 = (00000000)2
(e) 10000000
(f) 11000
N = 10000000 01111111 - complement +1 - add 1 [N]2 = (10000000)2 N = 00011000 11100111 - complement +1 - add 1 [N]2 = (11101000)2
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