SOLUTIONS MANUAL for Digital Logic Circuit Analysis & Design 2nd Edition by Nelson, Carroll & Irwin

SOLUTION MANUAL

SOLUTION MANUAL

Chapter 1 Computers and Digital Systems Chapter 2 Number Systems and Digital Codes Chapter 3 Logic Circuits and Boolean Algebra Chapter 4 Combinational Logic Circuit Design and Analysis Chapter 5 Introduction to Sequential Circuits Chapter 6 Synchronous Sequential Logic Circuit Analysis and Design Chapter 7 Asynchronous Sequential Circuit Analysis and Design Chapter 8 Programmable Digital Logic Devices Chapter 9 Design of Digital Systems

Digital Logic Circuit Analysis and Design Second Edition

Problem Solutions Manual

Victor P. Nelson Auburn University Bill D. Carroll University of Texas at Arlington H. Troy Nagle North Carolina State University J. David Irwin Auburn University

Contents Chapter 1 Number Systems and Digital Codes .......................................... 1 Chapter 2 Logic Circuits and Boolean Algebra ......................................... 27 Chapter 3 Combinational Logic Circuit Design and Analysis ................... 107 Chapter 4 Introduction to Sequential Circuits ....................................... 189 Chapter 5 Synchronous Sequential Circuit Analysis and Design ............. 215 Chapter 6 Asynchronous Sequential Circuit Analysis and Design ........... 265 Chapter 7 Programmable Digital Logic Devices ..................................... 303 Chapter 8 Design of Digital Systems ...................................................... 347

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No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 1 – Number Systems and Digital Codes 1.1

Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of binary numbers. (a) 10101, 1011 1 1 1 + 1 0

× 1 0 0 1 0 1 1 1 1

1 0 1 0

1 1 0 0

1 0 1 1 0 0 1 0 0 0 1 0 0

1 0 1 1 1 0 0

1 0 1 0 0

0 10 0 10 1 0 1 0 1 ‒ 1 0 1 1 1 0 1 0

0 1 1 1 0 1 1

1 1 0 1 1 1 0 1 0 1 - 1 0 1 1 Remainder 1 0 1 0

1 0 1

(b) 1011010, 101111 1 1 1 + 1 0

1 0 1 0

1 1 0 0

1 1 1 1

1 0 1 0 1 1 1 0 0 1

1 0 1 1 0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 ×

0 10 0 1 0 1 ‒ 1 0 1 0

10 1 10 0 10 0 10 1 0 1 0 1 1 1 1 1 0 1 1

0 1 .

1 0 1 1 1 1 1 0 1 1 0 1 0 .

1 0 1 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 Remainder 0 1 1 1

1 1 0 0

0 1 1 0 1 1 1 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) 101, 1011

1

1 1 1 0 1 + 1 0 1 1 1 0 0 0 0

1 1 0 1 1 0 0 0 0 1 0 1 1 1 0 1

(1) Borrow

0 1 1 1 0 1 1

×

10 0 0 1 ‒ 1 0 1 0 0

0.

1 0 1 1 1 0 1.

- 1 0 1 0 - 1 Remainder 0

1 1

(d) 10110110, 01011011 1 1 1 0 + 0 1 1 0 0

1 1 0 0

1 1 1 1

1 0 1 0

1 1 1 0 0 1 1 0 0 1

0 1 0 0 0 0 0 0 0

0

1

0

1 1 0 0 0 1 1 0 0 0 0

1

1

1 0 1 1 0 1 0 1

0

0 10 0 1 0 1 ‒ 0 1 0 0 1 0

1 0 1 0 0 1 0 0 1 0 0

× 0 0 1 0 0 0 0

10 0 1 1 1 0 0

1

1

0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0

1 0 1 1 1 0 0 1 0 0 1 0 0

1

1 0

1 0 1 1 0

1 0 1 1 1 1

1 0 0 1 1

10 10 0 10 0 0 10 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1

1 1 1 0

0

0 0 1 0 0 1

0 1 0

1

0

1

1

0

1 1

0 0

1 1

1 1

0 0

1 1

1 1

0

0

0

0

0

0

0

0

0

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Digital Logic Circuit Analysis and Design, 2nd Edition

(e) 1101011, 1010

1 1 1 0 1 + 1 1 1 1 0

× 1 0 0 1 1 0 1 0 0 0

1 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 0 1

1 0 1 1 0 1 0 1 0 1 0 0 0 1 0

1 1 0

(f) 1010101, 101010 1 0 1 0 1 0 1 + 1 0 1 0 1 0 1 1 1 0 0 0 1 1 0 1 0 1 0 1 × 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 0 0 1 0

(g) 10000, 1001 1 0 1 1 1

+

× 0 0 0 1 0 0 1 0 0

1 0 1 1 0 0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0 1

0 0 0 0 0

1 1 1 0 0 0 1

0 0 0 1 0 0 0

0 0 0

1 1 0 1 0 1 1 ‒ 1 0 1 0 1 1 0 0 0 0 1

1 0 1 0 1 1 0 1 0 1 0 0 1 1 Remainder

0 10 0 10 1 0 1 0 ‒ 1 0 1 0 1 0 1

0 1 0 0

10 0 1 1

1 1 0 1 0 0

0 1 0 0 1 1 0 1 1 0 1 1 1

1 0 1

1 0 . 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 . 0 0 1 0 1 0 1 0 Remainder 0 1 0 0

1 1 1 0 10 10 10 10 1 0 0 0 0 ‒ 1 0 0 1 0 0 1 1 1

1 0 0 1 1 0 0 - 1 0 0 1 1 0

0 0 1 0 1 1

1 0 1 1 0 0 0

.1 1 .0 0 0 1 1 0

0 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

Remainder

(h) 1011.0101, 110.11 1 1 1 1 0 1 + 1 1 1 0 0 1

× 0 1 0 1 0 1 1 0 1 1

1 0 1 1 1

1 0 1 0 0 1 0 0

0 1 0 0 1 0.

1 1.

0.

0

1 1.

1 1 1 1 0 0 0 1 0 0 1 0 1

1 1 0. 1 1 1 0 1 1. 0 1 1 0 1 1 0 0 1 1 1 0 Remainder 0 1 0

1.2

1 0 1 0 1 1 1 0 0 0 1

1.

1 1 0 1 0

0 1 0 1 0 1

0 0 0

0 10 1 0 1 ‒ 1 1 0 1 0

1 0.

1 0 0

0 1 1 1 0 1 1

0 1

1 1

1

0 10 1. 0 1 0 1 0. 1 1 0. 1 0 0 1

1 0 0 1 0 1 1 1

Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of octal numbers. (a) 372, 156 +

2 3 6

× 2 3 7 5

1 3 1 5

1 7 5 5

3 1 7 4 2 5

7 5 3 2

2 6 4

5

4

2 6 0

‒

1

5

6

3 3

3 1 2

7 3 3 3

Remainder

6 7 5 1

12 2 6 4

2.

2.

4 6 3 2 1

2 0

1 0

0 4 4 5 6

0 6 2

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 704, 230 + 1

× 1 2

2 6 0

5 1 6

7 2 1

0 3 3

4 0 4

7 2 0 1 0 1

0 3 0 4

4 0 0

4

0

6 7 2 4

10 0 3 5

7 4 2 2

0 6 2 0 1 1

‒

2

3

0

Remainder

(c) 1000, 777

+

7 7

1 1

0 7 7

0 7 7

0 7 7

1 × 7 0 0 7

0 7 0 0 0 0

0 7 0 0

0 7 0

7

0

0

Remainder

7 0 7

7

0

7

1

0 7 0

× 3 3

2 1 4

5 6 4

4 6 2

2 5 7

3 1 4

4 6 4 3 2 2

2 5 2 7

3 1 3

1

3

‒ ‒

6

5

7 0

6 0

0 0 0 2 6

0 0 0

0 7 0

1.

0.

7 1 0

(d) 423, 651 + 1

2.

4.

0 4 5 7 5 1

7 7 10 10 10 0 0 0 7 7 7 0 0 1

0 1

‒

4 0 4

1

6 4 2

4 4

4 5 2 2

2 1 1 0

Remainder

0 0

0 0

1 0

0 7 0

0 7 0

0 7 1

11 1 3 6 0.

3.

1 1 6 2 2

5 0 5 3 5 5 3 1

1 0

3 0

0 1 7 7 7

0 3 5

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.3

Calculate A + B , A − B , A× B , and A ÷ B for the following pairs of hexadecimal numbers. (a) 2CF3, 2B +

1 5 7

2 × E 9 8

2

1 C

2

D

C E E C

F 2 7 6 D

F 1 0

1 F 0 F

(b) FFFF, 1000 + 1

F F

3 B E

3 B 1

2

1

D E

13 3 B 8

1 C B 1 1

0 F

B 3

F D 1

3 9 A

F 1 E

F 0 F

F 0 F

F 0 F

0

0

F F

F 0 F F

C

2

C

2 2 0

‒

0

B

Remainder

F 0 F

0 0 F F

F 1 0 0 0 F F

F 0 0 0 0

F 0 0 0

F 0 0

0

0

0

+ 1

9 D 6

A 1 B

5 7 C

× 4 9 6 3

9 D 3 A 1 E

A 1 8 5

5 7 3

D

3

1

‒ +

D

1

7

C D 9 3

11 1 A 7

9 8

A F A 9

Remainder

F. F. 0 F 0 F 0 F

F 0 F 0 F F

Remainder

(c) 9A5, D17

7 7

E F 2 C

2

‒

F 0 F

× 0 F F

F 2 1

F 0

F 0

0 0 0 0 0

0 0 0

7 5 2 0.

5.

F 5 D 8 7

B 0 D 3 1 1 5 B

C 0

9 0

0 4 C C F

0 F 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) 372, 156 +

1 3 4

× 1 1 7 9

3 1 4 3 2 A

3 1 4

7 5 C

7 5 A A

2 6 C

4

C

2 6 8

‒

1

5

6

3 1 2

3 2

6 7 5 1

7 A C C

Remainder

12 2 6 C 2.

2.

C 6 0 5 5

9 0

4 0

0 6 A 5 4

0 8 8

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.4

Convert each of the following decimal numbers to binary, octal, and hexadecimal numbers. (a) 27 2 2 7 1 LSD 8 2 7 3 LSD 1 6 2 7 B LSD 2 1 3 1 8 3 3 MSD 1 6 3 1 MSD 2 6 0 0 0 (27)10 = (33)8 (27)10 = (1B)16 2 3 1 2 1 1 MSD 0 (27)10 = (11011)2 (b)

(c)

915 2 2 2 2

9 4 2 1 2 2 2

1 5 2 1 5 2 1 2 2 2

5 1 LSD 7 1 8 0 4 0 7 1 8 0 4 0 7 1 3 1 1 1 MSD 0 (915)10 = (1110010011)2

0.375 0.375 × 2 = 0.750 0.750 × 2 = 1.500 0.500 × 2 = 1.000

8 9 1 8 1 1 8 1 8

5 3 LSD 4 2 4 6 1 1 MSD 0 (915)10 = (1623)8

Or (915)10 = (1 110 010 011)2 = (1 6 2 3 )8

1 6 9 1 5 3 LSD 1 6 5 7 9 1 6 3 3 MSD 0 (27)10 = (393)16 Or (915)10 = (11 1001 0011)2 = (3 9 3 )16

0.375 × 8 = 3.000

0.375 × 16 = 6.000

(0.375)10 = (0.3)8

(0.375)10 = (0.6)16

.65 × 8 = 5.2 .2 × 8 = 1.6 .6 × 8 = 4.8 .8 × 8 = 6.4 .4 × 8 = 3.2 repeat

0.65 × 16 = 10.4 0.4 × 16 = 6.4 repeat

(0.375)10 = (0.011)2 (d)

0.65 .65 × 2 = 1.3 .3 × 2 = 0.6 .6 × 2 = 1.2 .2 × 2 = 0.4 .4 × 2 = 0.8 .8 × 2 = 1.6 repeat (0.65)10 = (0.101001)2

(0.375)10 = (0.A4)16

(0.65)10 = (0.51463)8

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Digital Logic Circuit Analysis and Design, 2nd Edition

(e)

174.25 Integer part: 2 1 7 4 0 LSD 2 8 7 1 2 4 3 1 2 2 1 1 2 1 0 0 2 5 1 2 2 0 2 1 1 0 (174)10 = (10101110)2 Fractional part: .25 × 2 = 0.5 .5 × 2 = 1.0 (0.25)10 = (0.01)2

8 1 7 8 2 8

4 6 LSD 1 5 2 2 MSD 0 (174)10 = (256)8

Or (174)10 = (10 101 110)2 = (2 5 6 )8

1 6 1 7 4 14 LSD 1 6 1 0 10 MSD 0 (174)10 = (AE)16 Or (174)10 = (1010 1110)2 =( A E )16

.25 × 8 = 2.0

0.25 × 16 = 4.0

(0.25)10 = (0.2)8

(0.25)10 = (0.4)16

Therefore, combining integer and fractional parts: (174.25)10 = (10101110.01)2 = (256.2)8 = (AE.4)16 (f)

250.8 Integer part: 2 2 5 0 0 LSD 1 1 2 5 1 2 6 2 0 2 3 1 1 2 1 5 1 2 7 1 2 3 1 2 1 1 0 (250)10 = (11111010)2

8 2 5 8 3 8

0 2 LSD 1 7 3 3 MSD 0 (250)10 = (372)8

Or (250)10 = (11 111 010)2 = (3 7 2 )8

Fractional part: .8 × 2 = 1.6 .6 × 2 = 1.2 .2 × 2 = 0.4 .4 × 2 = 0.8 repeats

.8 × 8 = 6.4 .4 × 8 = 3.2 .2 × 8 = 1.6 .6 × 8 = 4.8 repeats

(0.8)10 = (0.1100)2

(0.8)10 = (0.6314)8

1 6 2 5 0 10 LSD 1 6 1 5 15 MSD 0 (250)10 = (FA)16 Or (250)10 = (1111 1010)2 =( F A )16

0.8 × 16 = 12.8 repeats (0.8)10 = (0.C)16

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Digital Logic Circuit Analysis and Design, 2nd Edition

Therefore, combining integer and fractional parts: (250.8)10 = (11111010.1100)2 = (372.6314)8 = (FA.C)16 1.5

Convert each of the following binary numbers to octal, hexadecimal, and decimal numbers using the most appropriate conversion method. (a) 1101 001 101 1101 1 5 = (15)8 D = (D)16 23 + 22 + 20 = 8 + 4 + 1 = (13)10 (b) 101110 101 110 5 6 = (56)8

0010 1110 2 E = (2E)16

25 + 23 + 22 + 21 = 32 + 8 + 4 + 2 = (46)10 (c) 0.101 .101 .5 = (.5)8

.1010 .A = (.A)16

2-1 + 2-3 = .5 + .125 = (.625)10 (d) 0.01101 .011 010 .3 2 = (.32)8

.0110 1000 .6 8 = (.68)16

2-2 + 2-3+ 2-5 = .25 + .125 + .03125 = (.40625)10 (e) 10101.11 010 101.110 2 5 . 6 = (25.6)8

0001 0101 . 1100 1 5 . C = (15.C)16

24 + 22 + 20 + 2-1 + 2-2 = 16 + 4 + 1 + .5 + .25 = (21.75)10 (f) 10110110.001 010 110 110 . 001 2 6 6 . 1 = (266.1)8

1011 0110 . 0010 B 6 . 2 = (B6.2)16

27 + 25 + 24 + 22 + 21 + 2-3 = 128 + 32 + 16 + 4 + 1 + .125 = (181.125)10

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.6

Convert each of the following octal numbers to binary, hexadecimal, and decimal using the most appropriate conversion method. (a) 65 (65)8 = (110 101)2 6 5 0011 0101 = (35)16 3 5 6 × 8 + 5 = 48 + 5 = (53)10 (b) 371 (371)8 = (011 111 001)2 3 7 1 1111 1001 = (F9)16 F 9 2 3 × 8 + 7 × 8 + 1 = 192 + 56 + 1 = (249)10 (c) 240.51 (240.51)8 = (010 100 000 . 101 001)2 2 4 0 5 1 1010 0000 . 1010 0100 = (A0.A4)16 A 0 A 4 2 -1 2 × 8 + 4 × 8 + 5 × 8 + 4 × 8-2 = 128 + 32 + .625 + .0156 = (160.6406)10 (d) 2000 (2000)8 = (010 000 000 000)2 2 0 0 0 0100 0000 0000 = (400)16 4 0 0 3 2 × 8 = 1024 = (1024)10 (e) 111111 (111111)8 = (001 001 001 001 001 001)2 1 1 1 1 1 1 1001 0010 0100 1001 = (9249)16 9 2 4 9 5 4 3 2 8 + 8 + 8 + 8 + 81 + 80 = 32,878 + 4,096 + 512 + 64 + 8 + 1 = (37,449)10 (f) 177777 (177777)8 = (001 111 111 111 111 111)2 1 7 7 7 7 7 1111 1111 1111 1111 = (FFFF)16 F F F F 5 4 3 2 8 + 7 × 8 + 7 × 8 + 7 × 8 + 7 × 8 + 7 = 32,768 + 28,672 + 3,584 + 448 + 56 + 7 = (65,535)10

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.7

Convert each of the following hexadecimal numbers to binary, octal, and decimal using the most appropriate conversion method. (a) 4F (4F)16 = (0100 1111)2 4 F 001 001 111 = (117)8 1 1 7 4 × 16 + 15 = 64 + 15 = (79)10 (b) ABC (ABC)16 = (1010 1011 1100)2 A B C 101 010 111 100 = (5,274)8 5 2 7 4 10 × 162 + 11 × 16 + 12 = 2,560 + 176 + 12 = (2,748)10 (c) F8.A7 (F8.A7)16 = (1111 1000 . 1010 0111)2 F 8 A 7 011 111 000 . 101 001 110 = (370.516)8 3 7 0 5 1 6 15×16 + 8 + 10×16-1 + 7×16-2 = 240 + 8 + .625 + .027343750 = (240.6523438)10 (d) 2000 (2000)16 = (0010 0000 0000 0000)2 2 0 0 0 010 000 000 000 000 = (20,000)8 2 0 0 0 0 3 2×16 = (8,192)10 (e) 201.4 (201.4)16 = (0010 0000 0001 . 0100)2 2 0 1 4 001 000 000 001 . 010 = (1001.2)8 1 0 0 1 2 2 -1 2×16 + 1 + 4×16 = 512 + 1 + .25 = (513.25)10 (f) 3D65E (3D65E)16 = (0011 1101 0110 0101 1110)2 3 D 6 5 E 111 101 011 001 011 110 = (753,136)8 7 5 3 1 3 6 3×164 + 13×163+ 6×162+ 5×16 + 14 = 196,608+2,808+1,536+80+14 = (251,486)10

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.8

Find the two's complement of each of the following binary numbers assuming n = 8 . (a) 101010

(b) 1101011

(c) 0

N = 00101010 11010101 - complement +1 - add 1 [N]2 = (11010110)2

N = 01101011 10010100 - complement +1 - add 1 [N]2 = (10010101)2 N = 00000000 11111111 - complement +1 - add 1 [N]2 = (00000000)2

(d) 11111111

N = 00000000 11111111 - complement +1 - add 1 [N]2 = (00000000)2

(e) 10000000

(f) 11000

N = 10000000 01111111 - complement +1 - add 1 [N]2 = (10000000)2 N = 00011000 11100111 - complement +1 - add 1 [N]2 = (11101000)2

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.9

Find the one's complement of each of the following binary numbers assuming n = 8 . (a) 110101 00110101 (b)

(c)

11001010 - l's complement 1010011

0

01010011 10101100 - l's complement 00000000

(d)

(e)

(f)

11111111 - l's complement 10000000 10000000 01111111 - l 's complement 100001 00100001 11011110 - l's complement 01111111 01111111 10000000 - l's complement

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.10 Calculate A + B , A − B , − A + B , and − A − B for each of the following pairs of numbers assuming a two's complement number system and n = 8 . Check your results by decimal arithmetic. Explain any unusual results. (a) 1010101, 1010 A = (0, 1010101)2cns +(85)10 ‒A = (0, 1010101)2cns ‒(85)10 A +B

+

0 0 0

1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1

Result: (0, 1011111)2cns = +(95)10 -A + B

1 0 1 0 1 0 1 1 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 Result: (1, 0110101)2cns = ‒ (75)10 +

B = (0, 001010)2cns ‒B = (1, 110110)2cns

+(10)10 ‒(10)10

A-B

0 1 0 1 0 1 0 1 + 1 1 1 1 0 1 1 0 (1) 0 1 0 0 1 0 1 1 (Discard carry ) Result: (0, 1001011)2cns = +(75)10

-A-B

1 0 1 0 1 0 1 1 + 1 1 1 1 0 1 1 0 (1) 1 0 1 0 0 0 0 1 (Discard carry ) Result: (1, 0100001)2cns = ‒ (95)10

(b) 1101011, 0101010

A = (0, 1101011)2cns +(107)10 ‒A = (1, 0010101)2cns ‒(107)10 A+B

+

0 1 1 0 0 1 1 0 0

0 1 0 1 1 0 1 0 1 0 1 0 1 0 1

Overflow condition! Invalid result -A + B

1 0 0 1 0 1 0 1 + 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 Result: (1, 0110101)2cns = ‒ (65)10

B = (0, 0101010)2cns +(42)10 ‒B = (1, 1010110)2cns ‒(42)10 A-B

0 1 1 0 1 0 1 1 + 1 1 0 1 0 1 1 0 (1) 0 1 0 0 0 0 0 1 (Discard carry ) Result: (0, 1001011)2cns = +(65)10

-A - B

1 0 0 1 0 1 0 1 + 1 1 0 1 0 1 1 0 (1) 0 1 1 0 1 0 1 1 Overflow condition! Invalid result

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) 11101010, 101111

A = (1, 1101010)2cns ‒(22)10 ‒A = (0, 0010110)2cns +(22)10 A+B

+ (1)

1 1 1 0 0 1 0 0 0

0 1 0 1 0 0 1 1 1 1 1 1 0 0 1

(Discard carry) Result: (0,0011001)2cns = +(25)10 -A + B

0 0 0 1 0 1 1 0 + 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 Result: (0, 1000101)2cns = +(69)10

B = (0, 0101111)2cns +(47)10 ‒B = (1, 1010001)2cns ‒(47)10 A-B

1 1 1 0 1 0 1 0 + 1 1 0 1 0 0 0 1 (1) 1 0 1 1 1 0 1 1 (Discard carry ) Result: (1, 0111011)2cns = ‒(69)10

-A - B

0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 1 Result: (1, 0111011)2cns = ‒(25)10 +

(d) 10000000, 01111111

A = (1, 0000000)2cns ‒(22)10 ‒A : can’t do +(128)10 with 8 bits A+B

+

1 0 0 0 1 1 1 1 1

0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

(Discard carry) Result: (1,1111111)2cns = ‒(128)10

B = (0, 1111111)2cns +(127)10 ‒B = (1, 0000001)2cns ‒(127)10 A-B

1 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 1 (1) 0 0 0 0 0 0 0 1 Overflow condition! Invalid result

Cannot do ( ‒A + B ) or ( ‒A ‒ B) since ‒A cannot be represented!

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.11 Repeat Problem 1.10 for the following numbers using a one's complement number system. (a) 101011, 1101 A = (0, 0101011)1cns +(43)10 ‒A = (1, 1010100)1cns ‒(43)10 A +B

+

0 0 0

0 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 0

B = (0, 0001101)1cns +(13)10 ‒B = (1, 1110010)1cns ‒(13)10 A-B

Result: (0, 0111000)1cns = +(56)10 -A + B

1 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 Result: (1, 0110101)1cns = ‒(30)10 +

-A-B

0 0 1 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 1 0 1 + 1 0 0 0 1 1 1 1 0 (Carry added in) Result: (0, 1001100)1cns = +(30)10 + (1)

1 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 + 1 1 1 0 0 1 0 0 0 (Discard carry ) Result: (1, 0100001)1cns = ‒(56)10 + (1)

(b) 10111010, 11010 A = (1, 0111010)1cns ‒(69)10 ‒A = (0, 1000101)1cns +(69)10 A +B

+

1 0 1

0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0

B = (0, 0011010)1cns +(26)10 ‒B = (1, 1100101)1cns ‒(26)10 A-B

Result: (0, 0111000)1cns = ‒(43)10 -A + B

0 1 0 0 0 1 0 1 + 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 1 Result: (1, 0110101)1cns = +(95)10

-A-B

1 0 1 1 1 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 1 + 1 1 0 1 0 0 0 0 0 (Carry added in) Result: (0, 1001100)1cns = ‒(95)10 + (1)

0 1 0 0 0 1 0 1 + 1 1 1 0 0 1 0 1 (1) 0 0 1 0 1 0 1 0 + 1 0 0 1 0 1 0 1 1 (Discard carry ) Result: (1, 0100001)1cns = +(43)10

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) 1010101, 0101010 A = (0, 1010101)1cns +(85)10 ‒A = (1, 0101010)1cns ‒(85)10 A +B

+

0 0 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1

B = (0, 0101010)1cns +(42)10 ‒B = (1, 1010101)1cns ‒(42)10 A-B

Result: (0, 1111111)1cns = +(127)10 -A + B

1 0 1 0 1 0 1 0 + 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 Result: (1, 1010100)1cns = ‒(43)10

-A-B

0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 + 1 0 0 1 0 1 0 1 1 (Carry added in) Result: (0, 0101011)1cns = +(43)10 + (1)

1 0 1 0 1 0 1 0 + 1 1 0 1 0 1 0 1 (1) 0 1 1 1 1 1 1 1 + 1 1 0 0 0 0 0 0 0 (Carry added in ) Result: (1, 0000000)1cns = ‒(127)10

(d) 10000000, 01111111 A = (1, 0000000)1cns ‒ (127)10 ‒A = (0, 1111111)1cns +(127)10 A +B

+

1 0 1

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

B = (0, 1111111)1cns +(127)10 ‒B = (1, 0000000)1cns ‒(127)10 A-B

1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0 1 (Carry added in) Overflow condition! Invalid result

-A-B

0 1 1 1 1 1 1 1 + 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Result: (1, 1111111)1cns = ‒(0)10

Result: (1, 1111111)1cns = ‒(0)10 -A + B

0 1 1 1 1 1 1 1 + 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Overflow condition! Invalid result

+ (1)

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.12 Show how a 16-bit computer using a two's complement number system would perform the following computations. (a) (16850)10 + (2925)10 = (?)10 (b) (16850)10 ‒ (2925)10 = (?)10 (c) (2925)10 ‒ (16850)10 = (?)10 (c) ‒(2925)10 ‒ (16850)10 = (?)10 (16, 850)10 = (0, 100000111010010)2cns ‒(16, 850)10 = (1, 011111000101110)2cns (2, 925)10 = (0, 000101101101101)2cns ‒(2, 925)10 = (1, 111010010010011)2cns (a) (16, 850)10 + (2, 925)10 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 + 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 1 1 1 1 1 1 Result: (0, 100110100111111)2cns = (19, 775)10 (b) (16, 850)10 ‒ (2, 925)10 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 1 (1) 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 Result: (0, 011011001100101)2cns = (13, 925)10 +

(c) (2, 925)10 ‒ (16, 850)10 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 + 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 Result: (1, 100100110011011)2cns = -(13, 925)10 (d) ‒(2, 925)10 ‒ (16, 850)10 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 1 + 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 0 (1) 1 0 1 1 0 0 1 0 1 1 0 0 0 0 0 1 Result: (1, 011001011000001)2cns = -(19, 775)10

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.13 Show how each of the following numbers would be represented as floating-point numbers in IEEE 754-2008 Binary-32 and Binary-64 formats. (a) 1101

Binary-32 Format (sign bit, 8 exponent bits, 23 mantissa bits): (1101)2 = (1.101)2 × 23 M = +(1.101)2sm SM = 0 (leading 1 of M to be suppressed) E = +(3)10 bias + 3 = 127+3 = 130 = (10000010)excess-127 1011 = (0 10000010 10100000000000000000000)fp Binary-64 Format (sign bit, 11 exponent bits, 53 mantissa bits): Bias+3 = 1023+3 = 1026 = (10000000010)excess-1023 1101 = (0 10000000010 10100000000000000000000000000000000000000000000000000)fp

(b) 101110

Binary-32 (101110)2 = (1.01110)2 × 25 M = +(1.01110)2sm SM = 0 (leading 1 of M to be suppressed) E = +(5)10 bias + 5 = 127+5 = 132 = (10000100)excess-127 1011 = (0 10000100 01110000000000000000000)fp Binary-64 Bias+3 = 1023+5 = 1028 = (10000000100)excess-1023 1101 = (0 10000000100 01110000000000000000000000000000000000000000000000000)fp

(c) 0.101

Binary-32 (0.101)2 = (1.01)2 × 2-1 M = +(1.01)2sm SM = 0 (leading 1 of M to be suppressed) E = ‒(1)10 bias ‒ 1 = 127 ‒ 1 = 126 = (01111110)excess-127 0.101 = (0 01111110 01000000000000000000000)fp Binary-64 Bias ‒ 1 = 1023 ‒ 1 = 1021 = (01111111110)excess-1023 0.101 = (0 01111111110 01000000000000000000000000000000000000000000000000000)fp

(d) 0.01101

Binary-32 (0. 01101)2 = (1.101)2 × 2-2 M = +(1.101)2sm SM = 0 (leading 1 of M to be suppressed) E = ‒(2)10 bias ‒ 2 = 127 ‒ 2 = 125 = (01111101)excess-127 0. 01101 = (0 01111101 10100000000000000000000)fp Binary-64 Bias ‒ 2 = 1023 ‒ 2 = 1021 = (01111111101)excess-1023 0. 01101 = (0 01111111101 10100000000000000000000000000000000000000000000000000)fp

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Digital Logic Circuit Analysis and Design, 2nd Edition

(e) 10101.11

Binary-32 (10101.11)2 = (1.010111)2 × 24 M = +(1.010111)2sm SM = 0 (leading 1 of M to be suppressed) E = +(2)10 bias + 2 = 127 + 2 = 129 = (10000001)excess-127 10101.11 = (0 01111101 01011100000000000000000)fp Binary-64 Bias + 2 = 1023 + 2 = 1025 = (10000000001)excess-1023 10101.11 = (0 10000000001 01011100000000000000000000000000000000000000000000000)fp

(f) 10110110.001

Binary-32 (10110110.001)2 = (1.0110110001)2 × 27 M = +(1.0110110001)2sm SM = 0 (leading 1 of M to be suppressed) E = +(7)10 bias + 7 = 127 + 7 = 134 = (10000110)excess-127 10110110.001 = (0 10000110 01101100010000000000000)fp Binary-64 Bias + 7 = 1023 + 7 = 1030 = (10000000110)excess-1023 10110110.001 = (0 10000000110 01101100010000000000000000000000000000000000000000000)fp

1.14 Encode each of the following numbers in BCD. (a) 39 BCD: 0011 1001 (b) 1950 BCD: 0001 1001 0101 0000 (c) 94704 BCD: 1001 0100 0111 0000 0100 (d) 625 BCD: 0110 0010 0101 0101 1.15 Encode each of the following character strings in ASCII code. Represent the encoded strings by hexadecimal numbers. (a) 1980 1 9 8 0 ASCII: 31 39 38 30 (b) A = b + C A = b + C ASCII: 41 20 3D 20 62 20 2B 20 43 (e) COMPUTER ENGINEERING C O M P U T E R E N G I N E E R I N G ASCII: 43 4F 4D 50 55 54 45 52 20 45 4E 47 49 4E 45 45 52 49 4E 47 (d) The End. T h e E n d .

ASCII: 54 68 65 20 45 6E 64 2E

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.16 Repeat problem 1.15 assuming that a parity bit is concatenated to the ASCII codes to yield an odd parity code. (a) 1980 1 9 8 0 ASCII: 31 B9 38 B0 (b) A = b + C A = b + C ASCII: C1 20 3D 20 62 20 AB 20 43 (c) COMPUTER ENGINEERING C O M P U T E R E N G I N E E R I N G ASCII: 43 4F CD D0 D5 54 45 52 20 45 CE C7 49 CE 45 45 52 49 CE C7 (d) The End. T h e E n d .

ASCII: 54 68 E5 20 45 6E 64 AE 1.17 Define a 4-bit code for representing the decimal digits that has the property that the code words for any two digits whose difference is 1 differ in only one bit position and that this property also holds for the digits 0 and 9.

01234-

0000 0001 0011 0010 0110

56789-

0111 0101 0100 1100 1000

1.18 How many bit errors can be detected in a two-out-of-five code? How many errors, if any, can be corrected in a two-out-of-five code? Prove your answers mathematically.

To correct t errors and detect s errors: 2t + s + 1 ≤ dmin.

For t = 0, s = 1: 2t + s + 1 = 2 = dmin. Therefore single errors can be detected.

For t = 1, s = 0: 2t + s + 1 = 3 > dmin. Therefore no error correction.

1.19 Examine the Gray-coded disk of Fig 1.5. Suppose the display lights give the following indications: A is off, B is on, C is on, and D is flickering on and off. Locate the position of the disk by sector numbers.

A = 0, B = 1, C = 1, D = 0 => sector4 A = 0, B = 1, C = 1, D = 1 => sector5

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.20 For the nine-track magnetic tape of Fig 1.8, the following 8-bit messages are to be recorded. Determine the parity bit to establish odd parity for each message. (a) P10111010 5 1-bits => P=0 (b) P00111000 3 1-bits => P=0 (c) P10011001 4 1-bits => P=1 (d) P01011010 4 1-bits => P=1 1.21 Assume that the following are code words from an eight-bit even parity code. Which code words contain errors? (a) 00000000 0 1-bits => even parity => no error (b) 00110100 1 1-bits => odd parity => error (c) 01010101 4 1-bits => even parity => no error (d) 10111010 5 1-bits => odd parity => error 1.22 Develop a table that shows how check bits are defined across the information bits for Hamming Code 2 in Table 1.13.

Information Words (i3i2i1i0) 0000 0001 010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Hamming Code 2 (i3i2i1i0c3c2c1c0) 00000000 00011011 00101101 00110110 01001110 01010101 01100011 01111000 10000111 10011100 10101010 10110001 11001001 11010010 11100100 11111111

Check bits produce even parity over a subset of information bits. Looking at information bits containing a single 1 bit, if a check bit is 1, then that information bit must be included in that check bit.

- Information Word 0001: i0 = 1 sets c3, c1, and c0.

- Information Word 0010: i1 = 1 sets c3, c2, and c0.

-

Information Word 0100: i2 = 1 sets c3, c2, and c1.

-

Information Word 1000: i3 = 1 sets c2, c1, and c0.

Therefore, these check bits produce even parity over the following sets of information bits. c3 : i2, i1 , i0 c2 : i3, i2 , i1 c1 : i3, i2 , i0 c0 : i3, i1 , i0

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.23 Develop a syndrome table for Hamming Code 2 that covers the cases of no error, single errors, and double errors that involved information bit i3.

Each syndrome is the product of Hamming matrix H and the transpose of error vector eT. For example, for Hamming Code 2 and error vector 10000001, which contains errors in bits i3 and c0, the syndrome is:

0 1 𝑠𝑠 = 𝐻𝐻𝑒𝑒 𝑇𝑇 = � 1 1

1 1 1 0

1 1 0 1

1 0 1 1

1 0 0 0

0 1 0 0

0 0 1 0

1 ⎡0⎤ ⎢0⎥ 0 ⎢ ⎥ 0 0 � × ⎢ ⎥ = [0 1 0 ⎢0⎥ 1 ⎢0⎥ ⎢0⎥ ⎣1⎦

1 0]

The remaining syndromes, as listed in the following table, are determined by multiplying this Hamming matrix H by the transpose, eT, of each of the 16 error patterns that contain no errors, a single error, or a double error that includes bit i3.

Error Pattern 00000000 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 10000001 10000010 10000100 10001000 10010000 10100000 11000000

Syndrome 0000 0001 0010 0100 1000 1011 1101 1110 0111 0110 0101 0011 1111 1100 1010 1001

Meaning No error Error in c0 Error in c1 Error in c2 Error in c3 Error in i0 Error in i1 Error in i2 Error in i3 Errors in i3 and c0 Errors in i3 and c1 Errors in i3 and c2 Errors in i3 and c3 Errors in i3 and i0 Errors in i3 and i1 Errors in i3 and i2

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Digital Logic Circuit Analysis and Design, 2nd Edition

1.24 Find examples that show Hamming Code 2 is not double-error correcting nor triple-error detecting.

Double-error correcting: Since dmin = 4, a double error can produce a non-code word that is distance 2 from two or more valid code words.

Ex. Errors in bits c1 and c0 of code word 00000000 result in non-code word 00000011, which is distance 2 from code words 00000000, 00011011, 01100011, 10000111.

Therefore, we cannot determine which of these four code words contains the double error that produced 00000011, so the error is not correctable.

Triple-error detecting: Since dmin = 4, a triple error can produce a non-code word that is distance 1 from another code word.

Ex. Errors in bits c3, c2 and c1 of code word 00000000 result in non-code word 00001110, which is distance 3 from the original code word, but distance 1 from code word 01001110. Therefore, we cannot determine whether the erroneous non-code word resulted from a single error in code word 01001110 or a triple error in code word 00000000.

1.25 The following defines the check bits of a Hamming code for encoding eight-bit information words (i7i6i5i4i3i2i1i0). c3: i7,i6,i5,i3,i2 c1: i7,i5,i4,i2,i0 c2: i7,i6,i4,i3,i1 c0: i6,i5,i4,i1,i0 (a) How many information words are there?

8 information bits => 28 = 256 information words. (b) How many code words?

256 (one code word per information word). (c) Encode information words 00000000, 01010101, 10101010, 11111111.

00000000: All check bits will be 0, so code word = 00000000 0000 01010101: 𝑐𝑐3 = 𝑖𝑖7 ⨁𝑖𝑖6 ⨁𝑖𝑖5 ⨁𝑖𝑖3 ⨁𝑖𝑖2 = 0⨁1⨁0⨁0⨁1 = 0 𝑐𝑐2 = 𝑖𝑖7 ⨁𝑖𝑖6 ⨁𝑖𝑖4 ⨁𝑖𝑖3 ⨁𝑖𝑖1 = 0⨁1⨁1⨁0⨁0 = 0 𝑐𝑐1 = 𝑖𝑖7 ⨁𝑖𝑖5 ⨁𝑖𝑖4 ⨁𝑖𝑖2 ⨁𝑖𝑖0 = 0⨁0⨁1⨁1⨁1 = 1 𝑐𝑐0 = 𝑖𝑖6 ⨁𝑖𝑖5 ⨁𝑖𝑖4 ⨁𝑖𝑖1 ⨁𝑖𝑖0 = 1⨁0⨁1⨁0⨁1 = 1 Code word = 01010101 0011 10101010: 𝑐𝑐3 = 𝑖𝑖7 ⨁𝑖𝑖6 ⨁𝑖𝑖5 ⨁𝑖𝑖3 ⨁𝑖𝑖2 = 1⨁0⨁1⨁1⨁0 = 1 𝑐𝑐2 = 𝑖𝑖7 ⨁𝑖𝑖6 ⨁𝑖𝑖4 ⨁𝑖𝑖3 ⨁𝑖𝑖1 = 1⨁0⨁0⨁1⨁1 = 1 𝑐𝑐1 = 𝑖𝑖7 ⨁𝑖𝑖5 ⨁𝑖𝑖4 ⨁𝑖𝑖2 ⨁𝑖𝑖0 = 1⨁1⨁0⨁0⨁0 = 0 𝑐𝑐0 = 𝑖𝑖6 ⨁𝑖𝑖5 ⨁𝑖𝑖4 ⨁𝑖𝑖1 ⨁𝑖𝑖0 = 0⨁1⨁0⨁1⨁0 = 0 Code word = 10101010 1100

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Digital Logic Circuit Analysis and Design, 2nd Edition

11111111: 𝑐𝑐3 = 𝑖𝑖7 ⨁𝑖𝑖6 ⨁𝑖𝑖5 ⨁𝑖𝑖3 ⨁𝑖𝑖2 = 1⨁1⨁1⨁1⨁1 = 1 𝑐𝑐2 = 𝑖𝑖7 ⨁𝑖𝑖6 ⨁𝑖𝑖4 ⨁𝑖𝑖3 ⨁𝑖𝑖1 = 1⨁1⨁1⨁1⨁1 = 1 𝑐𝑐1 = 𝑖𝑖7 ⨁𝑖𝑖5 ⨁𝑖𝑖4 ⨁𝑖𝑖2 ⨁𝑖𝑖0 = 1⨁1⨁1⨁1⨁1 = 1 𝑐𝑐0 = 𝑖𝑖6 ⨁𝑖𝑖5 ⨁𝑖𝑖4 ⨁𝑖𝑖1 ⨁𝑖𝑖0 = 1⨁1⨁1⨁1⨁1 = 1 Code word = 11111111 1111

(d) What is the error detection and correction properties of this code?

Since information bits i1 and i0 are each included in only 2 check bits, the minimum weight of a code word is 3, and minimum distance dmin = 3. Therefore, this code is capable of correcting a single error, but cannot detect double errors.

Note that this code produces a syndrome of 4 bits, and therefore 16 unique syndromes, which is sufficient only identifying the no error case or the 12 possible single errors, as shown in the next part. (e) Develop a syndrome table that covers no error and single-error cases.

Error Pattern Syndrome 0000 000000000000 0001 000000000001 000000000010 0010 000000000100 0100 000000001000 1000 0011 000000010000 0101 000000100000 1010 000001000000 1100 000010000000 0111 000100000000 001000000000 1011 010000000000 1101 100000000000 1110

Meaning No error Error in c0 Error in c1 Error in c2 Error in c3 Error in i0 Error in i1 Error in i2 Error in i3 Error in i4 Error in i5 Error in i6 Error in i7

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Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 2 – Logic Circuits and Boolean Algebra 2.1 Construct truth tables for the following AND and OR gates. a b c f (a) (b) 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1

(c)

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 0 1 1 1 1 1 1 1

(d)

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.2 Construct truth tables for the following NAND and NOR gates. (a)

(c)

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 1 1 1 1 1 1 1 0

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 1 0 0 0 0 0 0 0

(b)

(d)

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.3 Construct truth tables for the following XOR and XNOR gates. (a)

(c)

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 0 1 1 0 1 0 0 1

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 1 0 0 1 0 1 1 0

(b)

(d)

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.4 Prove that the 3-variable XOR function is equivalent to the sum function of a full-adder.

3-variable XOR function: Full-adder sum function: (odd number of 1s) (a + b + c = 01 or 11) a b c f a b c f 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 Identical truth tables => equivalent functions.

2.5 Prove that the 3-variable majority function is equivalent to the carry function of a fulladder.

3-variable majority function: Full-adder carry function: (2 or more 1-bits) (a + b + c > 1) a b c f a b c f 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 Identical truth tables => equivalent functions.

2.6 Prove that a 3-variable XOR function is equivalent to a 3-variable odd parity function.

3-variable XOR (odd # 1s): Full-adder sum (a + b + c = 01 or 11) a b c f a b c f 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 Identical truth tables => equivalent functions.

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.7 Construct a truth table for the 3-variable even parity function. a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

f 1 0 0 1 0 1 1 0

f(a,b,c) = 1 if even number of 1-bits (0 or 2 1-bits)

2.8 Draw a block (I/O) diagram and construct a truth table for the function defined by the following Verilog model. module problem_2_8 (x, y, z); input x, y; output z; wire a, b, c; nand (a, x, y); nand (b, a, x); nand (c, a, y); nand (z, b, c); endmodule

x y 𝑎𝑎 = 𝑥𝑥𝑥𝑥 𝑏𝑏 = 𝑎𝑎𝑎𝑎 𝑐𝑐 = 𝑎𝑎𝑎𝑎 𝑧𝑧 = 𝑏𝑏𝑏𝑏

0 0 1 1

0 1 0 1

1 1 1 0

1 1 0 1

1 0 1 1

0 1 1 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.9 Repeat problem 2.8 for the following model. module problem_2_9 (A,B,C,f,g); input A,B,C; output f,g; assign f = ~A&~B&C | B&~C | A&B; assign g = ~A&C | A&~B&C | A&B&~C; endmodule

A B C 𝐴𝐴̅𝐵𝐵�𝐶𝐶 𝐵𝐵𝐶𝐶 𝐴𝐴𝐴𝐴 𝑓𝑓 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐴𝐴 𝐴𝐴̅𝐶𝐶 𝐴𝐴𝐵𝐵�𝐶𝐶 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝑔𝑔 = 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 0 0 0 0 0

0 0 1 0 0 0 1 0

0 0 0 0 0 0 1 1

0 1 1 0 0 0 1 1

0 1 0 1 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

0 1 0 1 0 1 1 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.10 Draw a block (I/O) diagram and construct a truth table for the function defined by the following VHDL model. entity prob2_10 is port (x, y: in bit; z: out bit); end prob2_10; architecture structure of prob2_10 is signal a, b, c: bit; begin process (x,y) begin a <= x nor y; b <= x nor a; c <= y nor a; z <= a nor b; end process; end structure;

x y 𝑎𝑎 = 𝑥𝑥 + 𝑦𝑦 𝑏𝑏 = 𝑥𝑥 + 𝑎𝑎 𝑐𝑐 = 𝑦𝑦 + 𝑎𝑎 𝑧𝑧 = 𝑎𝑎 + 𝑏𝑏

0 0 1 1

0 1 0 1

1 0 0 0

0 1 0 0

0 0 1 0

0 0 1 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.11 Repeat problem 2.10 for the following model. entity prob2_11 is port (A, B, C: in bit; f, g: out bit); end prob2_11; architecture structure of prob2_11 is begin process (x,y) begin f <= ((not A) and (not B)) or (B and C) or (A and C); g <= ((not A) and (not B)) or ((not B) and (not C)) or (A and B and C); end process; end structure; A B C 𝐴𝐴̅𝐵𝐵� 𝐵𝐵𝐵𝐵 𝐴𝐴𝐴𝐴 𝑓𝑓 = 𝐴𝐴̅𝐵𝐵� + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴 𝐵𝐵�𝐶𝐶̅ 𝐴𝐴𝐴𝐴𝐴𝐴 𝑔𝑔 = 𝐴𝐴̅𝐵𝐵� + 𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 1

1 1 0 1 0 1 0 1

1 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1

1 1 0 0 1 0 0 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.12 Construct truth tables for the following functions. (a) 𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐 a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

𝑎𝑎𝑎𝑎 0 0 0 0 0 0 1 1

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐 0 1 0 1 0 0 1 1

𝑎𝑎𝑐𝑐 0 1 0 1 0 0 0 0

(b) 𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵 + 𝐶𝐶𝐷𝐷) + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

𝐶𝐶𝐷𝐷

0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0

𝐵𝐵 + 𝐶𝐶𝐷𝐷

1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1

𝐴𝐴(𝐵𝐵 + 𝐶𝐶𝐷𝐷)

0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1

𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

𝐴𝐴(𝐵𝐵 + 𝐶𝐶𝐷𝐷) + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷

0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1

(c) g(a,b,c) = ∑m(1,4,5) m0 m1 m2 m3 m4 m5 m6 m7

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

g(a,b,c) 0 1 0 0 1 1 0 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) h(a,b,c) = ∏M(2,5,6,7) M0 M1 M2 M3 M4 M5 M6 M7

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

h(a,b,c) 1 1 0 1 1 0 0 0

2.13 Simplify (minimum literals) the following using the postulates and theorems of Boolean algebra. (a) �𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴��𝐴𝐴 + 𝐵𝐵�

= �𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴�𝐴𝐴 + �𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴�𝐵𝐵 [P5]

= 𝐴𝐴𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐵𝐵 = 0 + 𝐴𝐴𝐴𝐴 + 0 + 𝐴𝐴𝐵𝐵𝐶𝐶

= 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵𝐶𝐶 = 𝐴𝐴𝐵𝐵𝐶𝐶

[P5] [P6] [P2] [T4]

(b) 𝑓𝑓(𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥 + 𝑥𝑥𝑥𝑥𝑥𝑥 + 𝑥𝑥𝑦𝑦𝑦𝑦 + 𝑤𝑤𝑤𝑤 + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 [T4a] [T5a] = 𝑥𝑥 + 𝑥𝑥𝑦𝑦𝑦𝑦 + 𝑤𝑤𝑤𝑤 + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 [T4𝑎𝑎] = 𝑥𝑥 + yz + wx + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 [T4a] = 𝑥𝑥 + 𝑦𝑦𝑦𝑦 + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 [T5a] = 𝑥𝑥 + 𝑦𝑦𝑦𝑦 + x𝑦𝑦 [T4a] = 𝑥𝑥 + 𝑦𝑦𝑦𝑦 + 𝑦𝑦 = 𝑥𝑥 + 𝑦𝑦

2.14 Use DeMorgan’s theorem to complement the following expressions. (a) 𝑋𝑋𝑋𝑋 + 𝐴𝐴𝐶𝐶 + 𝐷𝐷𝐷𝐷

𝑋𝑋𝑋𝑋 + 𝐴𝐴𝐶𝐶 + 𝐷𝐷𝐷𝐷 = (𝑋𝑋𝑋𝑋)(𝐴𝐴𝐶𝐶)(𝐷𝐷𝐷𝐷)

(b) 𝑋𝑋 �𝑌𝑌 + 𝑍𝑍�𝑄𝑄 + 𝑅𝑅��

= (𝑋𝑋 + 𝑌𝑌)(𝐴𝐴 + 𝐶𝐶)(𝐷𝐷 + 𝐸𝐸)

𝑋𝑋(𝑌𝑌 + 𝑍𝑍(𝑄𝑄 + 𝑅𝑅)) = 𝑋𝑋 + (𝑌𝑌 + 𝑍𝑍�𝑄𝑄 + 𝑅𝑅�) = 𝑋𝑋 + 𝑌𝑌(𝑍𝑍�𝑄𝑄 + 𝑅𝑅�)

= 𝑋𝑋 + 𝑌𝑌(𝑍𝑍 + �𝑄𝑄 + 𝑅𝑅�)

= 𝑋𝑋 + 𝑌𝑌(𝑍𝑍 + 𝑄𝑄𝑅𝑅)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.15 Prove the following using appropriate methods.

(a) 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴 + 𝐵𝐵�𝐶𝐶̅ = 𝐴𝐴̅𝐵𝐵� + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐶𝐶̅ Expanding each side to canonical SOP form using Theorem 6: 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴 + 𝐵𝐵�𝐶𝐶̅ = 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ = Σ𝑚𝑚(0,1,3,4,6,7) 𝐴𝐴̅𝐵𝐵� + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐶𝐶̅ = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ = Σ𝑚𝑚(0,1,3,4,6,7)

Since the two expressions have the same canonical SOP form, they are equal. (b) 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵� ≠ 𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐴𝐴 Expanding to canonical SOP form using Theorem 6: 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵� = 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶 = Σ𝑚𝑚(3,4,5,6,7)

𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴 = Σ𝑚𝑚(0,2,3,4,5,7)

Since the two expressions have different canonical SOP forms, they are not equal.

2.16 Find canonical SOP and POS forms for the functions in Problems 2.12 (a) and (c). (a)

(c)

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑐𝑐 = Σ𝑚𝑚(1,3,6,7) = 𝑚𝑚1 + 𝑚𝑚3 + 𝑚𝑚6 + 𝑚𝑚7 = 𝑎𝑎�𝑏𝑏�𝑐𝑐 + 𝑎𝑎�𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = Σ𝑚𝑚(1,3,6,7) = Π𝑀𝑀(0,2,4,5) = 𝑀𝑀0 ∙ 𝑀𝑀2 ∙ 𝑀𝑀4 ∙ 𝑀𝑀5 = (𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐) 𝑔𝑔(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = Σ𝑚𝑚(1,4,5) = 𝑚𝑚1 + 𝑚𝑚4 + 𝑚𝑚5 = 𝑎𝑎�𝑏𝑏�𝑐𝑐 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐

𝑔𝑔(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = Σ𝑚𝑚(1,4,5) = Π𝑀𝑀(0,2,3,6,7) = 𝑀𝑀0 ∙ 𝑀𝑀2 ∙ 𝑀𝑀3 ∙ 𝑀𝑀6 ∙ 𝑀𝑀7 = (𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐̅)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.17 Find minterm and maxterm list forms for f and f as defined in the following truth table. x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

f 1 0 1 1 0 1 0 1

𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = Σ𝑚𝑚(0,2,3,5,7) = Π𝑀𝑀(1,4,6)

𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = Σ𝑚𝑚(1,4,6) = Π𝑀𝑀(0,2,3,5,7)

2.18 Using Boolean algebra, simplify each of the following expressions. (a) 𝑓𝑓(𝑤𝑤, 𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥 + 𝑥𝑥𝑥𝑥𝑥𝑥 + 𝑥𝑥𝑦𝑦𝑦𝑦 + 𝑤𝑤𝑤𝑤 + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 [T4a]

= 𝑥𝑥 + 𝑥𝑥𝑦𝑦𝑦𝑦 + 𝑤𝑤𝑤𝑤 + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 = 𝑥𝑥 + yz + wx + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 = 𝑥𝑥 + 𝑦𝑦𝑦𝑦 + 𝑤𝑤𝑥𝑥 + 𝑥𝑥𝑦𝑦 = 𝑥𝑥 + 𝑦𝑦𝑦𝑦 + x𝑦𝑦 = 𝑥𝑥 + 𝑦𝑦𝑦𝑦 + 𝑦𝑦 = 𝑥𝑥 + 𝑦𝑦

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = (𝐴𝐴𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐶𝐶̅ + 𝐷𝐷)(𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸) = (𝐴𝐴𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐶𝐶̅ + 𝐷𝐷)

= (𝐴𝐴𝐴𝐴 + 𝐶𝐶)𝐶𝐶̅ + 𝐷𝐷

= 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐷𝐷

(c)𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑦𝑦𝑧𝑧̅(𝑧𝑧̅ + 𝑧𝑧̅𝑥𝑥) + (𝑥𝑥̅ + 𝑧𝑧̅)(𝑥𝑥̅ 𝑦𝑦 + 𝑥𝑥̅ 𝑧𝑧)

[T5a] [T4𝑎𝑎] [T4a] [T5a] [T4a]

[T4b]

[P5a]

[T5b]

[T4b]

= 𝑦𝑦𝑧𝑧̅ + (𝑥𝑥̅ + 𝑧𝑧̅)(𝑥𝑥̅ 𝑦𝑦 + 𝑥𝑥̅ 𝑧𝑧)

[P5b]

= 𝑦𝑦𝑧𝑧̅ + 𝑥𝑥̅ 𝑦𝑦 + 𝑥𝑥̅ 𝑧𝑧

[T7a]

= 𝑦𝑦𝑧𝑧̅ + (𝑥𝑥̅ + 𝑧𝑧̅)𝑥𝑥̅ (𝑦𝑦 + 𝑧𝑧)

= 𝑦𝑦𝑧𝑧̅ + 𝑥𝑥̅ (𝑦𝑦 + 𝑧𝑧) = 𝑦𝑦𝑧𝑧̅ + 𝑥𝑥̅ 𝑧𝑧

[T4b]

[P5b]

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.19 Simplify each of the following logic expressions. (a)𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶)(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷) = (𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)

[T1b]

= (𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)

[T4b]

[T8b]

= �𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷� + �𝐵𝐵 + 𝐶𝐶� + (𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)

[T8a]

= 𝐴𝐴𝐶𝐶𝐷𝐷 + 𝐵𝐵𝐶𝐶 + 𝐴𝐴𝐵𝐵𝐷𝐷

[T7b]

= 𝐴𝐴𝐶𝐶𝐷𝐷 + 𝐵𝐵𝐶𝐶

� + 𝐵𝐵𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵 + 𝐶𝐶𝐷𝐷 � 𝐴𝐴 + 𝐴𝐴̅𝐷𝐷 + 𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 � (b)𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐷𝐷

[T6a]

� + 𝐵𝐵𝐷𝐷 � + 𝐶𝐶𝐷𝐷 � 𝐴𝐴 + 𝐴𝐴̅𝐷𝐷 + 𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 � = 𝐵𝐵 + 𝐴𝐴̅𝐷𝐷 � + 𝐶𝐶𝐷𝐷 � 𝐴𝐴 + 𝐴𝐴̅𝐷𝐷 + 𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 � = 𝐵𝐵 + 𝐴𝐴̅𝐷𝐷

[T4a]

� 𝐴𝐴 + 𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 � = 𝐵𝐵 + 𝐴𝐴̅ + 𝐶𝐶𝐷𝐷

[T6a]

[T4a]

� + 𝐶𝐶𝐶𝐶 = 𝐵𝐵 + 𝐴𝐴̅ + 𝐶𝐶𝐷𝐷

[T6a]

� 𝐴𝐴 + 𝐶𝐶𝐶𝐶 = 𝐵𝐵 + 𝐴𝐴̅ + 𝐶𝐶𝐷𝐷

[T5a]

= 𝐵𝐵 + 𝐴𝐴̅ + 𝐶𝐶 = 𝐵𝐵𝐴𝐴𝐶𝐶

(c)𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ = 𝐴𝐴𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅

[T8a]

[T4a] [P5b]

= 𝐴𝐴(𝐵𝐵� 𝐶𝐶 + 𝐵𝐵) + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅

[T5a]

= 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅

[T6a]

= 𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴

[T8a]

= 𝐴𝐴 ∙ (𝐴𝐴𝐴𝐴𝐴𝐴)

[P6b]

= 𝐴𝐴(𝐶𝐶 + 𝐵𝐵) + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶̅

[P5b]

= 𝐴𝐴 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴

[T4a]

= 𝐴𝐴 ∙ (𝐴𝐴𝐴𝐴𝐴𝐴)

[T3]

=0

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐵𝐵 + 𝐴𝐴̅)(𝐴𝐴𝐴𝐴 + 𝐶𝐶) + 𝐴𝐴𝐴𝐴𝐴𝐴̅ + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶) [P6b] = (𝐵𝐵 + 𝐴𝐴̅)(𝐴𝐴𝐴𝐴 + 𝐶𝐶) + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶)

[P5a]

= 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶 + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶)

[P5a]

= 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵

[T6a]

= 𝐴𝐴𝐴𝐴 + 𝐶𝐶 + 𝐴𝐴̅𝐵𝐵

[T6a]

= 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶) = 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵 + 𝐵𝐵𝐵𝐵 = 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐶𝐶 + 𝐴𝐴̅𝐵𝐵 = 𝐵𝐵 + 𝐶𝐶

[T4a]

[T1b]

[T4a]

[T8a]

= 𝐵𝐵� 𝐶𝐶̅

(e) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐴𝐴̅ + 𝐵𝐵� )(𝐴𝐴 + 𝐴𝐴̅𝐵𝐵)(𝐴𝐴̅ + 𝐵𝐵� + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶) + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶) = (𝐴𝐴̅ + 𝐵𝐵� )(𝐴𝐴 + 𝐴𝐴̅𝐵𝐵)(𝐴𝐴̅ + 𝐵𝐵� ) + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶) = 0 + (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶)

[T4a] [P6b] [P2a] [T3]

= (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴̅ + 𝐶𝐶)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.20 Prove part (b) of Theorem 4. 𝑎𝑎(𝑎𝑎 + 𝑏𝑏) = 𝑎𝑎𝑎𝑎 + 𝑎𝑎𝑎𝑎 = 𝑎𝑎 + 𝑎𝑎𝑎𝑎 = 𝑎𝑎

[𝑃𝑃5𝑏𝑏] [𝑇𝑇1𝑏𝑏] [𝑇𝑇4𝑎𝑎]

Alternatively: 𝑎𝑎(𝑎𝑎 + 𝑏𝑏) = (𝑎𝑎 + 0)(𝑎𝑎 + 𝑏𝑏) = 𝑎𝑎 + 0 ∙ 𝑏𝑏 = 𝑎𝑎 + 𝑏𝑏 ∙ 0 = 𝑎𝑎 + 0 = 𝑎𝑎

2.21 Prove part (b) of Theorem 5. 𝑎𝑎(𝑎𝑎� + 𝑏𝑏) = 𝑎𝑎𝑎𝑎� + 𝑎𝑎𝑎𝑎 = 0 + 𝑎𝑎𝑎𝑎 = 𝑎𝑎𝑎𝑎 + 0 = 𝑎𝑎𝑎𝑎

[𝑃𝑃2𝑎𝑎] [𝑃𝑃5𝑎𝑎] [𝑃𝑃3𝑎𝑎] [𝑃𝑃6𝑏𝑏] [𝑃𝑃2𝑎𝑎]

[𝑃𝑃5𝑏𝑏] [𝑃𝑃6𝑏𝑏] [𝑃𝑃3𝑎𝑎] [𝑃𝑃2𝑎𝑎]

2.22 Prove part (b) of Theorem 7 (consensus). (𝑎𝑎 + 𝑏𝑏)(𝑎𝑎� + 𝑐𝑐)(𝑏𝑏 + 𝑐𝑐) = (𝑎𝑎 + 𝑏𝑏)(𝑎𝑎� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐)

= (𝑎𝑎 + 𝑏𝑏)(𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐)(𝑎𝑎� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐) = (𝑎𝑎 + 𝑏𝑏)(𝑎𝑎� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐) = (𝑎𝑎 + 𝑏𝑏)(𝑎𝑎� + 𝑐𝑐)

2.23 Simplify (minimum literals) each of the following logic expressions. (a) 𝑓𝑓(𝐴𝐴, 𝑋𝑋, 𝑍𝑍) = 𝑋𝑋�(𝑋𝑋 + 𝑍𝑍) + 𝐴𝐴̅ + 𝐴𝐴𝐴𝐴 [T5b] = 𝑋𝑋�𝑍𝑍 + 𝐴𝐴̅ + 𝐴𝐴𝐴𝐴 = 𝑋𝑋�𝑍𝑍 + 𝐴𝐴̅ + 𝑍𝑍

= 𝑋𝑋�𝑌𝑌𝑌𝑌 + 𝑋𝑋𝑋𝑋𝑋𝑋 + 𝑋𝑋�𝑌𝑌𝑌𝑌� + 𝑋𝑋𝑋𝑋𝑌𝑌� = 𝑋𝑋𝑋𝑋 + 𝑋𝑋𝑋𝑋𝑌𝑌�

[T4b]

[T4b]

[T4a]

= (𝑋𝑋�𝑌𝑌 + 𝑋𝑋𝑋𝑋)𝑋𝑋 + (𝑋𝑋�𝑌𝑌 + 𝑋𝑋𝑋𝑋)𝑌𝑌� = 𝑋𝑋𝑋𝑋𝑋𝑋 + 𝑋𝑋𝑋𝑋𝑌𝑌�

[P3b]

[T5a]

= 𝐴𝐴̅ + 𝑍𝑍

(b) 𝑓𝑓(𝑋𝑋, 𝑌𝑌, 𝑍𝑍) = (𝑋𝑋�𝑌𝑌 + 𝑋𝑋𝑋𝑋)(𝑋𝑋 + 𝑌𝑌�)

[T6b]

[P5b] [P5b] [P6b] [T1b] [T4a]

= 𝑋𝑋𝑋𝑋

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥̅ 𝑦𝑦(𝑧𝑧 + 𝑦𝑦�𝑥𝑥) + 𝑦𝑦�𝑧𝑧

= 𝑥𝑥̅ 𝑦𝑦𝑦𝑦 + 𝑥𝑥̅ 𝑦𝑦𝑦𝑦�𝑥𝑥 + 𝑦𝑦�𝑧𝑧 = 𝑥𝑥̅ 𝑦𝑦𝑦𝑦 + 𝑦𝑦�𝑧𝑧

= (𝑥𝑥̅ 𝑦𝑦 + 𝑦𝑦�)𝑧𝑧 = (𝑥𝑥̅ + 𝑦𝑦�)𝑧𝑧

[P5b] [P6b] [P5b] [T5a] [P5b]

= 𝑥𝑥̅ 𝑧𝑧 + 𝑦𝑦�𝑧𝑧

2.24 Find the simplest logic expression for each of the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(1,4,5) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐵𝐵� = 𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐵𝐵�

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,2,4,5,8,11,15) �) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) ∙ (𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 ̅ � � � = (𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷) � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) ∙ (𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 ̅ � �) = (𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 �) ∙ (𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷 ̅ ̅ � � = (𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷) (c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,5,8,9,10,13) � + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 ̅ ̅ ̅ ̅ � � � � � � � = 𝐴𝐴𝐵𝐵 𝐷𝐷 + 𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵 𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵 𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵 𝐶𝐶𝐷𝐷 � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐷𝐷 � + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 ̅ ̅ � + 𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶 𝐷𝐷 = 𝐵𝐵� 𝐷𝐷 � � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ = 𝐵𝐵 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.25 Given the function f ( x, y, z ) = xy + xz write f ( x, y, z ) as a sum of minterms and as a product of maxterms.

If canonical SOP derived first: 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥𝑦𝑦� + 𝑥𝑥𝑧𝑧̅ = 𝑥𝑥𝑦𝑦�(𝑧𝑧̅ + 𝑧𝑧) + 𝑥𝑥(𝑦𝑦� + 𝑦𝑦)𝑧𝑧̅ = 𝑥𝑥𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥𝑦𝑦�𝑧𝑧 + 𝑥𝑥𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥𝑥𝑥𝑧𝑧̅ = 𝑥𝑥𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥𝑦𝑦�𝑧𝑧 + 𝑥𝑥𝑥𝑥𝑧𝑧̅ = 𝑚𝑚4 + 𝑚𝑚5 + 𝑚𝑚6 = ∑ 𝑚𝑚(4,5,6) = ∏ 𝑀𝑀(0,1,2,3,7)

If canonical POS derived first: 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥𝑦𝑦� + 𝑥𝑥𝑧𝑧̅ = 𝑥𝑥(𝑦𝑦� + 𝑧𝑧̅) = (𝑥𝑥 + 𝑦𝑦�)(𝑥𝑥 + 𝑦𝑦)(𝑦𝑦� + 𝑧𝑧̅) = (𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦)(𝑦𝑦� + 𝑧𝑧̅) = (𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧)(𝑦𝑦� + 𝑧𝑧̅) = (𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧)(𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧̅) = (𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧)(𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧̅) = 𝑀𝑀3 𝑀𝑀2 𝑀𝑀1 𝑀𝑀0 𝑀𝑀7 = ∏ 𝑀𝑀(0,1,2,3,7) = ∑ 𝑚𝑚(4,5,6) 2.26 Use the postulates and theorems of Boolean algebra to find an MSOP logic expression for each of the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(1,4,5,6) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ = 𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ = 𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐶𝐶̅ � ) + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 (b) 𝑔𝑔(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵 𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐴𝐴𝐷𝐷

(c) ℎ(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∏ 𝑀𝑀(5,6,7) = ∑ 𝑚𝑚(0,1,2,3,4) = 𝑎𝑎�𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐 + 𝑎𝑎�𝑏𝑏𝑐𝑐̅ + 𝑎𝑎�𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ = 𝑎𝑎�𝑏𝑏� + 𝑎𝑎�𝑏𝑏𝑐𝑐̅ + 𝑎𝑎�𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ = 𝑎𝑎�𝑏𝑏� + 𝑎𝑎�𝑏𝑏 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ = 𝑎𝑎� + 𝑎𝑎𝑏𝑏� 𝑐𝑐̅ = 𝑎𝑎� + 𝑏𝑏�𝑐𝑐̅

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.27 Use the postulates and theorems of Boolean algebra to find an MPOS logic expression for each of the functions given in problem 2.26. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(1,4,5,6) = ∏ 𝑀𝑀(0,2,3,7) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ ) = (𝐴𝐴 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ ) = (𝐴𝐴 + 𝐶𝐶)(𝐵𝐵� + 𝐶𝐶̅ )

� ) + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 (b) 𝑔𝑔(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷

� + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � + 𝐶𝐶̅ 𝐷𝐷 + 𝐶𝐶𝐷𝐷 � + 𝐶𝐶𝐶𝐶) + 𝐴𝐴(𝐵𝐵� + 𝐵𝐵)𝐶𝐶𝐷𝐷 = 𝐴𝐴𝐵𝐵�(𝐶𝐶̅ 𝐷𝐷 ̅ ̅ � � � � � � � � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 = 𝑚𝑚8 + 𝑚𝑚9 + 𝑚𝑚10 + 𝑚𝑚11 + 𝑚𝑚10 + 𝑚𝑚14 + 𝑚𝑚5 = ∑ 𝑚𝑚(5,8,9,10,11,14) = ∏ 𝑀𝑀(0,1,2,3,4,6,7,12,13,15) � )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) ∙ (𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) ∙ (𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷) (𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐶𝐶̅ )(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷) (𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐶𝐶̅ )(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷) (𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷

(c) ℎ(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∏ 𝑀𝑀(5,6,7)

= (𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐̅)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐̅) = (𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐̅)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐̅)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐̅) = (𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐̅)(𝑎𝑎� + 𝑏𝑏�) (𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐̅) = (𝑎𝑎� + 𝑐𝑐̅)(𝑎𝑎� + 𝑏𝑏�)

2.28 Map the functions given in problem 2.26 on K-maps showing both minterms (1s) and maxterms (0s). (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(1,4,5,6) = ∏ 𝑀𝑀(0,2,3,7)

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Digital Logic Circuit Analysis and Design, 2nd Edition

� ) + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = ∑ 𝑚𝑚(5,8 − 11,14) = ∏ 𝑀𝑀(0 − 4,6,7,12,13,15) (b) 𝑔𝑔(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷

(c) ℎ(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∏ 𝑀𝑀(5,6,7) = ∑ 𝑚𝑚(0 − 4)

2.29 Use K-maps to find MSOP and MPOS expressions for each of the following logic functions. (a) F(x,y,z) = ∑m(0,1,3,4,6,7)

OR:

𝐹𝐹(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥̅ 𝑦𝑦� + 𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑧𝑧̅

𝐹𝐹(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = (𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧̅)

𝐹𝐹(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥̅ 𝑧𝑧 + 𝑥𝑥𝑥𝑥

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) G(a,b,c,d) = ∑m(0,1,2,3,7,8,9,12,13,14)

𝐺𝐺(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑎𝑎�𝑏𝑏� + 𝑎𝑎𝑐𝑐̅ + 𝑎𝑎�𝑐𝑐𝑐𝑐 + 𝑎𝑎𝑎𝑎𝑑𝑑̅

(c) H(a,b,c,d) = ∏M(4,5,6,7,13,15)

𝐺𝐺(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = (𝑎𝑎 + 𝑏𝑏� + 𝑑𝑑)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐̅) ∙ (𝑎𝑎� + 𝑐𝑐̅ + 𝑑𝑑̅)

𝐻𝐻(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑏𝑏� + 𝑎𝑎𝑑𝑑̅

𝐻𝐻(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = (𝑎𝑎 + 𝑏𝑏�)(𝑏𝑏� + 𝑑𝑑̅)

2.30 Use K-maps to find MSOP and MPOS expressions for the complement function (F) from problem 2.29 (a).

Treat 1s as 0s for MPOS Treat 0s as 1s for MSOP

𝐹𝐹� (𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = (𝑥𝑥 + 𝑦𝑦)(𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥̅ + 𝑧𝑧)

𝐹𝐹� (𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥̅ 𝑦𝑦𝑧𝑧̅ + 𝑥𝑥𝑦𝑦�𝑧𝑧

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.31 Use K-maps to find MSOP and MPOS expressions for the following incompletely specified functions. (a) f(a,b,c,d) = ∑m(1,5,7,9) + d(6,13)

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑐𝑐̅𝑑𝑑 + 𝑎𝑎�𝑏𝑏𝑏𝑏

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑑𝑑(𝑏𝑏 + 𝑐𝑐̅)(𝑎𝑎� + 𝑐𝑐̅) or 𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑑𝑑(𝑏𝑏 + 𝑐𝑐̅)(𝑎𝑎� + 𝑏𝑏�)

(b) g(a,b,c,d) = ∏M(3,6,8,9,14) · D(1,2,4,7,11,12,13)

𝑔𝑔(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑎𝑎�𝑐𝑐̅ + 𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑏𝑏�𝑐𝑐

𝑔𝑔(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = (𝑏𝑏� + 𝑑𝑑)(𝑎𝑎 + 𝑐𝑐̅)(𝑎𝑎� + 𝑐𝑐)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.32 Use Venn diagrams to determine which of the following switching functions are equivalent. (a) f1 ( A, B, C ) = AB C + B + A B C

(b) f 2 ( A, B, C ) = A B C + B + AB C

(c) f 3 ( A, B, C ) = A C + AC + BC + A B

(d) f 4 ( A, B, C ) = AC + AB + BC + A C

Fom the above Venn diagrams, we see that: 𝑓𝑓1 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) and 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝑓𝑓3 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶).

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.33 Sketch the following functions on a Venn diagram. (a) f ( A, B) = AB + A B

(b) f ( A, B, C ) = AB + A C

(c) f ( A, B, C , D) = A + B CD + A BD

(d) f ( A, B, C , D) = A B + CD

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.34 Prove that the following expressions are valid using Venn diagrams. (a) A + B = AB + A B + AB = A B

(b) AC + BC + AB ≠ B C + A B + AC

(c) A C + AB + B C = A B + BC + AC

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) AD + AC D + AB + A BD + A B C = AB + BD + AD + B C

2.35 Use Theorem 5 to simplify the following expressions: (a) 𝑋𝑋� + 𝑋𝑋𝑋𝑋𝑋𝑋𝐶𝐶̅ + 𝐵𝐵� 𝐶𝐶 = 𝑋𝑋� + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐵𝐵� 𝐶𝐶 (b) 𝑋𝑋�𝑌𝑌� + (𝑋𝑋 + 𝑌𝑌)𝑍𝑍 = 𝑋𝑋�𝑌𝑌� + (𝑋𝑋�𝑌𝑌�)𝑍𝑍 = 𝑋𝑋�𝑌𝑌� + 𝑍𝑍 (c) 𝑍𝑍(𝑍𝑍̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ ) + 𝐴𝐴̅𝐵𝐵� = 𝑍𝑍𝑍𝑍𝑍𝑍𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵� (d) (𝑋𝑋� + 𝑌𝑌�)(𝑋𝑋𝑋𝑋 + 𝑍𝑍) = (𝑋𝑋� + 𝑌𝑌�) �(𝑋𝑋� + 𝑌𝑌�) + 𝑍𝑍� = (𝑋𝑋� + 𝑌𝑌�)𝑍𝑍

2.36 Use Theorem 8 (DeMorgan's) to complement the following expressions: (a) X (Y + Z (Q + R )) 𝑋𝑋(𝑌𝑌 + 𝑍𝑍̅(𝑄𝑄 + 𝑅𝑅� )) = 𝑋𝑋� + (𝑌𝑌 + 𝑍𝑍̅(𝑄𝑄 + 𝑅𝑅� )) = 𝑋𝑋� + 𝑌𝑌�(𝑍𝑍̅(𝑄𝑄 + 𝑅𝑅� )) = 𝑋𝑋� + 𝑌𝑌�(𝑍𝑍 + (𝑄𝑄 + 𝑅𝑅� )) = 𝑋𝑋� + 𝑌𝑌�(𝑍𝑍 + 𝑄𝑄� 𝑅𝑅)

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) X + Y ( Z + QR ) 𝑋𝑋 + 𝑌𝑌(𝑍𝑍̅ + 𝑄𝑄𝑅𝑅� ) = 𝑋𝑋�(𝑌𝑌(𝑍𝑍̅ + 𝑄𝑄𝑅𝑅� )) = 𝑋𝑋�(𝑌𝑌� + (𝑍𝑍̅ + 𝑄𝑄𝑅𝑅� )) = 𝑋𝑋�(𝑌𝑌� + (𝑍𝑍(𝑄𝑄𝑅𝑅� )) = 𝑋𝑋�(𝑌𝑌� + (𝑍𝑍(𝑄𝑄� + 𝑅𝑅))

(c) XY + AC + IQ 𝑋𝑋𝑋𝑋 + 𝐴𝐴𝐶𝐶̅ + 𝐼𝐼𝐼𝐼 = (𝑋𝑋𝑋𝑋)(𝐴𝐴𝐶𝐶̅ )(𝐼𝐼𝐼𝐼) = (𝑋𝑋� + 𝑌𝑌�)(𝐴𝐴̅ + 𝐶𝐶)(𝐼𝐼 ̅ + 𝑄𝑄� )

(d) ( A + BC )( A + D E ) � 𝐸𝐸) = �𝐴𝐴 + 𝐵𝐵𝐶𝐶̅ � + (𝐴𝐴̅ + 𝐷𝐷 � 𝐸𝐸) (𝐴𝐴 + 𝐵𝐵𝐶𝐶̅ )(𝐴𝐴̅ + 𝐷𝐷 � 𝐸𝐸) = 𝐴𝐴̅(𝐵𝐵𝐶𝐶̅ ) + 𝐴𝐴(𝐷𝐷 = 𝐴𝐴̅(𝐵𝐵� + 𝐶𝐶) + 𝐴𝐴(𝐷𝐷 + 𝐸𝐸� )

2.37 Apply Boolean algebra Theorem 7 (consensus) to simplify the following expressions: (a) 𝑄𝑄𝑄𝑄 + 𝑋𝑋�𝑄𝑄 + 𝑅𝑅𝑋𝑋 = 𝑋𝑋𝑋𝑋 + 𝑅𝑅𝑅𝑅

(b) (𝑋𝑋 + 𝑌𝑌)𝑍𝑍 + 𝑋𝑋�𝑌𝑌�𝑊𝑊 + 𝑍𝑍𝑍𝑍 = (𝑋𝑋�𝑌𝑌�)𝑍𝑍 + 𝑋𝑋�𝑌𝑌�𝑊𝑊 + 𝑍𝑍𝑍𝑍 = (𝑋𝑋�𝑌𝑌�)𝑍𝑍 + 𝑋𝑋�𝑌𝑌�𝑊𝑊 = (𝑋𝑋 + 𝑌𝑌)𝑍𝑍 + 𝑋𝑋�𝑌𝑌�𝑊𝑊 = 𝑋𝑋𝑋𝑋 + 𝑌𝑌𝑌𝑌 + 𝑋𝑋�𝑌𝑌�𝑊𝑊

(c) (𝑋𝑋� + 𝑌𝑌)𝑊𝑊𝑊𝑊 + 𝑋𝑋𝑌𝑌�𝑉𝑉 + 𝑉𝑉𝑉𝑉𝑉𝑉 = (𝑋𝑋𝑌𝑌�)𝑊𝑊𝑊𝑊 + 𝑋𝑋𝑌𝑌�𝑉𝑉 + 𝑉𝑉𝑉𝑉𝑉𝑉 = (𝑋𝑋𝑌𝑌�)𝑊𝑊𝑊𝑊 + 𝑋𝑋𝑌𝑌�𝑉𝑉 = (𝑋𝑋� + 𝑌𝑌)𝑊𝑊𝑊𝑊 + 𝑋𝑋𝑌𝑌�𝑉𝑉 = 𝑋𝑋�𝑊𝑊𝑊𝑊 + 𝑌𝑌𝑌𝑌𝑌𝑌 + 𝑋𝑋𝑌𝑌�𝑉𝑉

� )(𝑉𝑉 + 𝑋𝑋)(𝑉𝑉� + 𝑌𝑌 + 𝑍𝑍 + 𝑊𝑊 � ) = (𝑉𝑉 + 𝑋𝑋)(𝑉𝑉� + 𝑌𝑌 + 𝑍𝑍 + 𝑊𝑊 �) (d) (𝑋𝑋 + 𝑌𝑌 + 𝑍𝑍 + 𝑊𝑊

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.38 Find truth tables for the following switching functions. (a) f ( A, B) = A + B A B 𝑓𝑓(𝐴𝐴, 𝐵𝐵) = 𝐴𝐴 + 𝐵𝐵� 0 0 1 1

0 1 0 1

(b) f ( A, B, C ) = AB + A C

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C

0 1 0 1 0 1 0 1

𝐴𝐴𝐴𝐴 0 0 0 0 0 0 1 1

𝐴𝐴𝐶𝐶 0 1 0 1 0 0 0 0

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐶𝐶 0 1 0 1 0 0 1 1

𝑎𝑎𝑏𝑏�𝑐𝑐 0 0 0 0 0 1 0 0

𝑏𝑏𝑐𝑐 0 0 1 0 0 0 1 0

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎𝑎𝑎𝑎𝑎 + 𝑏𝑏𝑐𝑐 0 0 1 0 0 1 1 0

(c) f (a, b, c) = ab c + bc

a

b

c

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

a

b

c

1 0 1 1

(d) f (a, b, c) = a (b + c )(b + c) 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

(𝑏𝑏 + 𝑐𝑐̅) 1 0 1 1 1 0 1 1

(𝑏𝑏 + 𝑐𝑐) 1 1 0 1 1 1 0 1

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝑎𝑎(𝑏𝑏 + 𝑐𝑐)(𝑏𝑏 + 𝑐𝑐) 0 0 0 0 1 0 0 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.39 Find truth tables for each of the following logic functions. � (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷

A

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 𝐴𝐴𝐴𝐴𝐶𝐶𝐷𝐷 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

D

𝐴𝐴𝐴𝐴 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

� (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� + 𝐶𝐶𝐷𝐷

A

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

𝐴𝐴̅𝐵𝐵� 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

𝐶𝐶𝐷𝐷 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0

� 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

� 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� + 𝐶𝐶𝐷𝐷 1 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

� ) + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 (c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷

A

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 𝐶𝐶𝐷𝐷 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0

�) (𝐵𝐵� + 𝐶𝐶𝐷𝐷 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 0

�) 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0

𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

�𝐵𝐵𝐶𝐶� 𝐷𝐷 � + 𝐶𝐶𝐷𝐷 � ) + 𝐴𝐴 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0

2.40 Find the minterm and maxterm list forms for the logic functions of Problem 2.39. � (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 = 𝑚𝑚13 + 𝑚𝑚14 = ∑ 𝑚𝑚(13,14) = ∏ 𝑀𝑀(0 − 12,15)

� (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� + 𝐶𝐶𝐷𝐷 ̅ ̅ � � + 𝐶𝐶𝐶𝐶) + 𝐴𝐴̅𝐵𝐵�(𝐶𝐶̅ 𝐷𝐷 � + 𝐶𝐶̅ 𝐷𝐷 + 𝐶𝐶𝐷𝐷 � + 𝐶𝐶𝐶𝐶) = 𝐴𝐴𝐴𝐴(𝐶𝐶 𝐷𝐷 + 𝐶𝐶 𝐷𝐷 + 𝐶𝐶𝐷𝐷 ̅ ̅ � � � +(𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴)𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 = 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 ̅ ̅ � � � � � � +𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐵𝐵𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 = 𝑚𝑚12 + 𝑚𝑚13 + 𝑚𝑚14 + 𝑚𝑚15 + 𝑚𝑚0 + 𝑚𝑚1 + 𝑚𝑚2 + 𝑚𝑚3 + 𝑚𝑚2 + 𝑚𝑚6 + 𝑚𝑚10 + 𝑚𝑚14 = ∑ 𝑚𝑚(0 − 3,6,10,12 − 15) = ∏ 𝑀𝑀(4,5,7,8,9,11)

� ) + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 (c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐴𝐴𝐷𝐷 ̅ � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � � � + 𝐶𝐶𝐶𝐶) + 𝐴𝐴(𝐵𝐵� + 𝐵𝐵)𝐶𝐶𝐷𝐷 = 𝐴𝐴𝐵𝐵(𝐶𝐶 𝐷𝐷 + 𝐶𝐶̅ 𝐷𝐷 + 𝐶𝐶𝐷𝐷 ̅ ̅ � � � � � � � � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐷𝐷 = 𝑚𝑚8 + 𝑚𝑚9 + 𝑚𝑚10 + 𝑚𝑚11 + 𝑚𝑚10 + 𝑚𝑚14 + 𝑚𝑚5 = ∑ 𝑚𝑚(5,8 − 11,14) = ∏ 𝑀𝑀(0 − 4,6,7,12,13,15)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.41 Find the canonical SOP form for the logic functions of Problem 2.39. � (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷

� (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵� + 𝐶𝐶𝐷𝐷 ̅ ̅ � � + 𝐶𝐶𝐶𝐶) + 𝐴𝐴̅𝐵𝐵�(𝐶𝐶̅ 𝐷𝐷 � + 𝐶𝐶̅ 𝐷𝐷 + 𝐶𝐶𝐷𝐷 � + 𝐶𝐶𝐶𝐶) = 𝐴𝐴𝐴𝐴(𝐶𝐶 𝐷𝐷 + 𝐶𝐶 𝐷𝐷 + 𝐶𝐶𝐷𝐷 ̅ ̅ � � � +(𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐵𝐵 + 𝐴𝐴𝐴𝐴)𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 = 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � � + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 +𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 +𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � ) + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 (c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴(𝐵𝐵� + 𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐴𝐴𝐷𝐷 ̅ � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � � � + 𝐶𝐶𝐶𝐶) + 𝐴𝐴(𝐵𝐵� + 𝐵𝐵)𝐶𝐶𝐷𝐷 = 𝐴𝐴𝐵𝐵(𝐶𝐶 𝐷𝐷 + 𝐶𝐶̅ 𝐷𝐷 + 𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � � + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 = 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷

2.42 Expand the following function into canonical SOP form. 𝑓𝑓(𝑥𝑥1 , 𝑥𝑥2 , 𝑥𝑥3 ) = 𝑥𝑥1 𝑥𝑥̅3 + 𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 = 𝑥𝑥1 (𝑥𝑥̅2 + 𝑥𝑥2 )𝑥𝑥̅3 + (𝑥𝑥̅1 + 𝑥𝑥1 )𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 = 𝑥𝑥1 𝑥𝑥̅2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥̅1 𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 = 𝑥𝑥1 𝑥𝑥̅2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥̅1 𝑥𝑥2 𝑥𝑥̅3 + 𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 = 𝑚𝑚4 + 𝑚𝑚6 + 𝑚𝑚2 + 𝑚𝑚7 = ∑ 𝑚𝑚(2,4,6,7)

2.43 Expand the following function into canonical POS form.

� )(𝑋𝑋 + 𝑄𝑄� )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄)(𝑊𝑊 � + 𝑋𝑋�) 𝑓𝑓(𝑊𝑊, 𝑋𝑋, 𝑄𝑄) = (𝑄𝑄 + 𝑊𝑊 � � � + 𝑋𝑋�) = (𝑊𝑊 + 𝑄𝑄)(𝑋𝑋 + 𝑄𝑄 )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄)(𝑊𝑊 � � � � � + 𝑋𝑋� + 𝑄𝑄� 𝑄𝑄) = (𝑊𝑊 + 𝑋𝑋𝑋𝑋 + 𝑄𝑄)(𝑊𝑊 𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄 )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄)(𝑊𝑊 � + 𝑋𝑋� + 𝑄𝑄)(𝑊𝑊 � + 𝑋𝑋 + 𝑄𝑄)(𝑊𝑊 � + 𝑋𝑋 + 𝑄𝑄� )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄� )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄) = (𝑊𝑊 � + 𝑋𝑋� + 𝑄𝑄� )(𝑊𝑊 � + 𝑋𝑋� + 𝑄𝑄) ∙ (𝑊𝑊 � + 𝑋𝑋� + 𝑄𝑄)(𝑊𝑊 � + 𝑋𝑋 + 𝑄𝑄)(𝑊𝑊 � + 𝑋𝑋 + 𝑄𝑄� )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄� )(𝑊𝑊 + 𝑋𝑋 + 𝑄𝑄) = (𝑊𝑊 � + 𝑋𝑋� + 𝑄𝑄� ) ∙ (𝑊𝑊

= 𝑀𝑀6 ∙ 𝑀𝑀4 ∙ 𝑀𝑀5 ∙ 𝑀𝑀0 ∙ 𝑀𝑀0 ∙ 𝑀𝑀7 = ∏ 𝑀𝑀(0,1,4,5,6,7)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.44 Plot each of the following functions on Karnaugh maps. (a) f ( A, B, C ) = A B + B C + A C

(b) f ( A, B, C , D) = B C D + A BC + ABD

(c) f ( A, B, C , D, E ) = B C E + B CE + CD E + A BCD + ABC DE

2.45 Minimize each of the following functions using K-maps. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(3,5,6,7) = ∏ 𝑀𝑀(0,1,2,4) = 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴 = (𝐴𝐴 + 𝐵𝐵)(𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐶𝐶)

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,1,4,5,9,13,14,15) = ∏ 𝑀𝑀(2,3,5,7,8,10,11,12) � + 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵𝐷𝐷 � = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 � )(𝐵𝐵 + 𝐶𝐶̅ ) = (𝐴𝐴̅ + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷

(c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,1,2,8,9,10,11,12,13,14,15) = ∏ 𝑀𝑀(3,4,5,6,7) � = 𝐴𝐴 + 𝐵𝐵�𝐶𝐶̅ + 𝐵𝐵�𝐷𝐷 � �) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(3,4,6,9,11,13,15,18,25,26,27,29,31)

= ∏ 𝑀𝑀(0,1,2,5,7,8,10,12,14,16,17,19 − 24,28) = 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐸𝐸� + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷𝐷𝐷 + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷𝐸𝐸� = (𝐴𝐴̅ + 𝐶𝐶̅ + 𝐸𝐸)(𝐴𝐴̅ + 𝐵𝐵 + 𝐸𝐸� )(𝐴𝐴̅ + 𝐷𝐷 + 𝐸𝐸)(𝐴𝐴 + 𝐶𝐶 + 𝐸𝐸)(𝐴𝐴 + 𝐵𝐵� + 𝐸𝐸) ∙ (𝐵𝐵 + 𝐶𝐶̅ + 𝐸𝐸� )(𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)

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Digital Logic Circuit Analysis and Design, 2nd Edition

(e) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(1,5,8,10,12,13,14,15,17,21,24,26,31)

= ∏ 𝑀𝑀(0,2,3,4,6,7,9,11,16,18,19,20,22,23,25,27,28,29,30) � 𝐸𝐸 + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 = 𝐵𝐵𝐶𝐶̅ 𝐸𝐸� + 𝐵𝐵�𝐷𝐷 � )(𝐵𝐵 + 𝐸𝐸)(𝐵𝐵� + 𝐶𝐶 + 𝐸𝐸� )(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷 � + 𝐸𝐸)(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐸𝐸) = (𝐵𝐵 + 𝐷𝐷

2.46 Minimize the following functions containing don't-cares using the K-map. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(2,9,10,12,13) + 𝑑𝑑(1,5,14) � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ = 𝐶𝐶̅ 𝐷𝐷 + 𝐵𝐵�𝐶𝐶𝐷𝐷 ̅ � � � = 𝐶𝐶 𝐷𝐷 + 𝐵𝐵𝐶𝐶𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐷𝐷 � )(𝐴𝐴 + 𝐵𝐵�)(𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷) = (𝐶𝐶̅ + 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,3,6,7) + 𝑑𝑑(4,9,11) � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 = 𝐵𝐵�𝐷𝐷 = 𝐴𝐴̅(𝐵𝐵� + 𝐶𝐶)(𝐵𝐵 + 𝐷𝐷)

(c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(3,11,12,19,23,29) + 𝑑𝑑(5,7,13,27,28) � + 𝐶𝐶̅ 𝐷𝐷𝐷𝐷 + 𝐵𝐵�𝐷𝐷𝐷𝐷 = 𝐵𝐵𝐵𝐵𝐷𝐷 �) � + 𝐸𝐸)(𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 = (𝐵𝐵 + 𝐷𝐷)(𝐶𝐶 + 𝐷𝐷)(𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.47 Use the K-map to expand the following POS functions to canonical form. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐴𝐴 + 𝐵𝐵�)(𝐴𝐴̅ + 𝐵𝐵)(𝐵𝐵 + 𝐶𝐶̅ )

= ∏ 𝑀𝑀(1,2,3,4,5) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ )

� )(𝐴𝐴̅ + 𝐶𝐶) (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐴𝐴 + 𝐷𝐷

= ∏ 𝑀𝑀(1,3,5,7,8,9,12,13) � )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 ̅ ̅ ̅ ̅ � � � �) ∙ (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷

2.48 Minimize the following functions using a K-map. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(3,4,6,8,9,12,14)

� + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 = 𝐵𝐵𝐷𝐷 � � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷 �) = (𝐵𝐵 + 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚1,3,4,9,11,12,13,15,17,19,22,25,27,29,30,31) � 𝐸𝐸� + 𝐴𝐴𝐴𝐴𝐴𝐴𝐸𝐸� = 𝐶𝐶̅ 𝐸𝐸 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶 𝐷𝐷 � + 𝐸𝐸)(𝐴𝐴̅ + 𝐷𝐷 + 𝐸𝐸) = (𝐶𝐶 + 𝐸𝐸)(𝐵𝐵 + 𝐶𝐶̅ + 𝐸𝐸� )(𝐴𝐴 + 𝐷𝐷

2.49 Use K-maps to expand the following switching functions to canonical SOP form. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐴𝐴̅ + 𝐵𝐵)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐶𝐶) = ∑ 𝑚𝑚(0,2,3,7) = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴

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Digital Logic Circuit Analysis and Design, 2nd Edition

� (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐵𝐵� + 𝐴𝐴̅𝐶𝐶𝐶𝐶 + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷

= ∑ 𝑚𝑚(3,4,7,8,9,10,11,12) � + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � = 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷

� )(𝐴𝐴̅ + 𝐶𝐶) (c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐴𝐴 + 𝐵𝐵�)(𝐶𝐶 + 𝐷𝐷

= ∑ 𝑚𝑚(0,2,3,10,11,14,15) � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷

� (d) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝐴𝐴̅𝐸𝐸 + 𝐵𝐵𝐵𝐵𝐷𝐷

= ∑ 𝑚𝑚(1,3,5,7,9,11,13,14,15,30,31) � 𝐸𝐸 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷𝐷𝐷 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � 𝐸𝐸 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 � 𝐸𝐸 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 ̅ ̅ � � +𝐴𝐴𝐵𝐵𝐵𝐵𝐵𝐵𝐸𝐸 + 𝐴𝐴𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐸𝐸 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.50 Determine which of the following functions are equivalent.

f1 ( A, B, C , D) = AC + BD + AB D f 2 ( A, B, C , D) = AB D + AB + A BC f 3 ( A, B, C , D) = BD + AB D + ACD + ABC

f 4 ( A, B, C , D) = AC + AB C D + A BD + BC D f 5 ( A, B, C , D) = ( B + D )( A + B)( A + C )

𝑓𝑓1 = ∑ 𝑚𝑚(5,7,8,10,11,13,14,15) 𝑓𝑓2 = ∑ 𝑚𝑚(4,5,8,10,12,13,14,15) 𝑓𝑓3 = ∑ 𝑚𝑚(5,7,8,10,11,13,14,15) 𝑓𝑓4 = ∑ 𝑚𝑚(5,7,8,10,11,13,14,15) 𝑓𝑓5 = ∑ 𝑚𝑚(4,5,8,10,12,13,14,15)

Therefore, f1 = f3 = f4 and f2 = f5.

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.51 Use a K-map to find the following forms of the logic function below. (a) Canonical SOP form (b) Canonical POS form � 𝐸𝐸 + 𝐴𝐴𝐶𝐶̅ 𝐸𝐸 � 𝐸𝐸 + 𝐴𝐴𝐵𝐵�𝐷𝐷 + 𝐴𝐴̅𝐶𝐶 𝐷𝐷 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝐵𝐵𝐷𝐷 = ∑ 𝑚𝑚(5,9,13,17,18,19,22,23,25,27,29) = ∏ 𝑀𝑀(0 − 4,6,7,8, 10,11,12,14,15,16,20,21,24,26,28,30,31)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.52 Use K-maps to find the following functions. (a) 𝑓𝑓1 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) ∙ 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) (b) 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) + 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) (c) 𝑓𝑓3 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓1̅ (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) ∙ 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) (d) 𝑓𝑓4 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) ⊕ 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) where � 𝐵𝐵 � 𝐶𝐶 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴 � 𝐵𝐵 + 𝐵𝐵𝐷𝐷 � 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴

𝑓𝑓1 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) ∙ 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) � = 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐷𝐷 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) + 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐵𝐵 + 𝐴𝐴̅𝐶𝐶 𝑓𝑓3 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓1̅ (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) ∙ 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) � + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐷𝐷 (𝐴𝐴, (𝐴𝐴, 𝑓𝑓4 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑓𝑓𝛼𝛼 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) ⊕ 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) � + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.53 Use K-maps to generate all the prime implicants for the a two output logic circuit that realizes the following functions. � 𝐵𝐵 � 𝐶𝐶 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴 � � 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴𝐵𝐵 + 𝐵𝐵𝐷𝐷

�} 𝑃𝑃𝑃𝑃𝛼𝛼𝛼𝛼 = {𝐴𝐴̅𝐵𝐵𝐵𝐵, 𝐴𝐴𝐴𝐴𝐷𝐷 𝑃𝑃𝑃𝑃𝛼𝛼 = {𝐴𝐴𝐴𝐴, 𝐵𝐵𝐵𝐵, 𝐴𝐴̅𝐵𝐵� 𝐶𝐶, 𝐴𝐴̅𝐶𝐶𝐶𝐶} � , 𝐴𝐴̅𝐵𝐵} 𝑃𝑃𝑃𝑃𝛽𝛽 = {𝐵𝐵𝐷𝐷

2.54 Repeat 2.53 using the multiple-output Quine-McCluskey technique. Compare your prime implicant charts.

List 1 List 2 List 3 Minterm ABCD Flags Minterms ABCD Flags Minterms ABCD Flags 2 0010 α √ 2,3 001α PI5 4,5,6,7 01-β PI1 4 0100 β √ 4,5 010β √ 4,6,12,14 -1-0 β PI2 3 0011 α √ 4,6 01-0 β √ 5,7,13,15 -1-1 α PI3 5 0101 αβ √ 4,12 -100 β √ 12,13,14,15 11-α PI4 6 0110 β √ 3,7 0-11 α √ 12 1100 αβ √ 5,7 01-1 αβ PI6 7 0111 αβ √ 5,13 -101 α PI7 13 1101 α √ 6,7 011β √ 14 1110 αβ √ 6,14 -110 β √ 15 1111 α √ 12,13 110α √ 12,14 11-0 αβ PI8 7,15 -111 α √ 13,15 11-1 α √ 14,15 111α √

�} 𝑃𝑃𝑃𝑃𝛼𝛼𝛼𝛼 = {𝑃𝑃𝑃𝑃7 = 𝐴𝐴̅𝐵𝐵𝐵𝐵, 𝑃𝑃𝑃𝑃8 = 𝐴𝐴𝐴𝐴𝐷𝐷 𝑃𝑃𝑃𝑃𝛼𝛼 = {𝑃𝑃𝑃𝑃3 = 𝐴𝐴𝐴𝐴, 𝑃𝑃𝑃𝑃4 = 𝐵𝐵𝐵𝐵, 𝑃𝑃𝑃𝑃5 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶, 𝑃𝑃𝑃𝑃6 = 𝐴𝐴̅𝐶𝐶𝐶𝐶} � , 𝑃𝑃𝑃𝑃2 = 𝐴𝐴̅𝐵𝐵 } 𝑃𝑃𝑃𝑃𝛽𝛽 = {𝑃𝑃𝑃𝑃1 = 𝐵𝐵𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.55 Minimize the following functions using the Quine--McCluskey method. (a) f ( A, B, C , D) = ∑ m(0,2,4,5,7,9,11,12) List 1 ABCD 0000 0010 0100 0101 1001 1100 0111 1011

Minterm 0 2 4 5 9 12 7 11

√

*PI1 PI2 PI3 *PI4 *PI5 *PI6

0 X X

Covered √ √ √ √ √ √ √ √

Minterms 0,2 0,4 4,5 4,12 5,7 9,11

List 2 ABCD 00-0 0-00 010-100 10010-0

√

√

√

2

⊗

√

4

5

X X X

X X

√

7

9

Covered PI1 PI2 PI3 PI4 PI5 PI6

√

√

11

12

⊗ ⊗ ⊗

⊗

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃6 � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵� 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 (b) f ( A, B, C , D, E ) = ∑m(0,1,2,7,9,11,12,23,27,28) Minterm 0 1 2 9 12 7 11 28 23 27

List 1 ABCDE 00000 00001 00010 01001 01100 00111 01011 11100 10111 11011

Covered √ √ √ √ √ √ √ √ √ √

Minterms 0,1 0,2 1,9 9,11 12,28 7,23 11,27

List 2 ABCDE 0000000-0 0-001 010-1 -1100 -0111 -1011

Covered PI1 PI2 PI3 PI4 PI5 PI6 PI7

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Digital Logic Circuit Analysis and Design, 2nd Edition

√

0 X X

PI1 *PI2 PI3 PI4 *PI5 *PI6 *PI7

1 X X

√

2

√

7

⊗

√

9

11

X X

X

√

12

√

23

√

27

⊗ ⊗

X

√

28

⊗ ⊗ ⊗

Choose PO3 to cover minterms 1 and 9. 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃6 + 𝑃𝑃𝑃𝑃7 + 𝑃𝑃𝑃𝑃3 � 𝐸𝐸� + 𝐵𝐵𝐵𝐵𝐷𝐷 � 𝐸𝐸� + 𝐵𝐵� 𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷

2.56 Use the Quine-McCluskey method to minimize the following functions with don't-cares. (a) f ( A, B, C , D) = ∑m(0,6,9,10,13) + d (1,3,8) List 1 List 2 List 3 Minterm ABCD Minterms ABCD Minterms ABCD 0 0000 √ 0,1 000- √ 0,1,8,9 -00- PI1 1 0001 √ 0,8 -000 √ 8 1000 √ 1,3 00-1 PI2 3 0011 √ 1,9 -001 √ 6 0110 PI5 8,9 100- √ 9 1001 √ 8,10 10-0 PI3 10 1010 √ 9,13 1-01 PI4 13 1101 √ √

*PI1 PI2 *PI3 *PI4 *PI5

0

⊗

√

6

√

9 X

X

√

10

√

13

⊗ ⊗

⊗

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃5 � + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 � = 𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) f ( A, B, C , D) = ∑m(1,4,7,10,13) + d (5,14,15) List 1 Minterm ABCD 1 0001 4 0100 5 0101 10 1010 7 0111 13 1101 14 1110

List 2 Minterms ABCD √ 1,5 0-01 √ 4,5 010√ 5,7 01-1 √ 5,13 -101 √ 10,14 10-0 √ 7,15 -111 √ 13,15 11-1 14,15 111√

*PI1 *PI2 *PI3 *PI4 PI5

1

√

4

√

7

⊗

PI2 PI3 √ √ PI4 √ √ PI5 √

10

List 3 Minterms ABCD 5,7,13,15 -1-1 PI1

√

13

⊗

⊗ ⊗ ⊗

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃4 � = 𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐷𝐷 2.57 Minimize the following multiple-output functions using the Q--M technique. (a) 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,1,2,9,15)

𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,8,12,15)

List 1 List 2 Minterm ABCD Flags Minterms ABCD Flags 0 0000 αβ √ 0,1 000α PI1 1 0001 α √ 0,2 00-0 αβ PI2 2 0010 αβ √ 0,8 -000 β PI3 8 1000 β √ 1,9 -100 α PI4 9 1001 α √ 8,12 1-00 β PI5 12 1100 β √ 15 1111 αβ PI6

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Digital Logic Circuit Analysis and Design, 2nd Edition

√

PI1 α *PI2 αβ PI3 β *PI4 α *PI5 β *PI6 αβ

0 X X

fα √

√

1 X

√

2

√

9

√

15

⊗ X

⊗

fβ √

√

0

2

X X

⊗

√

8

12

√

15

X X

⊗

⊗

⊗

𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃6 � + 𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃6 � + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷

(b) 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(3,7,9,14) + 𝑑𝑑(1,4,6,11) 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(6,7,12) + 𝑑𝑑(3,14) List 1 List 2 List 3 Minterm ABCD Flags Minterms ABCD Flags Minterms ABCD Flags 1 0001 α √ 1,3 001α √ 1,3,9,11 -0-1 α PI1 4 0100 α √ 1,9 -001 α √ 3 0011 αβ √ 4,6 01-0 α PI2 6 0110 αβ √ 3,7 0-11 αβ PI3 9 1001 α √ 3,11 -011 α √ 12 1100 β √ 6,7 011αβ PI4 7 0111 αβ √ 6,14 -110 αβ PI5 11 1011 α √ 9,11 10-1 α √ 14 1110 αβ √ 12,14 11-0 β PI6 fα √

*PI1 α PI2 α PI3 αβ PI4 αβ *PI5 αβ *PI6 β

3 X

7

X

X X

fβ √

9

⊗

√

14

⊗

6

X X

7

√

12

X X

⊗

Choose PI4 to cover minterms 7 in fα and minterms 6 and 7 in fβ. 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃4 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 = 𝐵𝐵� 𝐷𝐷 + 𝐵𝐵𝐵𝐵𝐷𝐷 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃6 + 𝑃𝑃𝑃𝑃4 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 = 𝐴𝐴𝐴𝐴𝐷𝐷 72 material is protected under all copyright laws as they currently exist. © 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Digital Logic Circuit Analysis and Design, 2nd Edition

2.58 Apply the covering procedure to obtain a minimum list of prime implicants for the function f ( A, B, C , D) = ∑m(1,3,4,6,7,9,13,15) List 1 Minterm ABCD Covered 1 0001 √ 4 0100 √ 3 0011 √ 6 0110 √ 9 1001 √ 7 0111 √ 13 1101 √ 15 1011 √ 1 X X

PI1 PI2 *PI3 PI4 PI5 PI6 PI7 PI8

3 X X

√ 4

√ 6

⊗

X X

Minterms 1,3 1,9 4,6 3,7 6,7 9,13 7,15 13,15 7

9

X X X

PI1 PI2 PI4 PI5 PI6 PI7 PI8

3 X

7

X

X X

9

13

15

X X

X

X X

X X

13

Covered PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8 15

X

X

X X

Remove essential prime implicant PI3 and columns 1 and 3.

Then, row PI4 covers row PI5, so remove row PI5.

1 X X

List 2 ABCD 00-1 -001 01-0 0-11 0111-01 -111 11-1

PI1 PI2 PI4 PI6 PI7 PI8

1 X X

X X

3 X

7

X

X X

9

13

15

X X

X X

X X

The table now contains a cycle. Let us select PI1, removing row PI1 and columns 1 and 3.

Then, row PI6 covers PI2 and row PI7 covers PI4, so we can remove rows PI2 and PI4.

PI2 PI4 PI6 PI7 PI8

7

X X

9 X

13

X

X X

15

X X

PI6 PI7 PI8

7

X

9 X

13 X X

15 X X

From the resulting table, we select PI6 to cover minterms 9 and 13, and PI7 to cover minterms 7 and 15.

The minimum set of prime implicants is: {PI3, PI1, PI6, PI7}.

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.59 Plot the following functions on the K-map and determine the minterm lists. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐵𝐵� + 𝐴𝐴𝐶𝐶̅ = ∑ 𝑚𝑚(0,1,4,5,6)

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐴𝐴̅𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵 + 𝐵𝐵𝐵𝐵 = ∑ 𝑚𝑚(0,2,3,7)

2.60 Plot the following functions on the K-map and determine the minterm lists. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐴𝐴̅𝐵𝐵 + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� = ∑ 𝑚𝑚(2,3,4,5,7)

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵 + 𝐵𝐵𝐶𝐶̅ = ∑ 𝑚𝑚(1,2,3,5,6)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.61 Plot the following functions on the K-map and determine the minterm lists. � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐷𝐷 � (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 = ∑ 𝑚𝑚(2,3,5,8,12,13,14)

� + 𝐴𝐴𝐴𝐴𝐴𝐴 (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐷𝐷 = ∑ 𝑚𝑚(0,1,3,11,12,14,15)

2.62 Plot the following functions on the K-map and determine the minterm lists. � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵�𝐷𝐷 (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐷𝐷 = ∑ 𝑚𝑚(3,4,5,6,9,11,13)

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Digital Logic Circuit Analysis and Design, 2nd Edition

� + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴 (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 = ∑ 𝑚𝑚(0,1,5,7,8,14,15)

2.63 Plot the following functions on the K-map and determine the minterm lists. � + 𝐵𝐵𝐵𝐵𝐷𝐷 � 𝐸𝐸 + 𝐴𝐴̅𝐵𝐵𝐷𝐷 � 𝐸𝐸� + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸� + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐸𝐸� (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐵𝐵�𝐷𝐷𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 = ∑ 𝑚𝑚(2,3,7,8,12,13,18,19,23,24,26,29)

� + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸 (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝐴𝐴̅𝐵𝐵�𝐷𝐷𝐸𝐸� + 𝐴𝐴̅𝐵𝐵𝐷𝐷

= ∑ 𝑚𝑚(2,6,8,9,11,12,13,15,16,17,25,27,29,31)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.64 Plot the following functions on the K-map and determine the maxterm lists. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐴𝐴 + 𝐵𝐵)(𝐵𝐵� + 𝐶𝐶) = ∏ 𝑀𝑀(0,1,2,6)

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐵𝐵�(𝐴𝐴̅ + 𝐶𝐶)

= ∏ 𝑀𝑀(2,3,4,6,7)

2.65 Plot the following functions on the K-map and determine the maxterm lists. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = 𝐴𝐴(𝐵𝐵 + 𝐶𝐶̅ ) = ∏ 𝑀𝑀(0,1,2,3,5)

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵�) = ∏ 𝑀𝑀(0,2,3,4)

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.66 Plot the following functions on the K-map and determine the maxterm list. � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷)(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐶𝐶 + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷) (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐶𝐶̅ + 𝐷𝐷 = ∏ 𝑀𝑀(0,3,7,8,11,12,14,15)

� )(𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷 � )(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 �) (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐵𝐵� + 𝐶𝐶)(𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷 = ∏ 𝑀𝑀(1,3,4,5,11,12,13)

2.67 Plot the following functions on the K-map and determine the maxterm list. � )(𝐴𝐴 + 𝐵𝐵�)(𝐵𝐵� + 𝐷𝐷)(𝐴𝐴̅ + 𝐶𝐶 + 𝐷𝐷) (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐴𝐴 + 𝐷𝐷 = ∏ 𝑀𝑀(1,3,4,5,6,7,8,12,14)

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� )(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷) (b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = (𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷 = ∏ 𝑀𝑀(2,4,5,10,13,14,15)

2.68 Plot the following function on the K-map and determine the maxterm list.

� )(𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐷𝐷 + 𝐸𝐸)(𝐵𝐵� + 𝐷𝐷 + 𝐸𝐸� ) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = (𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 = ∏ 𝑀𝑀(0,1,6,7,8,9,12,13,16,20,22,23,25,29)

2.69 Use the K-map to simplify the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(1,5,6,7) = 𝐴𝐴𝐴𝐴 + 𝐵𝐵�𝐶𝐶

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(0,1,2,3,4,5) = 𝐴𝐴̅ + 𝐵𝐵�

2.70 Use the K-map to simplify the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(0,2,3,5) = 𝐴𝐴̅𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑ 𝑚𝑚(0,3,4,6,7)

= 𝐵𝐵�𝐶𝐶̅ + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴 - Option 1 = 𝐵𝐵�𝐶𝐶̅ + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐶𝐶̅ - Option 2

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2.71 Find MSOP and MPOS forms of the following functions using a K-map. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,5,7,8,10,13,15) � = 𝐵𝐵𝐵𝐵 + 𝐵𝐵�𝐷𝐷 � �) = (𝐵𝐵 + 𝐷𝐷)(𝐵𝐵 + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,3,4,5,6,7,9,11,12,13,14,15) = 𝐵𝐵 + 𝐷𝐷 = (𝐵𝐵 + 𝐷𝐷)

2.72 Use the K-map to simplify the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,4,5,7,8,10,11,15)

� + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶 - Option 1 = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 ̅ ̅ � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵�𝐷𝐷 � - Option 2 = 𝐴𝐴𝐶𝐶 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,4,5,6,9,11,15)

� + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵�𝐷𝐷 - Option 1 = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 - Option 2 = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐷𝐷

2.73 Find MSOP and MPOS forms of the following functions using a K-map. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,2,5,6,7,9,11,15) � + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐷𝐷 = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐶𝐶 𝐷𝐷 ̅ �) = (𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴̅ + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,1,2,5,12,13,14,15)

� + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵�𝐷𝐷 �) = (𝐴𝐴̅ + 𝐵𝐵)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.74 Use the K-map to simplify the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,4,5,6,8,9,11,13,15) � + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ = 𝐴𝐴𝐴𝐴 + 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,2,4,5,6,9,12,14)

� + 𝐵𝐵𝐷𝐷 � + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 - Option 1 = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐶𝐶 𝐷𝐷 � + 𝐵𝐵𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ - Option 2 = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐶𝐶 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.75 Find MSOP and MPOS forms of the following functions using a K-map. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(0,4,6,7,8,11,15,20,22,24,26,27,31)

� 𝐸𝐸� + 𝐵𝐵�𝐶𝐶𝐸𝐸� + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐸𝐸� + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐶𝐶 – Option 1 = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 ̅ ̅ � = 𝐴𝐴𝐶𝐶 𝐷𝐷 𝐸𝐸� + 𝐵𝐵�𝐶𝐶𝐸𝐸� + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐸𝐸� + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷𝐷𝐷 – Option 2 � )(𝐵𝐵� + 𝐶𝐶̅ + 𝐸𝐸)(𝐴𝐴̅ + 𝐵𝐵 + 𝐸𝐸� )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷 � + 𝐸𝐸) = (𝐷𝐷 + 𝐸𝐸� )(𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(2,7,10,12,13,22,23,26,27,28,29)

� + 𝐵𝐵�𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷𝐸𝐸� + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 = 𝐵𝐵𝐵𝐵𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷 � + 𝐸𝐸) = (𝐶𝐶 + 𝐷𝐷)(𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶 + 𝐸𝐸� )(𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷

2.76 Use the K-map to simplify the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(1,3,8,9,11,12,14,17,19,20,22,24,25,27) � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐸𝐸� = 𝐶𝐶̅ 𝐸𝐸 + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐸𝐸� + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(0,7,8,10,13,15,16,24,28,29,31)

� 𝐸𝐸� + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐸𝐸� + 𝐴𝐴𝐴𝐴𝐷𝐷 � 𝐸𝐸� - Option 1 = 𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸� + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐸𝐸� + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � - Option 2 = 𝐶𝐶̅ 𝐷𝐷

2.77 Find MSOP and MPOS forms of the following functions using a K-map. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(1,2,5,6,13,15,16,18,22,24,29)

� 𝐸𝐸 + 𝐵𝐵�𝐷𝐷𝐸𝐸� + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐵𝐵𝐵𝐵𝐷𝐷 � 𝐸𝐸 + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸� = 𝐴𝐴̅𝐵𝐵�𝐷𝐷 ̅ � � = (𝐴𝐴 + 𝐷𝐷 + 𝐸𝐸)(𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸)(𝐵𝐵 + 𝐷𝐷 + 𝐸𝐸 )(𝐵𝐵� + 𝐷𝐷 + 𝐸𝐸� )(𝐵𝐵� + 𝐶𝐶 + 𝐸𝐸� ) �) ∙ (𝐴𝐴̅ + 𝐵𝐵 + 𝐸𝐸� )(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(1,7,9,12,14,15,16,23,24,28,30)

� 𝐸𝐸 + 𝐵𝐵�𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐵𝐵𝐵𝐵𝐸𝐸� + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸� + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐵𝐵 - Option 1 = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸 + 𝐵𝐵�𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐵𝐵𝐵𝐵𝐸𝐸� + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸� + 𝐴𝐴̅𝐶𝐶𝐶𝐶𝐶𝐶 - Option 2 = 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 � � = (𝐴𝐴 + 𝐶𝐶 + 𝐸𝐸)(𝐶𝐶 + 𝐷𝐷 )(𝐵𝐵 + 𝐷𝐷 + 𝐸𝐸)(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷)(𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸� ) ∙ (𝐴𝐴̅ + 𝐵𝐵� + 𝐸𝐸� )(𝐴𝐴̅ + 𝐷𝐷 + 𝐸𝐸� )

2.78 Use the K-map to simplify the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(0,5,10,11,13,15,16,18,29,31)

� 𝐸𝐸� + 𝐴𝐴̅𝐶𝐶 𝐷𝐷 � 𝐸𝐸 + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐸𝐸� = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(4,5,7,8,9,12,13,16,18,23,24,25,28,29) � + 𝐵𝐵𝐷𝐷 � + 𝐵𝐵�𝐶𝐶𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐸𝐸� = 𝐴𝐴̅𝐶𝐶 𝐷𝐷

2.79 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(0,2,3,4) = (𝐴𝐴 + 𝐵𝐵�)(𝐵𝐵 + 𝐶𝐶)

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(0,3,4,7)

= (𝐵𝐵 + 𝐶𝐶)(𝐵𝐵� + 𝐶𝐶̅ )

2.80 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(0,1,4,5,6) = 𝐵𝐵(𝐴𝐴̅ + 𝐶𝐶)

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(1,2,3,6)

= (𝐴𝐴 + 𝐶𝐶̅ )(𝐵𝐵� + 𝐶𝐶)

2.81 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(1,2,5,7) = (𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(1,2,3,4)

= (𝐴𝐴 + 𝐶𝐶̅ )(𝐴𝐴 + 𝐵𝐵�)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)

2.82 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(0,1,3,4,6,7) = (𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵�) - Option 1 = (𝐴𝐴 + 𝐵𝐵)(𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐶𝐶) - Option 2

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∏ 𝑀𝑀(2,3,5,7)

= (𝐴𝐴 + 𝐵𝐵�)(𝐴𝐴̅ + 𝐶𝐶̅ )

2.83 Find the MSOP and MPOS forms of the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,1,5,7,8,10,11,15)

� )(𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ ) - Option 1 = (𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐷𝐷) - Option 2 = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,1,2,4,6,7,8,10,14)

= (𝐴𝐴 + 𝐷𝐷)(𝐶𝐶̅ + 𝐷𝐷)(𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ )

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.84 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(2,3,4,5,7,12,13)

� ) - Option 1 = (𝐵𝐵� + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷 ̅ � � � ) - Option 2 = (𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 )(𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(1,2,5,7,11,13,15)

� )(𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷 � ) (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷) = (𝐵𝐵� + 𝐷𝐷

2.85 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,2,4,5,6,9,11,13) � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐷𝐷 �) = (𝐴𝐴 + 𝐷𝐷)(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(1,3,4,5,6,9,11,12,13)

� )(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷) = (𝐵𝐵� + 𝐶𝐶)(𝐵𝐵 + 𝐷𝐷

2.86 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,1,5,7,9,11,12,14)

� )(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵 + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶))(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(3,4,5,7,8,9,10)

� )(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐷𝐷) = (𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

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2.87 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∏ 𝑀𝑀(3,4,6,13,15,16,19,24,29,31)

� + 𝐸𝐸� )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶̅ + 𝐸𝐸)(𝐵𝐵� + 𝐶𝐶̅ + 𝐸𝐸� )(𝐴𝐴̅ + 𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸) = (𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∏ 𝑀𝑀(1,4,7,9,15,17,20,22,25,30)

� + 𝐸𝐸� )(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷 � + 𝐸𝐸) = (𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸� )(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

2.88 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∏ 𝑀𝑀(0,1,2,5,7,8,10,15,17,21,22,24,26,29)

� + 𝐸𝐸� )(𝐵𝐵� + 𝐶𝐶 + 𝐸𝐸) = (𝐴𝐴 + 𝐶𝐶 + 𝐸𝐸)(𝐵𝐵 + 𝐷𝐷 + 𝐸𝐸� )(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷 ̅ ̅ ̅ ̅ � � ∙ (𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸 )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸)

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∏ 𝑀𝑀(0,2,4,6,9,11,13,15,16,19,20,25,27,29,31)

� + 𝐸𝐸� ) = (𝐵𝐵� + 𝐸𝐸� )(𝐴𝐴 + 𝐵𝐵 + 𝐸𝐸)(𝐵𝐵 + 𝐷𝐷 + 𝐸𝐸)(𝐴𝐴̅ + 𝐶𝐶 + 𝐷𝐷

2.89 Find the minimum SOP form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,2,7,12,15) + 𝑑𝑑(5,9,10,11,13) � + 𝐵𝐵𝐵𝐵 = 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐵𝐵�𝐶𝐶𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,5,15) + 𝑑𝑑(8,9,12,13) � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵�𝐷𝐷

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2.90 Determine the minimum SOP form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(4,7,9,15) + 𝑑𝑑(1,2,3,6) � + 𝐵𝐵𝐵𝐵𝐵𝐵 = 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,3,4,5) + 𝑑𝑑(8,9,10,11) � + 𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ = 𝐵𝐵�𝐷𝐷

2.91 Find the minimum SOP form for the following function.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(7,9,12,13,19,22) + 𝑑𝑑(0,3,20,25,27,28,29) � + 𝐵𝐵𝐷𝐷 � 𝐸𝐸 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐸𝐸� + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷𝐷𝐷 - Option 1 = 𝐵𝐵𝐵𝐵𝐷𝐷 � � = 𝐵𝐵𝐵𝐵𝐷𝐷 + 𝐵𝐵𝐷𝐷 𝐸𝐸 + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐸𝐸� + 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷𝐷𝐷 - Option 2

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2.92 Determine the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(4,7,9,11,12) ∙ 𝐷𝐷(0,1,2,3) � )(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷 �) = (𝐵𝐵 + 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,3,7,12) ∙ 𝐷𝐷(2,10,11,14)

� )(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷) = (𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

2.93 Find the minimum POS form for the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(3,4,10,13,15) ∙ 𝐷𝐷(6,7,14)

� )(𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐶𝐶̅ + 𝐷𝐷) = (𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

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(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∏ 𝑀𝑀(0,7,11,13) ∙ 𝐷𝐷(1,2,3)

� )(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 � )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 �) = (𝐴𝐴 + 𝐵𝐵)(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷

2.94 Find the minimum POS form for the following function.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∏ 𝑀𝑀(0,5,6,9,21,28,31) ∙ 𝐷𝐷(2,12,13,14,15,25,26) � + 𝐸𝐸)(𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐸𝐸)(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸� )(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷 ̅ � � � � � ∙ (𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸 )(𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷 + 𝐸𝐸 ) - Option 1 � + 𝐸𝐸)(𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶 + 𝐸𝐸)(𝐵𝐵 + 𝐶𝐶̅ + 𝐷𝐷 + 𝐸𝐸� )(𝐴𝐴 + 𝐶𝐶̅ + 𝐷𝐷 � + 𝐸𝐸� )(𝐵𝐵� + 𝐶𝐶 + 𝐷𝐷 + 𝐸𝐸� ) - Option 2 ∙ (𝐵𝐵� + 𝐶𝐶̅ + 𝐷𝐷

2.95 Use the Quine--McCluskey method to minimize the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,3,5,7,11,12,14,15) List 1 Minterm ABCD 0 0000 2 0010 3 0011 5 0101 12 1100 7 0111 11 1011 14 1110 15 1111

List 2 Minterms ABCD √ 0,2 00-0 √ 2,3 001√ 3,7 0-11 √ 3,11 -011 √ 5,7 01-1 √ 12,14 11-0 √ 7,15 -111 √ 11,15 1-11 √ 14,15 111-

PI2 PI3 √ √ PI4 PI5 √ √ PI6

List 3 Minterms ABCD 3,7,11,15 --11 PI1

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Digital Logic Circuit Analysis and Design, 2nd Edition

√

*PI1 *PI2 PI3 *PI4 *PI5 PI6

√

0

2

⊗

X X

√

√

3 X X

√

5

7 X

⊗

X

√

11

⊗

√

√

12

14

⊗

X X

√

15 X

X

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃5 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐷𝐷 � = 𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵� 𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,1,6,8,9,13,14,15) List 1 Minterm ABCD 0 0000 1 0001 8 1000 6 0110 9 1001 13 1101 14 1110 15 1111 √

*PI1 *PI2 PI3 PI4 PI5

0

⊗

√

1

⊗

List 2 Minterms ABCD √ 0,1 000√ 0,8 -000 √ 1,9 -001 √ 8,9 100√ 6,14 -110 √ 9,13 1-01 √ 13,15 11-1 √ 14,15 111√

6

⊗

√

8

⊗

√

9 X

13

List 3 Minterms ABCD 0,1,8,9 -00- PI1

√ √ √ √ PI2 PI3 PI4 PI5 √

14

15

X X

X X X

X X

PI3 PI4 PI5

13 X X

15 X X

Essential: PI1 and PI2. After removing these rows and columns, PI4 covers the remaining two minterms.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃4 � + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐵𝐵� 𝐶𝐶̅ + 𝐵𝐵𝐵𝐵𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

2.96 Use the Quine--McCluskey method to minimize the following functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,4,5,6,8,9,10,12,14) List 1 Minterm ABCD 1 0000 4 0100 8 1000 5 0101 6 0110 9 1001 10 1010 12 1100 14 1110

*PI1 *PI2 PI3 PI4 PI5 PI6

1

√

4 X

X X

List 2 Minterms ABCD √ 1,5 0-01 √ 1,9 -001 √ 4,5 010√ 4,6 01-0 √ 4,12 -100 √ 8,9 100√ 8,10 10-0 √ 8,12 1-00 √ 6,14 -110 10,14 1-10 12,14 11-0

5

√

6

⊗

√

8 X

X X

9

PI3 PI4 PI5 √ √ PI6 √ √ √ √ √ √

10

⊗

List 3 Minterms ABCD 4,6,12,14 -1-0 PI1 8,10,12,14 1--0 PI2

√

12 X X

√

14 X X

X

X

X

PI3 PI4 PI5 PI6

1 X X

5 X

9 X

X

X

X

Essential: PI1 and PI2. Remove them from the table.

Row dominance: remove PI5 and PI6. Then select PI3 and PI4.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃4 � + 𝐴𝐴𝐷𝐷 � + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷 + 𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 = 𝐵𝐵𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(4,5,6,8,11,13,15) Minterm 4 8 5 6 11 13 15

List 1 ABCD 0100 1000 0101 0110 1011 1101 1111

Covered √ PI6 √ √ √ √ √

Minterms 4,5 4,6 5,13 11,15 13,15

List 2 ABCD 01001-0 -101 1-11 11-1

Covered PI1 PI2 PI3 PI4 PI5

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Digital Logic Circuit Analysis and Design, 2nd Edition

√

PI1 *PI2 PI3 *PI4 PI5 *PI6

4 X X

√

5 X

√

6

8

√

11

13

⊗

X

√

15

X

⊗ ⊗

PI1 PI3 PI5

X X

X

5 X X

13 X X

Essential: PI2, PI4, PI6. PI3 covers the remaining two minterms.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃6 + 𝑃𝑃𝑃𝑃3 � + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 � + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷 = 𝐴𝐴̅𝐵𝐵𝐷𝐷

2.97 Minimize the following functions using the Quine-McCluskey method. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,3,6,7,8,9,12,14) Minterm 1 8 3 6 9 12 7 14

PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8

List 1 ABCD 0001 1000 0011 0110 1001 1100 0111 1110

1 X X

Covered √ √ √ √ √ √ √ √

Minterms 1,3 1,9 8,9 8,12 3,7 6,7 6,14 12,14

List 2 ABCD 00-1 -001 1001-00 0-11 011-110 11-0

3 X

7

9

6

8 X X

X

X X

X X

12

Covered PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8

14

X

X X X

X X

Cycle: Arbitrarily choose PI1 and remove that row.

100 material is protected under all copyright laws as they currently exist. © 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Digital Logic Circuit Analysis and Design, 2nd Edition

PI2 PI3 PI4 PI5 PI6 PI7 PI8

6

7

8 X X

X X

9 X X

12

14

X

X X X

X X

Row dominance: remove PI2 and PI5, making PI3 and PI6 essential.

After removing these four rows, PI8 covers the remaining minterms.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃6 + 𝑃𝑃𝑃𝑃8 � = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷 + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(0,2,4,5,10,11,13,15) Minterm 0 2 4 5 10 11 13 15

PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8

List 1 ABCD 0000 0010 0100 0101 1010 1011 1101 1111

0 X X

Covered √ √ √ √ √ √ √ √

Minterms 0,2 0,4 2,10 4,5 5,13 10,11 11,15 13,15

List 2 ABCD 00-0 0-00 -010 010-101 1011-11 11-1

2 X

5

11

X

4 X X

X X

10

13

Covered PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8

15

X

X

X X

X X

X X

Cycle: Arbitrarily choose PI1 and remove that row.

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Digital Logic Circuit Analysis and Design, 2nd Edition

PI2 PI3 PI4 PI5 PI6 PI7 PI8

4 X

5

X

X X

10

11

13

15

X

X

X X

PI5 PI7 PI8

13 X X

15 X X

X X

X X

Row dominance: remove PI2 and PI3, making PI4 and PI6 essential.

After removing these four rows, PI8 covers the remaining minterms.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃6 + 𝑃𝑃𝑃𝑃8 � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵� 𝐷𝐷

2.98 Use the Quine-McCluskey method to minimize the following functions with don't-cares. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(1,6,7,9,12) + 𝑑𝑑(8,11,15) Minterm 1 8 6 9 12 7 11 15

List 1 ABCD 0001 1000 0011 0110 1001 1100 0111 1110 √

*PI1 PI2 *PI3 *PI4 PI5 PI6 PI7

1

⊗

Covered √ √ √ √ √ √ √ √

Minterms 1,9 8,9 8,12 6,7 9,11 7,15 11,15

√

√

√

6

7

⊗

X X

9 X X

List 2 ABCD -001 1001-00 01110-1 -111 1-11

Covered PI1 PI2 PI3 PI4 PI5 PI6 PI7

√

12

⊗

X

Essential: PI1, PI3, PI4. These cover all minterms.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃4 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵 = 𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐶𝐶̅ 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ∑ 𝑚𝑚(7,8,13,15) + 𝑑𝑑(3,4,10,14) Minterm 4 8 3 10 7 13 14 15

*PI1 PI2 PI3 PI4 *PI5 PI6 PI7

List 1 ABCD 0100 1000 0011 1010 0111 1101 1110 1111

7 X X

Covered PI7 √ √ √ √ √ √ √

Minterms 8,10 3,7 10,14 7,15 13,15 14,15

√

√

8

⊗

√

13

15

⊗

X X X

List 2 ABCD 10-0 0-11 1-10 -111 11-1 111-

Covered PI1 PI2 PI3 PI4 PI5 PI6

Essential: PI1 and PI5. Complete the cover with PI2 or PI4.

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃2 � + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐶𝐶𝐶𝐶 = 𝐴𝐴𝐵𝐵� 𝐷𝐷 or 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃4 � + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵𝐵𝐵 = 𝐴𝐴𝐵𝐵� 𝐷𝐷

2.99 Minimize the following functions with don't-cares using the Quine-McCluskey method. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(5,7,11,12,27,29) + 𝑑𝑑(14,20,21,22,23) List 1 List 2 List 3 Minterm ABCDE Minterms ABCDE Minterms ABCDE 5 00101 √ 5,7 001-1 √ 5,7,21,23 -01-1 PI1 12 01100 √ 5,21 -0101 √ 20,21,22,23 101-- PI2 20 10100 √ 12,14 011-0 PI3 7 00111 √ 20,21 1010- √ 11 01011 √ 20,22 101-0 √ 14 01110 √ 7,23 -0111 √ 21 10101 √ 11,27 -1011 PI4 22 10110 √ 21,23 101-1 √ 23 10111 √ 21,29 1-101 PI5 27 11011 √ 22,23 1011- √ 29 11101 √

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Digital Logic Circuit Analysis and Design, 2nd Edition

√ 5 ⊗

√ 7 ⊗

√ 11

√ 12

√ 27

√ 29

*PI1 PI2 *PI3 ⊗ *PI4 ⊗ ⊗ *PI5 ⊗ Essential: PI1, PI3, PI4, PI5. These cover all specified minterms. 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃5 � 𝐸𝐸 = 𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐸𝐸� + 𝐵𝐵𝐶𝐶̅ 𝐷𝐷𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐷𝐷

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(1,4,6,9,14,17,22,27,28) + 𝑑𝑑(12,15,20,30,31)

List 1 List 2 List 3 Minterm ABCDE Minterms ABCDE Minterms ABCDE 1 00001 √ 1,9 0-001 PI3 4,6,20,22 -01-0 √ 4 00100 √ 1,17 -0001 PI4 4,6,12,14 0-1-0 √ 6 00110 √ 4,6 001-0 √ 4,12,20,28 --100 √ 9 01001 √ 4,12 0-100 √ 6,14,22,30 --110 √ 12 01100 PI6 4,20 -0100 √ 12,14,28,30 -11-0 √ 17 10001 √ 6,14 0-110 √ 20,22,28,30 1-1-0 √ 20 10100 √ 6,22 -0110 √ 14,15,30,31 -111- PI2 14 01110 √ 12,14 011-0 √ 22 10110 √ 12,28 -1100 √ 28 11100 √ 20,22 101-0 √ 15 01111 √ 20,28 1-100 √ 27 11011 √ 14,15 0111- √ List 4 30 11110 √ 14,30 -1110 √ Minterms ABCDE 31 11111 √ 22,30 1-110 √ 4,6,12,14,20,22,28,30 --1-0 PI1 28,30 111-0 √ 15,31 -1111 √ 27,31 11-11 PI5 30,31 1111- √

*PI1 PI2 *PI3 *PI4 *PI5 PI6

√ 1 X X

√ 4 ⊗

√ 6 ⊗

√ 9

⊗

√ 14 X X

√ 17

√ 22 ⊗

√ 27

√ 28 ⊗

⊗ ⊗

All prime implicants except PI2 and PI6 are essential, and cover all minterms. 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃3 + 𝑃𝑃𝑃𝑃4 + 𝑃𝑃𝑃𝑃5 � 𝐸𝐸 + 𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � 𝐸𝐸 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐶𝐶𝐸𝐸� + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷

104 material is protected under all copyright laws as they currently exist. © 2020 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Digital Logic Circuit Analysis and Design, 2nd Edition

2.100 Minimize the following multiple-output function using the Quine-McCluskey method. 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(0,2,8,9,20,24) + 𝑑𝑑(4,10,14,26,30) 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = ∑ 𝑚𝑚(3,4,8,11,24) + 𝑑𝑑(10,14,26,30)

List 1 List 2 List 3 Minterm ABCDE Flags Minterms ABCDE Flags Minterms ABCDE Flags 0 00000 α √ 0,2 000-0 α √ 0,2,8,10 0-0-0 α PI1 2 00010 α √ 0,4 00-00 α PI4 8,10,24,26 -10-0 αβ PI2 4 00100 αβ √ 0,8 0-000 α √ 10,14,26,30 -1-10 αβ PI3 8 01000 αβ √ 2,10 0-010 α √ 3 00011 Β √ 4,20 -0100 αβ PI5 9 01001 α √ 8,9 0100α PI6 10 01010 αβ √ 8,10 010-0 αβ √ 20 10100 αβ √ 8,24 -1000 αβ √ 24 11000 αβ √ 3,11 0-011 β PI7 11 01011 β √ 10,14 01-10 αβ √ 14 01110 αβ √ 10,26 -1010 αβ √ 26 11010 αβ √ 24,26 110-0 αβ √ 30 11110 αβ √ 14,30 -1110 αβ √ 26,30 11-10 αβ √ √

PI1 α *PI2 αβ PI3 αβ PI4 α *PI5 αβ *PI6 α *PI7 β

0 X

√

2

⊗

√

8 X X

fα √

9

24

√

3

√

4

⊗

X X

20

√

fβ √

8

√

11

⊗

⊗

√

24

⊗

⊗

⊗ ⊗

⊗

Essential prime implicants: PI1, PI2, PI5, PI6 for fα, and PI2,PI5, PI7 for fβ. These cover all minterms. 𝑓𝑓𝛼𝛼 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝑃𝑃𝑃𝑃1 + 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃6 � 𝐸𝐸� + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � = 𝐴𝐴̅𝐶𝐶̅ 𝐸𝐸� + 𝐵𝐵𝐶𝐶̅ 𝐸𝐸� + 𝐵𝐵� 𝐶𝐶𝐷𝐷 𝑓𝑓𝛽𝛽 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = 𝑃𝑃𝑃𝑃2 + 𝑃𝑃𝑃𝑃5 + 𝑃𝑃𝑃𝑃7 � 𝐸𝐸� + 𝐴𝐴̅𝐶𝐶̅ 𝐷𝐷𝐷𝐷 = 𝐵𝐵𝐶𝐶̅ 𝐸𝐸� + 𝐵𝐵� 𝐶𝐶𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

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Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 3 – Combinational Logic Circuit Design and Analysis 3.1 Design minimal 2-level AND-OR and NAND-NAND realizations of the following logic function. Draw circuit diagrams of your realizations. 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = Σm(0,1,4,5,6) = 𝑥𝑥̅ 𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥̅ 𝑦𝑦�𝑧𝑧 + 𝑥𝑥𝑦𝑦�𝑧𝑧̅ + 𝑥𝑥𝑦𝑦�𝑧𝑧 + 𝑥𝑥𝑥𝑥𝑧𝑧̅ = 𝑦𝑦� + 𝑥𝑥𝑧𝑧̅

3.2 Design minimal 2-level OR-AND and NOR-NOR realizations of the function defined in problem 3.1. Draw circuit diagrams. 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = ΠM(2,3,7) = (𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧̅)(𝑥𝑥̅ + 𝑦𝑦� + 𝑧𝑧̅) = (𝑥𝑥 + 𝑦𝑦�)(𝑦𝑦� + 𝑧𝑧̅)

3.3 Write Verilog and/or VHDL dataflow models for the logic function given in problem 3.1. //Verilog Problem 3.3 module Problem3_3 (f,x,y,z); input x,y,z; output f; assign f = ~y | (x & ~z) ; endmodule --VHDL Problem 3.3 entity Problem3_3 is port (f: out bit; x,y,z: in bit); end Problem3_3; architecture dataflow of Problem3_3 is begin f <= not y or (x and not z); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.4 Write Verilog and/or VHDL structural models for your NAND-NAND design from problem 3.1. //Verilog Problem 3.4 structural model module Problem3_4 (f,x,y,z); input x,y,z; output f; wire yn, zn, xzn; not not1 (yn, y); not not2 (zn, z); and and1 (xzn, x, zn); or or1 (f, yn, xzn); endmodule --VHDL Problem 3.4 structural model entity Problem3_4 is port (f: out bit; -- output x,y,z: in bit); -- inputs end Problem3_4; architecture structure of Problem3_4 is component and2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component or2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component inv -- gate model in my library port (b: out bit; a1: in bit); end component; signal yn, zn, xzn: bit; -- internal wires begin N1: inv port map (b=>yn, a1=>y); N2: inv port map (b=>zn, a1=>z); A1: and2 port map (b=>xzn, a1=>x, a2=>zn); O1: or2 port map (b=>f, a1=>yn, a2=>xzn); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.5 Design minimal 2-level AND-OR and NAND-NAND realizations of the following logic function. Draw circuit diagrams. 𝑔𝑔(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ΠM(2,3,6,8,9,12) = Σm(0,1,4,5,7,10,11,13,14,15) = 𝑎𝑎�𝑏𝑏�𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐̅𝑑𝑑 + 𝑎𝑎�𝑏𝑏𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏𝑐𝑐̅𝑑𝑑 + 𝑎𝑎�𝑏𝑏𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑏𝑏�𝑐𝑐𝑑𝑑̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐𝑐𝑐 + 𝑎𝑎𝑎𝑎𝑐𝑐̅𝑑𝑑 + 𝑎𝑎𝑎𝑎𝑎𝑎𝑑𝑑̅ + 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 = 𝑎𝑎�𝑐𝑐̅ + 𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎

3.6 Design minimal 2-level OR-AND and NOR-NOR realizations of the function defined in problem 3. Draw circuit diagrams. 𝑔𝑔(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ΠM(2,3,6,8,9,12) = (𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐̅ + 𝑑𝑑)(𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐̅ + 𝑑𝑑̅ )(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐̅ + 𝑑𝑑)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐 + 𝑑𝑑) ∙ (𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐 + 𝑑𝑑̅)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐 + 𝑑𝑑) = (𝑎𝑎 + 𝑏𝑏 + 𝑐𝑐̅)(𝑎𝑎 + 𝑐𝑐̅ + 𝑑𝑑̅)(𝑎𝑎� + 𝑏𝑏 + 𝑐𝑐)(𝑎𝑎� + 𝑐𝑐 + 𝑑𝑑)

3.7 Write Verilog and/or VHDL dataflow models for the function defined in problem 3.5. //Verilog Problem 3.7 module Problem3_7 (g,a,b,c,d); input a,b,c,d; output g; assign g = (~a & ~c) | (b & d) | (a & c) ; endmodule

--VHDL Problem 3.7 entity Problem3_7 is port (g: out bit; a,b,c,d: in bit); end Problem3_7; architecture dataflow of Problem3_7 is begin g <= (not a and not c) or (b and d) or (a and c); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.8 Write Verilog and/or VHDL structural models for your NOR-NOR design from problem 3.5. //Verilog Problem 3.8 structural NOR-NOR module Problem3_8 (g,a,b,c,d); input a,b,c,d; output g; wire an, cn, dn, n1, n2, n3, n4; not not1 (an, a); not not2 (cn, c); not not3 (dn, c); nor nor1 (n1, a, b, cn); nor nor2 (n2, a, cn, dn); nor nor3 (n3, an, b, c); nor nor4 (n4, an, c, d); nor nor5 (g, n1, n2, n3, n4); endmodule --VHDL Problem 3.8 structural NOR-NOR entity Problem3_8 is port (g: out bit; -- output a,b,c,d: in bit); -- inputs end Problem3_8; architecture structure of Problem3_8 is component nor3 -- gate model in my library port (b: out bit; a1,a2,a3: in bit); end component; component nor4 -- gate model in my library port (b: out bit; a1,a2,a3,a4: in bit); end component; component inv -- gate model in my library port (b: out bit; a1: in bit); end component; signal an, cn, dn, n1, n2, n3, n4: bit; -- internal wires begin I1: inv port map (b=>an, a1=>a); I2: inv port map (b=>cn, a1=>c); I3: inv port map (b=>dn, a1=>d); NR1: nor3 port map (b=>n1, a1=>a, a2=>b, a3=>cn); NR2: nor3 port map (b=>n2, a1=>a, a2=>cn, a3=>dn); NR3: nor3 port map (b=>n3, a1=>an, a2=>b, a3=>c); NR4: nor3 port map (b=>n4, a1=>an, a2=>c, a3=>d); NR5: nor4 port map (b=>g, a1=>n1, a2=>n2, a3=>n3, a4=>n4); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.9 Find MSOP and MPOS expressions for the function realized by the logic circuit below. What is the worst-case propagation delay through this circuit if each gate has a delay of tgate?

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = (𝐴𝐴 ⊕ 𝐵𝐵)�𝐴𝐴𝐴𝐴� + (𝐵𝐵 + 𝐶𝐶) = (𝐴𝐴̅𝐵𝐵 + 𝐴𝐴𝐵𝐵� )(𝐴𝐴̅ + 𝐶𝐶̅ ) + 𝐵𝐵� 𝐶𝐶̅ = 𝐴𝐴̅𝐵𝐵 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐵𝐵� 𝐶𝐶̅ = 𝐴𝐴̅𝐵𝐵 + 𝐵𝐵� 𝐶𝐶̅ - MSOP ̅ ̅ ̅ � � = (𝐴𝐴 + 𝐵𝐵 𝐶𝐶 )(𝐵𝐵 + 𝐵𝐵 𝐶𝐶 ) = (𝐴𝐴̅ + 𝐵𝐵� )(𝐴𝐴̅ + 𝐶𝐶̅ )(𝐵𝐵 + 𝐶𝐶̅ ) = (𝐴𝐴̅ + 𝐵𝐵� )(𝐵𝐵 + 𝐶𝐶̅ ) -MPOS

The worst-case propagation delay is 3tgate, through three levels of gates.

3.10 Design a minimal realization of the circuit from problem 3.9 using only NAND2 and/or NOR2 gates. Draw the circuit diagram.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.11 Design a logic circuit with inputs A, B, C, D and outputs f and g as shown below. The inputs represent the four bits in a BCD digit. Output f should be logic-1 if the input digit is divisible by 3. Output g should be logic-0 if and only if the input is a valid BCD digit.

Assume you have NAND2, NAND3, NAND4, and NOT gates to use in your realization.

Minimize the number of gates and literals used. Draw your circuit diagram.

ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f 1 0 0 1 0 0 1 0 0 1 -

g 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(0,3,6,9) + 𝑑𝑑(10 − 15) � + 𝐵𝐵�𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � = 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵𝐷𝐷 𝑔𝑔(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(10 − 15) = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.12 Design a minimum two-level NAND realization for the following logic function. 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(1,2,3,5,6,7,8,9,12,14) � + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ = 𝐴𝐴̅𝐷𝐷 + 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐷𝐷

3.13 Repeat problem 3.12 for NOR gates. 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(1,2,3,5,6,7,8,9,12,14) = Π𝑀𝑀(0,4,10,11,13,15) � )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ ) = (𝐴𝐴 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴̅ + 𝐵𝐵� + 𝐷𝐷

3.14 Design a minimal two-level NAND realization for each of the following logic functions. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = Σ𝑚𝑚(0,2,3,7) = 𝐴𝐴̅𝐶𝐶̅ + 𝐵𝐵𝐵𝐵

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(0,2,8,10,14,15) = 𝐴𝐴̅𝐶𝐶̅ + 𝐵𝐵𝐵𝐵

(c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = Σ𝑚𝑚(4,5,6,7,25,27,29,31) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴

3.15 Design a minimal two-level NOR realization for the functions in problem 3.14. (a) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = Σ𝑚𝑚(0,2,3,7) = Π𝑀𝑀(1,4,5,6) = (𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐶𝐶)

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(0,2,8,10,14,15) = Π𝑀𝑀(1,3,4,5,6,7,9,11,12,13) �) = (𝐵𝐵� + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� )(𝐵𝐵 + 𝐷𝐷

(c) 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷, 𝐸𝐸) = Σ𝑚𝑚(4,5,6,7,25,27,29,31) = Π𝑀𝑀(0 − 3,8 − 24,26,28,30) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴

3.16 Find a minimum NAND-NAND equivalent circuit for the one below.

Writing expressions for each of the gate outputs: ���������� 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ((𝐴𝐴̅𝐵𝐵) + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶) ���������� = (𝐴𝐴 + 𝐵𝐵� + 𝐷𝐷)(𝐵𝐵 + 𝐶𝐶) ̅ � = 𝐴𝐴𝐵𝐵 𝐷𝐷 + 𝐵𝐵 + 𝐶𝐶 = 𝐵𝐵 + 𝐶𝐶

The equivalent circuit is thus a simple OR gate, which can be created with a NAND gate and two inverters.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.17 Find a minimum NOR-NOR equivalent circuit for the one above.

Since the above circuit reduces to a simple OR function (B+C) we can implement this with a NOR gate and an inverter.

3.18 Write Verilog and/or VHDL dataflow models of the function from Problem 3.16. //Verilog Problem 3.18 dataflow model module Problem3_18 (f,A,B,C,D); input A,B,C,D; output f; assign f = ~((D | ~(~A & B)) & ~(B | C)) ; endmodule

--VHDL Problem 3.18 dataflow model entity Problem3_18 is port (f: out bit; A,B,C,D: in bit); end Problem3_18; architecture dataflow of Problem3_18 is begin f <= (D or ((not A) nand B)) nand (B nor C); end;

3.19 Write Verilog and/or VHDL structural models of the circuit in Problem 3.16. //Verilog Problem 3.19 structural model module Problem3_19 (f,A,B,C,D); input A,B,C,D; output f; wire AN, N1, O1, R1; not not1 (AN, A); nand nand1 (N1, AN, B); or or1 (O1, D, N1); nor nor1 (R1, B, C); nand nand2 (f, O1, R1); endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem 3.19 structural model entity Problem3_19 is port (f: out bit; -- output A,B,C,D: in bit); -- inputs end Problem3_19; architecture structure of Problem3_19 is component nor2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component nand2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component or2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component inv -- gate model in my library port (b: out bit; a1: in bit); end component; signal AN, N1, R1, O1: bit; -- internal wires begin I1: inv port map (b=>AN, a1=>A); ND1: nand2 port map (b=>N1, a1=>AN, a2=>B); OR1: or2 port map (b=>O1, a1=>D, a2=>N1); NR1: nor2 port map (b=>R1, a1=>B, a2=>C); ND2: nand2 port map (b=>f, a1=>O1, a2=>R1); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.20 Given the timing diagram below, find the simplest Boolean expression for f ( A, B, C ) .

Time t0 t1 t2 t3 t4 t5 t6 t7

abc 000 001 010 011 100 101 110 111

f(A,B.C) 1 0 0 1 0 0 0 1

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = Σ𝑚𝑚(0,3,7) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ + 𝐵𝐵𝐵𝐵

3.21 Given the logic circuit below, find a minimum two-level NOR-NOR realization.

����̅ � �𝐴𝐴̅𝐷𝐷 �� ��𝐶𝐶𝐷𝐷 � � �𝐵𝐵�𝐷𝐷��] 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = ��𝐴𝐴𝐶𝐶

����̅ � �𝐴𝐴̅𝐷𝐷 � + �𝐶𝐶𝐷𝐷 � � �𝐵𝐵�𝐷𝐷� = �𝐴𝐴𝐶𝐶 � ) + (𝐶𝐶̅ + 𝐷𝐷)(𝐵𝐵 + 𝐷𝐷 �) = (𝐴𝐴̅ + 𝐶𝐶)(𝐴𝐴 + 𝐷𝐷 ̅ ̅ ̅ � ) + (𝐵𝐵 + 𝐷𝐷 � )] � = [(𝐴𝐴 + 𝐶𝐶)(𝐴𝐴 + 𝐷𝐷 ) + (𝐶𝐶 + 𝐷𝐷)][(𝐴𝐴 + 𝐶𝐶)(𝐴𝐴 + 𝐷𝐷 � )][(𝐴𝐴 + 𝐷𝐷 � ) + (𝐵𝐵 + 𝐷𝐷 � )] � ) + (𝐶𝐶̅ + 𝐷𝐷)][(𝐴𝐴̅ + 𝐶𝐶) + (𝐵𝐵 + 𝐷𝐷 = [(𝐴𝐴̅ + 𝐶𝐶) + (𝐶𝐶̅ + 𝐷𝐷)][(𝐴𝐴 + 𝐷𝐷 ̅ ̅ ̅ ̅ � � � � (𝐴𝐴 )(𝐴𝐴 = + 𝐶𝐶 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐷𝐷 + 𝐶𝐶 + 𝐷𝐷)(𝐴𝐴 + 𝐶𝐶 + 𝐵𝐵 + 𝐷𝐷 + 𝐷𝐷 + 𝐵𝐵 + 𝐷𝐷 ) � )(𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷 �) = (𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷 � )(𝐴𝐴 + 𝐵𝐵 + 𝐷𝐷 �) = (𝐵𝐵 + 𝐶𝐶 + 𝐷𝐷

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.22 Write Verilog and/or VHDL structural models for the circuit given in Problem 3.21. //Verilog Problem 3.22 structural model module Problem3_22 (f,A,B,C,D); input A,B,C,D; output f; wire AN,BN,CN,DN,N1,N2,N3,N4,N5,N6; not not1 (AN, A); not not2 (BN, B); not not3 (CN, C); not not4 (DN, D); nand nand1 (N1, A, CN); nand nand2 (N2, AN, D); nand nand3 (N3, C, DN); nand nand4 (N4, BN, D); nand nand5 (N5, N1, N2); nand nand6 (N6, N3,N4); nand nand7 (f, N5,N6); endmodule

--VHDL Problem 3.22 structural model entity Problem3_22 is port (f: out bit; -- output A,B,C,D: in bit); -- inputs end Problem3_22; architecture structure of Problem3_22 is component nand2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component inv -- gate model in my library port (b: out bit; a1: in bit); end component; signal AN,BN,CN,DN,N1,N2,N3,N4,N5,N6: bit; -- internal wires begin I1: inv port map (b=>AN, a1=>A); I2: inv port map (b=>BN, a1=>B); I3: inv port map (b=>CN, a1=>C); I4: inv port map (b=>DN, a1=>D); ND1: nand2 port map (b=>N1, a1=>A, a2=>CN); ND2: nand2 port map (b=>N2, a1=>AN, a2=>D); ND3: nand2 port map (b=>N3, a1=>C, a2=>DN); ND4: nand2 port map (b=>N4, a1=>BN, a2=>D); ND5: nand2 port map (b=>N5, a1=>N1, a2=>N2); ND6: nand2 port map (b=>N6, a1=>N3, a2=>N4); ND7: nand2 port map (b=>f, a1=>N5, a2=>N6); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.23 Write Verilog and/or VHDL dataflow models for the function realized by the circuit in Problem 3.21. //Verilog Problem 3.23 dataflow model module Problem3_23 (f,A,B,C,D); input A,B,C,D; output f; assign f = ~(~( (~(A & ~C)) & (~(~A & D))) & ~(( ~(C & ~D)) & (~(~B & D)))) ; endmodule

--VHDL Problem 3.23 dataflow model entity Problem3_23 is port (f: out bit; A,B,C,D: in bit); end Problem3_23; architecture dataflow of Problem3_23 is begin f <= ((A nand not C) nand (not A nand D)) nand ((C nand not D) nand (not B nand D)); end;

3.24 For the timing diagram shown below, find both a minimum NAND-NAND and a minimum NOR-NOR realization.

Time ABC 000 t0 001 t1 010 t2 011 t3 100 t4 101 t5 110 t6 111 t7

f ( A, B , C) 0 1 0 1 0 0 1 1

f(A,B,C) = Σ𝑚𝑚(1,3,6,7) = ∏𝑀𝑀(0,2,4,5)

= 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐶𝐶 + 𝐴𝐴𝐴𝐴 = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ ) = (𝐴𝐴 + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.25 A long hallway has three doors, one at each end and one in the middle. A switch is located at each door to operate the lights along the hallway. Label the switches A , B , and C .

Assume that flipping any of the switches will turn the light on if it’s currently off, or off if it’s currently on. Write a Verilog and/or VHDL model of the logic needed to control the lights.

ABC 000 001 010 011 100 101 110 111

f(A,B,C) 0 1 1 0 1 0 0 1

- all off initially - 1st switch on - 1st switch on - 2nd switch on - 1st switch on - 2nd switch on - 2nd switch on - 3rd switch on

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = Σ𝑚𝑚(1,2,4,7) = Π𝑀𝑀(0,3,5,6) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴̅𝐵𝐵 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶)

//Verilog Problem 3.25 hallway light module Problem3_25_HallLight (f,A,B,C); input A,B,C; output f; assign f = (~A & ~B & C) | (~A & B & ~C) | (A & ~B & ~C) | (A & B & C) ; //sum of minterms endmodule --VHDL Problem 3.25 hallway light entity Problem3_25_HallLight is port (f: out bit; A,B,C: in bit); end Problem3_25_HallLight; architecture dataflow of Problem3_25_HallLight is begin f <= (not A and not B and C) or (not A and B and not C) or (A and not B and not C) or (A and B and C); -- sum of minterms end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.26 Joe, Jack, and Jim get together once a week to either go to a movie or go bowling. To decide what to do, they vote and a simple majority wins. Assuming a vote for the movie is represented as a 1, design a logic circuit that automatically computes the decision. Realize your design with a minimum number of NAND and NOR gates. Write a Verilog and/or VHDL behavioral model of design.

Let x = Joe, y = Jack, z = Jim xyz 000 001 010 011 100 101 110 111

f(x,y,z) 0 0 0 1 0 1 1 1

𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = Σ𝑚𝑚(3,5,6,7) = Π𝑀𝑀(0,1,2,4) = 𝑥𝑥̅ 𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑦𝑦�𝑧𝑧 + 𝑥𝑥𝑥𝑥𝑧𝑧̅ + 𝑥𝑥𝑥𝑥𝑥𝑥 = 𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑥𝑥 + 𝑥𝑥𝑥𝑥 - MSOP = (𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧̅)(𝑥𝑥 + 𝑦𝑦� + 𝑧𝑧)(𝑥𝑥̅ + 𝑦𝑦 + 𝑧𝑧) = (𝑥𝑥 + 𝑦𝑦)(𝑥𝑥 + 𝑧𝑧)(𝑦𝑦 + 𝑧𝑧) - MPOS

//Verilog Problem 3.26 voting module Problem3_26_Voter (f,A,B,C); input A,B,C; output f; assign f = (A & B) | (A & C) | (B & C); //sum of products endmodule --VHDL Problem 3.26 voter entity Problem3_26_Voter is port (f: out bit; A,B,C: in bit); end Problem3_26_Voter; architecture dataflow of Problem3_26_Voter is begin f <= (A and B) or (A and C) or (B and C); -- sum of products end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.27 Derive the logic equation for a circuit with three inputs A , B , C and output z.. The output is to be high only when exactly one of the three inputs is high. Realize your circuit with a minimum of NAND and NOR gates. Also write a Verilog and/or VHDL behavioral model.

ABC 000 001 010 011 100 101 110 111

f(A,B,C) 0 1 1 0 1 0 0 0

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = Σ𝑚𝑚(1,2,4) = Π𝑀𝑀(0,3,5,6,7) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐵𝐵� 𝐶𝐶̅ - MSOP = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵 + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶)(𝐴𝐴̅ + 𝐵𝐵� + 𝐶𝐶̅ ) = (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)(𝐵𝐵� + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐶𝐶̅ )(𝐴𝐴̅ + 𝐵𝐵� ) - MPOS

//Verilog Problem 3.27 one-of-three module Problem3_27_OneOfThree (f,A,B,C); input A,B,C; output f; assign f = (~A & ~B & C) | (~A & B & ~C) | (A & ~B & ~C); //sum of products endmodule --VHDL Problem 3.27 one-of-three entity Problem3_27_OneOfThree is port (f: out bit; A,B,C: in bit); end Problem3_27_OneOfThree; architecture dataflow of Problem3_27_OneOfThree is begin f <= (not A and not B and C) or (not A and B and not C) or (A and not B and not C); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.28 We wish to design a logic circuit with four inputs A , B , C , and D . The output is to be high only when a majority of the inputs is high. Realize the circuit using only NOR gates.

ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f(A,B,C,D) 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Π𝑀𝑀(0 − 6,8,9,10,12)

3.29 A logic circuit has four inputs A , B , C , and D . Find the logic equations for the circuit if the output is to be high only when an odd number of the inputs is high. Realize the circuit using a minimum number of logic gates.

ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f(A,B,C,D) 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(1,2,4,7,8,11,13,14) � + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐶𝐶 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 There are no adjacent minterms/maxterms.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.30 The input to a logic circuit consists of four signal lines A , B , C , and D . These lines represent a 4-bit binary number, where A is the most significant bit and D the least significant bit. Design the logic circuit such that the output is high only when the binary input is less than (0111) 2 = 710 . Use any type of logic gate to realize the circuit.

ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f(A,B,C,D) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0

𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(0 − 6) = Π𝑀𝑀(7 − 15)

MSOP form:

3.31 A burglar alarm controller is designed so that it senses four input signal lines. Line A is from a secret control switch, line B is from a pressure sensor under a steel safe in a locked closet, line C is from a battery-powered clock, and line D is connected to a switch on the locked closet door. The following conditions produce a logic 1 voltage on the corresponding input line.

A: The control switch is closed.

B: The safe is in its normal position in the closet.

C: The clock is between 0900 and 1600 hours.

D: The closet door is closed.

Write a logic expression for the burglar alarm that produces a logic 1 (rings a bell) when the safe is moved and the control switch is closed, or when the closet is opened after banking hours, or when the closet is opened with the control switch open. Write a Verilog and/or VHDL model for alarm controller. � 𝐶𝐶̅ + 𝐷𝐷 � 𝐴𝐴̅ 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝐵𝐵� 𝐴𝐴 + 𝐷𝐷

//Verilog Problem 3.31 Burglar Alarm module Problem3_31_BurglarAlarm (f,A,B,C,D); input A,B,C,D; output f; assign f = (~B & A) | (~D & ~C) | (~D & ~A); endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL burglar alarm entity Problem3_31_BurglarAlarm is port (f: out bit; A,B,C,D: in bit); end Problem3_31_BurglarAlarm; architecture equations of Problem3_31_BurglarAlarm is begin f <= (not B and A) or (not D and not C) or (not D and not A); end;

3.32 Derive the logic equations for a circuit that will subtract two 2-bit binary numbers, ( X 1 X 0 ) 2 − (Y1Y0 ) 2 , and produce as an output the resulting number ( D1 D0 ) 2 and borrow condition B1 . Write a Verilog and/or VHDL model of the subtractor.

X1 X0 Y1 Y0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

B1 D1 D0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 0

𝐷𝐷1 = ∑ 𝑚𝑚(1,2,6,7,8,11,12,13)

𝐷𝐷1 = 𝑋𝑋�1 𝑋𝑋�0 𝑌𝑌�1 𝑌𝑌0 + 𝑋𝑋1 𝑋𝑋�0 𝑌𝑌1 𝑌𝑌0 + 𝑋𝑋1 𝑌𝑌�1 𝑌𝑌�0 +𝑋𝑋1 𝑋𝑋0 𝑌𝑌�1 + 𝑋𝑋�1 𝑋𝑋0 𝑌𝑌1 + 𝑋𝑋�1 𝑌𝑌1 𝑌𝑌�0

𝐵𝐵1 = ∑ 𝑚𝑚(1,2,3,6,7,11)

𝐵𝐵1 = 𝑋𝑋�1 𝑌𝑌1 + 𝑋𝑋�1 𝑋𝑋�0 𝑌𝑌0 + 𝑋𝑋�0 𝑌𝑌1 𝑌𝑌0

𝐷𝐷0 = ∑ 𝑚𝑚(1,3,4,6,9,11,12,14)

𝐷𝐷0 = 𝑋𝑋�0 𝑌𝑌0 + 𝑋𝑋0 𝑌𝑌�0

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Verilog Problem 3.32 Subtractor module Problem3_32_Subtractor (B1,D1,D0,X1,X0,Y1,Y0); input X1,X0,Y1,Y0; output B1,D1,D0; assign {B1,D1,D0} = {X1,X0} - {Y1,Y0}; endmodule --VHDL Problem 3.32 Subtractor library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Problem3_32_Subtractor is port (B1,D1,D0: out STD_LOGIC; X1,X0,Y1,Y0: in STD_LOGIC); end Problem3_32_Subtractor; architecture equations of Problem3_32_Subtractor is signal Diff: unsigned (2 downto 0); signal XS,YS: std_logic_vector (1 downto 0); begin XS <= ‘0’ & X1 & X0; YS <= ‘1’ & (not Y1) & (not Y0); Diff <= UNSIGNED(XX) + UNSIGNED(YY) + 1; -- numeric_std UNSIGNED type B1 <= Diff(2); D1 <=Diff(1); D0 <= Diff(0); end;

3.33 Design a logic circuit that accepts BCD inputs and gives an output of logic 1 only when the input decimal digit is divisible by 3. Use a four-variable K-map to design your circuit.

ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f(A,B,C,D) 1 0 0 1 0 0 1 0 0 1 -

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.34 Design a logic circuit that has five input variables and one output variable. Four of the input variables represent BCD digits, and the fifth is a control line. While the control line is at logic 0, the output should be logic 1 only if the BCD digit is greater than or equal to 5.

While the control line is high, the output should be logic 1 only if the BCD digit is less than or equal to 5.

CTL ABCD 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111

f 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 -

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.35 Design a multiple-output logic circuit whose input is a BCD digit and whose outputs are defined as follows: 𝑓𝑓1 : Detects input digits that are divisible by 4, 𝑓𝑓2 : Detects numbers greater than or equal to 3, 𝑓𝑓3 : Detects numbers less than 7. Write a Verilog and/or VHDL model of the circuit. Also, realize the circuit using NAND gates.

𝑓𝑓1 = Σ𝑚𝑚(4,8) + 𝑑𝑑(10 − 15) � 𝑓𝑓1 = 𝐶𝐶̅ 𝐷𝐷

𝑓𝑓2 = Σ𝑚𝑚(3 − 9) + 𝑑𝑑(10 − 15) 𝑓𝑓2 = 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶𝐶𝐶

𝑓𝑓3 = Σ𝑚𝑚(0 − 6) + 𝑑𝑑(10 − 15) 𝑓𝑓3 = 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴̅𝐶𝐶̅

//Verilog Problem 3.35 module Problem3_35 (f1,f2,f3,A,B,C,D); input A,B,C,D; output f1,f2,f3; assign f1 = ({C,D} == 2’b00) ? 1’b1 : 1’b 0; // ends in 00 if divisible by 4 assign f2 = ({A,B,C,D} >= 4’d3) ? 1’b 1 : 1’b 0; // greater or equal to 3 assign f3 = ({A,B,C,D} < 4’d7) ? 1’b 1 : 1’b 0; // less than 7 endmodule --VHDL Problem 3.35 entity Problem3_35 is port (f1,f2,f3: out bit; A,B,C,D: in bit); end Problem3_35; architecture behavior of Problem3_35 is signal ABCD: bit_vector(3 downto 0); -- 4-bit vector for BCD number begin ABCD <= A & B & C & D; -- create 4-bit vector f1 <= ‘1’ when ABCD(1 downto 0) = “00” else ‘0’; -- ends in 00 if divisible by 4 f2 <= ‘1’ when ABCD >= “0011” else ‘0’; -- greater or equal to 3 f3 <= ‘1’ when ABCD < “0111” else ‘0’; -- less than 7 end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.36 Design a multiple-output combinational network that has two input signals x0 and x1, two control signals c0 and c1, and two output functions f0 and f1. The control signals have the following effect on the outputs. For example, when c0 = 0 and c1 = 1, then f0(x0, x1, c0, c1) = x0 and f1(x0, x1, c0, c1) = 0. Write a Verilog and/or VHDL model of the circuit. Also, realize the circuit using NOR gates.

c0 0 0

c1 0 1

1 1

0 1

f0 0 x0 0 x0

f1 0 0 x1 x1

//Verilog Problem 3.36 module Problem3_36 (f0,f1,x0,x1,c0,c1); input x0,x1,c0,c1; output f0,f1; assign f0 = (c1 == 1) ? x0 : 0; assign f1 = (c0 == 1) ? x1 : 0; endmodule --VHDL Problem 3.36 entity Problem3_36 is port (f0,f1: out bit; x0,x1,c0,c1: in bit); end Problem3_36; architecture behavior of Problem3_36 is begin f0 <= x0 when c1 = ‘1’ else ‘0’; f1 <= x1 when c0 = ‘1’ else ‘0’; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.37 Derive logic expressions for outputs 5 and 11 of the 4-to-16 decoder module in Fig. 3.33.

Using these expressions, describe the operation of the decoder and the function of the enable inputs. ���� ∙ 𝐺𝐺2 ����)𝐷𝐷 ����) ∙ 𝑚𝑚5 � 𝐶𝐶𝐵𝐵� 𝐴𝐴 = ������������������ Output 5: (𝐺𝐺1 (𝐺𝐺1 ∙ 𝐺𝐺2 ������������������� ���� ∙ ���� Output 11: (𝐺𝐺1 𝐺𝐺2)𝐷𝐷𝐶𝐶̅ 𝐵𝐵𝐵𝐵 = (𝐺𝐺1 ∙ ���� 𝐺𝐺2) ∙ 𝑚𝑚 11

���� ∙ ���� When G1 = 1 or G2 = 1, (𝐺𝐺1 𝐺𝐺2) = 0, and all outputs are 1 (disabled). ���� (𝐺𝐺1 When G1 = 0 and G2 = 0, ∙ ���� 𝐺𝐺2) = 1, and the outputs correspond to minterms.

3.38 Design a Verilog and/or VHDL behavioral module for a 4-to-16 decoder. The inputs are {D, C , B, A} and the outputs are active low {O0 , O1 , , O15 } . The decoder should have one active-high enable line, E . //Problem 3.38 4-to-16 decoder module Problem3_38 (E,D,C,B,A,O); input E,D,C,B,A; output reg [15:0] O; always @(*) if (E == 0) O = 16’b1111111111111111; // all outputs inactive if disabled else case ({D,C,B,A}) 4'd0: O = 16’b1111111111111110 ; //activate O(0) 4'd1: O = 16’b1111111111111101 ; //activate O(1) 4'd2: O = 16’b1111111111111011 ; //activate O(2) 4'd3: O = 16’b1111111111110111 ; //activate O(3) 4'd4: O = 16’b1111111111101111 ; //activate O(4) 4'd5: O = 16’b1111111111011111 ; //activate O(5) 4'd6: O = 16’b1111111110111111 ; //activate O(6) 4'd7: O = 16’b1111111101111111 ; //activate O(7) 4'd8: O = 16’b1111111011111111 ; //activate O(8) 4'd9: O = 16’b1111110111111111 ; //activate O(9) 4'd10: O = 16’b1111101111111111 ; //activate O(10) 4'd11: O = 16’b1111011111111111 ; //activate O(11) 4'd12: O = 16’b1110111111111111 ; //activate O(12) 4'd13: O = 16’b1101111111111111 ; //activate O(13) 4'd14: O = 16’b1011111111111111 ; //activate O(14) 4'd15: O = 16’b0111111111111111 ; //activate O(15) endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- VHDL Problem 3-38 4-to-16 decoder entity Problem3_38 is port (E: in bit; -- active-high enable input D,C,B,A: in bit; -- decoder inputs O: out bit_vector(15 downto 0)); -- active-low outputs O(15) to O(0) end Problem3_38; architecture behavior of Problem3_38 is signal T: bit_vector(3 downto 0); -- vector for inputs begin T <= D & C & B & A; -- 4-bit number for DCBA O <= “1111111111111111” when E = ‘0’ else -- all outputs inactive if not enabled “1111111111111110” when T = “0000” else -- activate O(0) “1111111111111101” when T = “0001” else -- activate O(1) “1111111111111011” when T = “0010” else -- activate O(2) “1111111111110111” when T = “0011” else -- activate O(3) “1111111111101111” when T = “0100” else -- activate O(4) “1111111111011111” when T = “0101” else -- activate O(5) “1111111110111111” when T = “0110” else -- activate O(6) “1111111101111111” when T = “0111” else -- activate O(7) “1111111011111111” when T = “1000” else -- activate O(8) “1111110111111111” when T = “1001” else -- activate O(9) “1111101111111111” when T = “1010” else -- activate O(10) “1111011111111111” when T = “1011” else -- activate O(11) “1110111111111111” when T = “1100” else -- activate O(12) “1101111111111111” when T = “1101” else -- activate O(13) “1011111111111111” when T = “1110” else -- activate O(14) “0111111111111111” when T = “1111”; -- activate O(15) end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.39 Design a 5-to-32 decoder using 3-to-8 decoder modules as building blocks. Assume each 3to-8 decoder has one active-low enable input, E1 , and one active-high enable input, E2 .

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.40 Realize each of the following sets of functions using a 4-to-16 decoder module and output logic gates (choose NAND or AND gates to minimize the fan-in of the output gates). (a) 𝑓𝑓1 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑ 𝑚𝑚(2,4,10,11,12,13) 𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∏ 𝑀𝑀(0 − 3,6 − 9,12,14,15) = ∑ 𝑚𝑚(4,5,10,11,13) 𝑓𝑓3 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑏𝑏�𝑐𝑐 + 𝑎𝑎�𝑏𝑏�𝑑𝑑 = ∑ 𝑚𝑚(1,2,3,10,11)

(b) 𝑓𝑓1 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑ 𝑚𝑚(0,1,7,13) 𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑎𝑎𝑎𝑎𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 = ∑ 𝑚𝑚(11,12,13,15) 𝑓𝑓3 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∏ 𝑀𝑀(0,1,2,5,6,7,8,9,11,12,15) = ∑ 𝑚𝑚(3,4,10,13,14)

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) Repeat part (a) for the complements of the three functions.

(d) Repeat part (b) for the complements of the three functions.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.41 Given the circuit below, find the minimum SOP expression for f (W , X , Y , Z ) .

𝑓𝑓(𝑊𝑊, 𝑋𝑋, 𝑌𝑌, 𝑍𝑍) = (𝑚𝑚 � 0 𝑚𝑚 � 1 𝑚𝑚 � 9 𝑚𝑚 � 11 ) + (𝑚𝑚 � 9 𝑚𝑚 � 11 𝑚𝑚 � 13 𝑚𝑚 � 15 ) = (𝑚𝑚0 + 𝑚𝑚1 + 𝑚𝑚9 + 𝑚𝑚11 )(𝑚𝑚9 + 𝑚𝑚11 + 𝑚𝑚13 + 𝑚𝑚15 ) = 𝑚𝑚9 + 𝑚𝑚11 = 𝑊𝑊𝑋𝑋�𝑌𝑌�𝑍𝑍 + 𝑊𝑊𝑋𝑋�𝑌𝑌𝑌𝑌 = 𝑊𝑊𝑋𝑋�𝑍𝑍

3.42 Design a logic circuit realization binary-to-decimal decoder whose inputs are active-high, 4bit, BCD-encoded numbers ( x3 x2 x1 x0 ) and whose outputs are the active-low lines

(d 9 , d 8 ,, d1 , d 0 ) .

NOTE: The K-map for each output di has six don’t care terms (10-15) and a single minterm mi. Expressions are complemented to make outputs active low. 𝑑𝑑0 = 𝑥𝑥̅ 3 𝑥𝑥̅2 𝑥𝑥̅1 𝑥𝑥̅0 𝑑𝑑1 = 𝑥𝑥̅3 𝑥𝑥̅2 𝑥𝑥̅1 𝑥𝑥0 𝑑𝑑2 = 𝑥𝑥̅ 2 𝑥𝑥1 𝑥𝑥̅0 𝑑𝑑3 = 𝑥𝑥̅ 2 𝑥𝑥1 𝑥𝑥0 𝑑𝑑4 = 𝑥𝑥2 𝑥𝑥̅1 𝑥𝑥̅0

𝑑𝑑5 = 𝑥𝑥2 𝑥𝑥̅1 𝑥𝑥0 𝑑𝑑6 = 𝑥𝑥2 𝑥𝑥1 𝑥𝑥̅0 𝑑𝑑7 = 𝑥𝑥2 𝑥𝑥1 𝑥𝑥0 𝑑𝑑8 = 𝑥𝑥3 𝑥𝑥̅0 𝑑𝑑9 = 𝑥𝑥3 𝑥𝑥0

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.43 Design a behavioral Verilog and/or VHDL module for the decoder described above. //Verilog Problem 3.43 binary to decimal decoder – dataflow model of Problem 3.42 equations module Problem3_43_dataflow (A,B,C,D,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9); input A,B,C,D; output d0,d1,d2,d3,d4,d5,d6,d7,d8,d9; assign d0 = ~(~D&~C&~B&~A); assign d1 = ~(~D&~C&~B&A); assign d2 = ~(~C&B&~A); assign d3 = ~(~C&B&A); assign d4 = ~(C&~B&~A); assign d5 = ~(C&~B&A); assign d6 = ~(C&B&~A); assign d7 = ~(C&B&A); assign d8 = ~(D&~A); assign d9 = ~(D&A); endmodule //Verilog Problem 3.43 binary to decimal decoder – behavioral model module Problem3_43_behavior (xin,dout); input [3:0] xin; //4 inputs xin(3:0) output [9:0] dout; //10 outputs dout(9:0) reg [9:0] dint; //internal wire dint(9:0) always @(*) //react to any input change case (xin) 4'b0000: dint = 10'b1111111111; //d0 active 4'b0001: dint = 10'b1111111101; //d1 active 4'b0010: dint = 10'b1111111011; //d2 active 4'b0011: dint = 10'b1111110111; //d3 active 4'b0100: dint = 10'b1111101111; //d4 active 4'b0101: dint = 10'b1111011111; //d5 active 4'b0110: dint = 10'b1110111111; //d6 active 4'b0111: dint = 10'b1101111111; //d7 active 4'b1000: dint = 10'b1011111111; //d8 active 4'b1001: dint = 10'b0111111111; //d9 active default: dint = 10'b1111111111; //no active outputs otherwise endcase assign dout = dint; //drive the outputs endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem 3.43 binary to decimal decoder – dataflow model of Problem 3.42 equations library ieee; use ieee.std_logic_1164.all; entity Problem3_43_dataflow is port (D,C,B,A: in std_logic; -- decimal input Y: out std_logic_vector(9 downto 0)); -- active-low outputs end Problem3_43_dataflow; architecture dataflow of Problem3_43_dataflow is begin Y(0) <= not (not D and not C and not B and not A); Y(1) <= not (not D and not C and not B and A); Y(2) <= not (not C and B and not A); Y(3) <= not (not C and B and A); Y(4) <= not (C and not B and not A); Y(5) <= not (C and not B and A); Y(6) <= not (C and B and not A); Y(7) <= not (C and B and A); Y(8) <= not (D and not A); Y(9) <= not (D and A); end; -- VHDL Problem 3.43 binary to decimal decoder – behavioral model library ieee; use ieee.std_logic_1164.all; entity Problem3_43_behavior is port (xin: in bit_vector(3 downto 0); -- decoder inputs x(3) to x(0) dout: out bit_vector(9 downto 0)); -- active-low outputs d(9) to d(0) end Problem3_43_behavior; architecture behavior of Problem3_43_behavior is begin dout <= “1111111110” when xin = “0000” else -- activate O(0) “1111111101” when xin = “0001” else -- activate O(1) “1111111011” when xin = “0010” else -- activate O(2) “1111110111” when xin = “0011” else -- activate O(3) “1111101111” when xin = “0100” else -- activate O(4) “1111011111” when xin = “0101” else -- activate O(5) “1110111111” when xin = “0110” else -- activate O(6) “1101111111” when xin = “0111” else -- activate O(7) “1011111111” when xin = “1000” else -- activate O(8) “0111111111” when xin = “1001” else -- activate O(9) “1111111111” ; -- all outputs inactive otherwise end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.44 Design a decoder whose input is a 4-bit code (c3c2 c1c0 ) representing the hexadecimal digits {0 to 9,A,b,C,d,E,F } , with the outputs driving a seven-segment display digit to display the corresponding character. (The letters B and D are normally displayed in lowercase to distinguish them from the numerals 8 and 0, respectively.) c3c2c1c0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Segments: SASBSCSDSESFSG 1111110 0110000 1101101 1111001 0110011 1011011 1011111 1110000 1111111 1110011 1110111 0011111 1001110 0111101 1001111 1000111

𝑆𝑆𝐸𝐸 = 𝑐𝑐̅2 𝑐𝑐̅0 + 𝑐𝑐1 𝑐𝑐̅0 + 𝑐𝑐3 𝑐𝑐2 + 𝑐𝑐3 𝑐𝑐1

𝑆𝑆𝐴𝐴 = 𝑐𝑐̅2 𝑐𝑐̅0 + 𝑐𝑐̅3 𝑐𝑐1 + 𝑐𝑐2 𝑐𝑐1 + 𝑐𝑐3 𝑐𝑐̅0 +𝑐𝑐̅3 𝑐𝑐2 𝑐𝑐0 + 𝑐𝑐3 𝑐𝑐̅2 𝑐𝑐̅1

𝑆𝑆𝐵𝐵 = 𝑐𝑐̅3 𝑐𝑐̅2 + 𝑐𝑐̅2 𝑐𝑐̅0 + 𝑐𝑐̅3 𝑐𝑐̅1 𝑐𝑐̅0 +𝑐𝑐̅3 𝑐𝑐1 𝑐𝑐0 + 𝑐𝑐3 𝑐𝑐̅1 𝑐𝑐0

𝑆𝑆𝐶𝐶 = 𝑐𝑐̅3 𝑐𝑐̅1 + 𝑐𝑐̅3 𝑐𝑐0 + 𝑐𝑐̅3 𝑐𝑐2 +𝑐𝑐3 𝑐𝑐̅2 + 𝑐𝑐̅1 𝑐𝑐0

𝑆𝑆𝐷𝐷 = 𝑐𝑐̅3 𝑐𝑐̅2 𝑐𝑐̅0 + 𝑐𝑐2 𝑐𝑐̅1 𝑐𝑐0 + 𝑐𝑐2 𝑐𝑐1 𝑐𝑐̅0 +𝑐𝑐̅2 𝑐𝑐1 𝑐𝑐0 + 𝑐𝑐3 𝑐𝑐̅1 𝑐𝑐̅0

𝑆𝑆𝐹𝐹 = 𝑐𝑐̅1 𝑐𝑐̅0 + 𝑐𝑐2 𝑐𝑐̅0 + 𝑐𝑐3 𝑐𝑐1 + 𝑐𝑐3 𝑐𝑐̅2 + 𝑐𝑐̅3 𝑐𝑐2 𝑐𝑐̅1 𝑆𝑆𝐺𝐺 = 𝑐𝑐̅3 𝑐𝑐2 𝑐𝑐̅1 + 𝑐𝑐3 𝑐𝑐0 + 𝑐𝑐1 𝑐𝑐̅0 +𝑐𝑐3 𝑐𝑐̅2 + 𝑐𝑐̅2 𝑐𝑐1

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Digital Logic Circuit Analysis and Design, 2nd Edition

Note: Several AND gate outputs (product terms) could be shared by multiple functions, to reduce overall gate count.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.45 Write a behavioral Verilog and/or VHDL model for the HEX to seven-segment decoder described in problem 3.44. //Verilog Problem 3.45 hex to 7-segment decoder module Problem3_45_Hex2Segments (cin,seg); input [3:0] cin; //4 inputs cin(3) to cin(0) output [6:0] seg; //7 segment outputs: gfedcba reg [6:0] tint; //internal wire always @(*) case (cin) // gfedcba 4'b0000: tint = 7'b0111111; // 0 4'b0001: tint = 7'b0000110; // 1 4'b0010: tint = 7'b1011011; // 2 4'b0011: tint = 7'b1001111; // 3 4'b0100: tint = 7'b1100110; // 4 4'b0101: tint = 7'b1101101; // 5 4'b0110: tint = 7'b1111101; // 6 4'b0111: tint = 7'b0000111; // 7 4'b1000: tint = 7'b1111111; // 8 4'b1001: tint = 7'b1100111; // 9 4'b1010: tint = 7'b1110111; // A 4'b1011: tint = 7'b1111100; // B (b) 4'b1100: tint = 7'b0111001; // C 4'b1101: tint = 7'b1011110; // D (d) 4'b1110: tint = 7'b1111001; // E // F 4'b1111: tint = 7'b1110001; default: tint = 7'b0000000; //no active outputs otherwise endcase assign seg = tint; //drive the outputs endmodule

-- VHDL Problem 3.45 hex to 7-segment decoder entity Problem3_45_Hex2Segments is port (cin: in bit_vector(3 downto 0); -- decoder inputs c(3) to c(0) seg: out bit_vector(6 downto 0)); -- 7 segment outputs seg(6) to seg(0) end Problem3_45_Hex2Segments; architecture behavior of Problem3_45_Hex2Segments is begin with cin select seg <= “0111111” when “0000”, -- 0 “0000110” when “0001”, -- 1 “1011011” when “0010”, -- 2 “1001111” when “0011”, -- 3 “1100110” when “0100”, -- 4 “1101101” when “0101”, -- 5 “1111101” when “0110”, -- 6 “0000111” when “0111”, -- 7 “1111111” when “1000”, -- 8 “1100111” when “1001”, -- 9 “1110111” when “1010”, -- A “1111100” when “1011”, -- B (b) “0111001” when “1100”, -- C “1011110” when “1101”, -- D (d)

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Digital Logic Circuit Analysis and Design, 2nd Edition

end;

“1111001” when “1110”, -- E “1110001” when “1111”, -- F “0000000” when others ; -- all outputs inactive otherwise

3.46 Design a logic circuit that converts a 4-bit number from sign magnitude format to two's complement format. Use a two-level AND-OR circuit for each of the four outputs.

Value

+0 +1 +2 +3 +4 +5 +6 +7 -0 -1 -2 -3 -4 -5 -6 -7

x3x2x1x0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

y3y2y1y0 0000 0001 0010 0011 0100 0101 0110 0111 0000 1111 1110 1101 1100 1011 1010 1001

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.47 Repeat problem 3.46 for behavioral Verilog and/or VHDL.

//Verilog Problem 3.47 sign-magnitude to 2s complement module Problem3_47_SignMag2TwoComplement (xin,yout); input [3:0] xin; //sign-magnitude input output [3:0] yout; //twos-complement output assign yout = (xin[3] == 1’b0) ? xin : //positive values same ~{1’b0, xin[2:0]} + 1’b1; //twos complement for negative endmodule

-- VHDL Problem 3.47 sign-magnitude to 2s complement library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Problem3_47_SignMag2TwoComplement is port (xin: in std_logic_vector(3 downto 0); -- sign-magnitude input yout: out std_logic_vector(3 downto 0)); -- twos-complement output end Problem3_47_SignMag2TwoComplement; architecture behavior of Problem3_47_SignMag2TwoComplement is begin yout <= xin when xin(3) = ‘0’ else --positive values same std_logic_vector(unsigned(not(‘0’ & xin(2:0))) + 1); --twos complement of xin + 1 end;

3.48 Design a decoder that converts a 4-bit number from Gray code to binary code.

Arranging Gray codes in order of binary numbers: Value 0 1 3 2 7 6 4 5 15 14 12 13 8 9 11 10

x3x2x1x0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

y3y2y1y0 0000 0001 0011 0010 0111 0110 0100 0101 1111 1110 1100 1101 1000 1001 1011 1010

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.49 Repeat problem 3.48 for behavioral Verilog and/or VHDL. //Verilog Problem 3.49 Gray code to binary converter module Problem3_49_Gray2Binary (xin,yout); input [3:0] xin; //Gray code input output [3:0] yout; //binary output reg [3:0] tint; //internal wire always @(*) case (xin) //Gray Binary Value 4'b0000: tint = 4'b0000; // 0 4'b0001: tint = 4'b0001; // 1 4'b0010: tint = 4'b0011; // 3 4'b0011: tint = 4'b0010; // 2 4'b0100: tint = 4'b0111; // 7 4'b0101: tint = 4'b0110; // 6 4'b0110: tint = 4'b0100; // 4 4'b0111: tint = 4'b0101; // 5 4'b1000: tint = 4'b1111; // 15 4'b1001: tint = 4'b1110; // 14 4'b1010: tint = 4'b1100; // 12 4'b1011: tint = 4'b1101; // 13 4'b1100: tint = 4'b1000; // 8 4'b1101: tint = 4'b1001; // 9 4'b1110: tint = 4'b1011; // 11 4'b1111: tint = 4'b1010; // 10 endcase assign yout = tint; //drive the outputs endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- VHDL Problem 3.49 Gray code to binary converter entity Problem3_49_Gray2Binary is port (xin: in bit_vector(3 downto 0); -- Gray code input yout: out bit_vector(3 downto 0)); -- Binary output end Problem3_49_Gray2Binary; architecture behavior of Problem3_49_Gray2Binary is begin with xin select -- Gray Binary Value yout <= “0000” when “0000”, -- 0 “0001” when “0001”, -- 1 “0011” when “0010”, -- 3 “0010” when “0011”, -- 2 “0111” when “0100”, -- 7 “0110” when “0101”, -- 6 “0100” when “0110”, -- 4 “0101” when “0111”, -- 5 “1111” when “1000”, -- 15 “1110” when “1001”, -- 14 “1100” when “1010”, -- 12 “1101” when “1011”, -- 13 “1000” when “1100”, -- 8 “1001” when “1101”, -- 9 “1011” when “1110”, -- 11 “1010” when “1111”; -- 10 end;

3.50 Design a 4-to-2 bit priority encoder circuit using only NOR gates. The inputs are a3 a2 a1a0 with a3 having the highest priority and a0 the lowest. The outputs are y1 y0 , indicating the highest-priority active input, and G , which indicates that at least one input is active.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.51 Repeat problem 3.50 using behavioral Verilog and/or VHDL. //Verilog Problem 3.51 4-to-2 priority encoder module Problem3_51_PriorityEncoder (a3,a2,a1,a0,y1,y0,G); input a3,a2,a1,a0; output y1,y0,G; assign {G,y1,y0} = (a3 == 1’b0) ? 3’b111 : //a3 active – high priority (a2 == 1’b0) ? 3’b110 : //a2 active (a1 == 1’b0) ? 3’b101 : //a1 active (a0 == 1’b0) ? 3’b100 : //a0 active – low priority 3’b000; //none active (y1y0 don’t care) endmodule --VHDL Problem 3.51 4-to-2 priority encoder library ieee; use ieee.std_logic_1164.all; entity Problem3_51_PriorityEncoder is port (a3,a2,a1,a0: in std_logic; -- active-high inputs y1,y0 : out std_logic; -- number of active input G: out std_logic); -- high if any input(s) active End Problem3_51_PriorityEncoder; architecture behavioral of Problem3_51_PriorityEncoder is signal gyy: std_logic_vector(2 downto 0); begin gyy <= “111” when (a3 = '1') else -- a3 active – high priority “110” when (a2 = '1') else -- a2 active “101” when (a1 = '1') else -- a1 active “100” when (a0 = '1') else -- a0 active – low priority “000”; -- no active inputs G <= gyy(2); y1 <= gyy(1); y0 <= gyy(0); -- drive outputs end;

3.52 Derive logic expressions for the outputs of the AND gates driven by inputs D3 and D6 of the 8-to-1 multiplexer module in Fig. 3.43. Using these expressions, describe the operation of the multiplexer and the function of the strobe (enable) input.

AND gate D3: 𝐷𝐷3 (𝐶𝐶̅ 𝐵𝐵𝐵𝐵)𝐺𝐺̅ = 𝐷𝐷3 (𝑚𝑚3 )𝐺𝐺̅ AND gate D6: 𝐷𝐷6 (𝐶𝐶𝐶𝐶𝐴𝐴̅)𝐺𝐺̅ = 𝐷𝐷6 (𝑚𝑚6 )𝐺𝐺̅

When G = 1, all AND gate outputs are 0 (mux is disabled).

When G = 0, the output of AND gate Di is equal to input Di if selection inputs (C,B,A) correspond to minterm mi. The outputs of the other AND gates will be 0. Therefore, the overall output is equal to input Di.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.53 Write a behavioral Verilog and/or VHDL module describing the functionality of the 8-to-1 multiplexer in Fig. 3.43. //Verilog Problem 3.53 8-to-1 gated multiplexer module Problem3_53_8to1mux (C, B, A, G, D, Y, W); input C, B, A, G; // select and gate inputs input [7:0] D; // data inputs output reg Y; // active-high and active-low outputs output W; always @(*) begin if (G) Y = 1’b0; // mux disabled else case ({C, B, A}) // mux enabled - select input 3’b000: Y = D[{C, B, A}]; 3’b001: Y = D[{C, B, A}]; 3’b010: Y = D[{C, B, A}]; 3’b011: Y = D[{C, B, A}]; 3’b100: Y = D[{C, B, A}]; 3’b101: Y = D[{C, B, A}]; 3’b110: Y = D[{C, B, A}]; 3’b111: Y = D[{C, B, A}]; endcase end endmodule --VHDL Problem 3.53 8-to-1 gated multiplexer library ieee; use ieee.std_logic_1164.all; entity Problem3_53_8to1mux is port (C, B, A, G: in std_logic; -- select and enable inputs D: in std_logic_vector(7 downto 0); -- data inputs Y,W: out std_logic); --active-high and active-low outputs end Problem3_53_8to1mux; architecture equations of Problem3_53_8to1mux is signal S: std_logic_vector(2 downto 0); begin S <= C & B & A; -- select input value Y <= '0' when G = '0' else -- mux disabled D(0) when S = "000" else -- mux enabled – select data input D(1) when S = "001" else D(2) when S = "010" else D(3) when S = "011" else D(4) when S = "100" else D(5) when S = "101" else D(6) when S = "110" else D(7) when S = "111"; W <= not Y; -- active-low output end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.54 Design a 5-to-1 multiplexer circuit, minimizing the number of gates in the circuit as much as possible.

3.55 Write a behavioral Verilog and/or VHDL module to describe the functionality of a 5-to-1 multiplexer. //Verilog Problem 3.55 5-to-1 multiplexer module Problem3_53_5to1mux (C, B, A, D, Y); input C, B, A; // select and gate inputs input [7:0] D; // data inputs output reg Y; // active-high and active-low outputs always @(*) case ({C, B, A}) // select input 3’b000: Y = D[{C, B, A}]; 3’b001: Y = D[{C, B, A}]; 3’b010: Y = D[{C, B, A}]; 3’b011: Y = D[{C, B, A}]; 3’b100: Y = D[{C, B, A}]; endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem 3.55 5-to-1 multiplexer library ieee; use ieee.std_logic_1164.all; entity Problem3_55_5to1mux is port ( S: in std_logic_vector(2 downto 0); -- select inputs D: in std_logic_vector(7 downto 0); -- data inputs Y: out std_logic); -- mux output end Problem3_55_5to1mux; architecture equations of Problem3_55_5to1mux is begin Y <= D(0) when S = "000" else -- select data input D(1) when S = "001" else D(2) when S = "010" else D(3) when S = "011" else D(4) when S = "100"; end;

3.56 Design a three-input/3-bit multiplexer. Use only NAND gates in your realization.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.57 Repeat problem 3.56 using behavioral Verilog and/or VHDL.

//Verilog Problem 3.57 three-input/3-bit multiplexer module Problem3_57 (I0, I1, I2, S1, S0, Y); input [2:0] I0,I1,I2; // three 3-bit inputs input S1, S0; // select inputs output [2:0] Y; // 3-bit output assign Y = {I0[{S1,S0}], I1[{S1,S0}], I2[{S1,S0}]}; // S selects one bit of each input endmodule

--VHDL Problem 3.57 three-input/3-bit multiplexer library ieee; use ieee.std_logic_1164.all; entity Problem3_57 is port ( I0,I1,I2: in std_logic_vector(2 downto 0); -- three 3-bit inputs S: in std_logic_vector(1 downto 0); -- select inputs Y: out std_logic_vector(2 downto 0)); -- 3-bit output end Problem3_57; architecture equations of Problem3_57 is begin Y <= I0(0) & I1(0) & I2(0) when S = "00" else -- select data input I0(1) & I1(1) & I2(1) when S = "01" else I0(2) & I1(2) & I2(2) when S = "10"; end;

3.58 Design an 8-to-1 multiplexer using only 4-to-1 multiplexer modules without enable lines.

(Do not use any additional gates.)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.59 Design a dual (2-bit) 16-input multiplexer using only 8-to-1 multiplexer modules, OR gates, and inverters.

3.60 Write a behavioral Verilog and/or VHDL model of an 8-to-1 multiplexer. Then write a model of a 2-bit, 16-to-1 multiplexer that uses the 8-to-1 multiplexer as a component. //Verilog Problem 3.60 8-to-1 multiplexer module Problem3_60_Mux8to1 (C, B, A, I, Y); input C, B, A; // select and gate inputs input [7:0] I; // data inputs output Y; // mux output assign Y = I[{C,B,A}]; endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Verilog Problem 3.60 2-bit 16-to-1 multiplexer module Problem3_60_Mux16to1_2bit (D, C, B, A, D0, D1, Y0, Y1); input D, C, B, A; // select and gate inputs input [15:0] D0, D1; // data inputs output Y0, Y1; // active-high output wire Y00, Y01, Y10, Y11; Problem3_60_Mux8to1 m1 (.C(C), .B(B), .A(A), .I(D0[7:0]), .Y(Y00)); Problem3_60_Mux8to1 m2 (.C(C), .B(B), .A(A), .I(D0[15:8]), .Y(Y01)); Problem3_60_Mux8to1 m3 (.C(C), .B(B), .A(A), .I(D1[7:0]), .Y(Y10)); Problem3_60_Mux8to1 m4 (.C(C), .B(B), .A(A), .I(D1[15:8]), .Y(Y11)); assign {Y1,Y0} = (D == 0) ? {Y00,Y01} : {Y10,Y11}; endmodule --VHDL Problem 3.60 8-to-1 multiplexer library ieee; use ieee.std_logic_1164.all; entity Problem3-60_Mux8to1 is port (C, B, A: in std_logic; -- select input I: in std_logic_vector(7 downto 0); -- data inputs Y: out std_logic); -- outputs end Problem3-60_Mux8to1; architecture equations of Problem3-60_Mux8to1 is signal S: std_logic_vector(2 downto 0); begin S <= C & B & A; -- select input value Y <= I(0) when S = "000" else -- select data input I(1) when S = "001" else I(2) when S = "010" else I(3) when S = "011" else I(4) when S = "100" else I(5) when S = "101" else I(6) when S = "110" else I(7) when S = "111"; end; --VHDL Problem 3.60 2-bit 16-to-1 multiplexer library ieee; use ieee.std_logic_1164.all; entity Problem3_60_Mux16to1_2Bit is port (D, C, B, A: in std_logic; -- select input D0,D1: in std_logic_vector(15 downto 0); -- data inputs Y0,Y1: out std_logic); -- outputs end Problem3_60_Mux16to1_2Bit; architecture equations of Problem3_60_Mux16to1_2Bit is component Problem3-60_Mux8to1 is port (C, B, A: in std_logic; -- select input I: in std_logic_vector(7 downto 0); -- data inputs Y: out std_logic); -- outputs end component;

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Digital Logic Circuit Analysis and Design, 2nd Edition

begin M1: M2: M3: M4:

end;

signal Y00,Y01,Y10,Y11: std_logic; Problem3-60_Mux8to1 port map( C, B, A, D0(7 downto 0), Y00); Problem3-60_Mux8to1 port map( C, B, A, D0(15 downto 8), Y01); Problem3-60_Mux8to1 port map( C, B, A, D1(7 downto 0), Y10); Problem3-60_Mux8to1 port map( C, B, A, D1(15 downto 8), Y11);

with D select Y0 <= Y00 when ‘0’, Y10 when others; with D select Y1 <= Y01 when ‘0’, Y11 when others;

3.61 Realize each of the following functions with a 4-to-1 multiplexer module. (a)𝑓𝑓1 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∑ 𝑚𝑚(2,4,5,7) = 𝑎𝑎�𝑏𝑏𝑐𝑐̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐 + 𝑎𝑎𝑎𝑎𝑎𝑎 = �𝑎𝑎�𝑏𝑏�� ∙ 0 + (𝑎𝑎�𝑏𝑏)𝑐𝑐̅ + (𝑎𝑎𝑏𝑏�) ∙ 1 + (𝑎𝑎𝑎𝑎)𝑐𝑐

(b) 𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = ∏ 𝑀𝑀(0,6,7) = ∑ 𝑚𝑚(1,2,3,4,5)

= 𝑎𝑎�𝑏𝑏�𝑐𝑐 + 𝑎𝑎�𝑏𝑏𝑐𝑐̅ + 𝑎𝑎�𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐 = �𝑎𝑎�𝑏𝑏��𝑐𝑐 + (𝑎𝑎�𝑏𝑏) ∙ 1 + (𝑎𝑎𝑏𝑏�) ∙ 1 + (𝑎𝑎𝑎𝑎) ∙ 0

(c) 𝑓𝑓3 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = (𝑎𝑎 + 𝑏𝑏�)(𝑏𝑏� + 𝑐𝑐)

= (𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐̅)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎� + 𝑏𝑏� + 𝑐𝑐)(𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐) = ∏ 𝑀𝑀(2,3,6, ) = ∑ 𝑚𝑚(0,1,4,5,7) = 𝑎𝑎�𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐 + 𝑎𝑎𝑎𝑎𝑎𝑎 = �𝑎𝑎�𝑏𝑏�� ∙ 1 + (𝑎𝑎�𝑏𝑏) ∙ 0 + (𝑎𝑎𝑏𝑏�) ∙ 1 + (𝑎𝑎𝑎𝑎)𝑐𝑐

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.62 Realize each of the following functions with an 8-to-1 multiplexer module. (a)𝑓𝑓(𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∑ 𝑚𝑚(0,2,3,5,7)

(b)𝑓𝑓(𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑐𝑐̅ + 𝑏𝑏 = �𝑏𝑏 + 𝑐𝑐̅ + 𝑑𝑑̅�(𝑏𝑏 + 𝑐𝑐̅ + 𝑑𝑑) = ∏ 𝑀𝑀(2,3) = ∑ 𝑚𝑚(0,1,4,5,7)

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) f(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = ∏ 𝑀𝑀(0,1,2,3,6,7,8,9,12,14,15)

3.63 Find the minterm list of the function f ( A, B, C , D) realized by the circuit below.

𝑌𝑌0 = (𝐴𝐴̅ ⊕ 0)(𝐵𝐵�𝐶𝐶̅ ) + 𝐴𝐴̅(𝐵𝐵�𝐶𝐶) + 𝐴𝐴(𝐵𝐵𝐶𝐶̅ ) + (𝐴𝐴 ⊕ 1)(𝐵𝐵𝐵𝐵) = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵

𝑌𝑌1 = (𝐴𝐴̅ ⊕ 𝐴𝐴)(𝐵𝐵�𝐶𝐶̅ ) + 1(𝐵𝐵�𝐶𝐶) + 0(𝐵𝐵𝐶𝐶̅ ) + (𝐴𝐴̅ ⊕ 1)𝐵𝐵𝐵𝐵 = 𝐵𝐵�𝐶𝐶̅ + 𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴

� + 𝑌𝑌1 𝐷𝐷 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑌𝑌0 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 � = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ 𝐷𝐷 ̅ ̅ ̅ ̅ � � � � +𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 = 𝛴𝛴𝛴𝛴(0,1,2,3,6,9,11,12,15)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.64 Find the minterms of the function f ( A, B, C , D) realized by the following circuit.

𝑌𝑌0 = 0 ∙ 𝐵𝐵� + 1 ∙ 𝐵𝐵 = 𝐵𝐵 𝑌𝑌1 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴̅𝐵𝐵 𝑌𝑌2 = 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐴𝐴 𝑌𝑌3 = 1 ∙ 𝐵𝐵� + 0 ∙ 𝐵𝐵 = 𝐵𝐵�

𝑌𝑌4 = 𝑌𝑌0 𝐶𝐶̅ + 𝑌𝑌1 𝐶𝐶 = 𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵 = 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐵𝐵�𝐶𝐶 + 𝐴𝐴̅𝐵𝐵𝐵𝐵

𝑌𝑌5 = 𝑌𝑌2 𝐶𝐶̅ + 𝑌𝑌3 𝐶𝐶 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐵𝐵�𝐶𝐶 = 𝐴𝐴̅𝐵𝐵�𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵�𝐶𝐶 + 𝐴𝐴𝐵𝐵�𝐶𝐶

� + 𝑌𝑌5 𝐷𝐷 𝑓𝑓(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝑌𝑌4 𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐵𝐵�𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵𝐵𝐵𝐷𝐷 � = 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ 𝐷𝐷 ̅ ̅ ̅ ̅ � � � +𝐴𝐴𝐵𝐵𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐶𝐶 𝐷𝐷 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶 + 𝐴𝐴𝐵𝐵𝐶𝐶𝐶𝐶 = 𝛴𝛴𝛴𝛴(1,3,4,6,10,11,12,13)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.65 Find the minterms of the function realized by the circuit below.

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = 𝐷𝐷0�𝑎𝑎�𝑏𝑏�𝑐𝑐̅� + 𝐷𝐷1�𝑎𝑎�𝑏𝑏�𝑐𝑐� + 𝐷𝐷2(𝑎𝑎�𝑏𝑏𝑐𝑐̅) + 𝐷𝐷3(𝑎𝑎�𝑏𝑏𝑏𝑏) +𝐷𝐷4�𝑎𝑎𝑏𝑏�𝑐𝑐̅� + 𝐷𝐷5�𝑎𝑎𝑏𝑏�𝑐𝑐� + 𝐷𝐷6(𝑎𝑎𝑎𝑎𝑐𝑐̅) + 𝐷𝐷7(𝑎𝑎𝑎𝑎𝑎𝑎) 𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐) = (𝑎𝑎�𝑏𝑏�)�𝑎𝑎�𝑏𝑏�𝑐𝑐̅� + (𝑎𝑎�𝑏𝑏)�𝑎𝑎�𝑏𝑏�𝑐𝑐� + (𝑎𝑎𝑏𝑏�)(𝑎𝑎�𝑏𝑏𝑐𝑐̅) + (𝑎𝑎𝑎𝑎)(𝑎𝑎�𝑏𝑏𝑏𝑏) +(𝑐𝑐̅𝑏𝑏�)�𝑎𝑎𝑏𝑏�𝑐𝑐̅� + (𝑐𝑐̅𝑏𝑏)�𝑎𝑎𝑏𝑏�𝑐𝑐� + (𝑐𝑐𝑏𝑏�)(𝑎𝑎𝑎𝑎𝑐𝑐̅) + (𝑐𝑐𝑐𝑐)(𝑎𝑎𝑎𝑎𝑎𝑎) = 𝑎𝑎�𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎𝑎𝑎𝑎𝑎 = 𝛴𝛴𝛴𝛴(0,4,7)

3.66 Determine the function realized by the circuit below in minterm list form. Consider B to be the MSB for the multiplexer.

𝑆𝑆 = 𝑎𝑎 ⊕ 𝑏𝑏 ⊕ 1 = ������������� �𝑎𝑎𝑏𝑏� + 𝑎𝑎�𝑏𝑏� ∙ 1 + �𝑎𝑎𝑏𝑏� + 𝑎𝑎�𝑏𝑏� ∙ 0 = 𝑎𝑎�𝑏𝑏� + 𝑎𝑎𝑎𝑎 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = 𝑎𝑎𝑎𝑎 + 𝑎𝑎 ∙ 1 + 𝑏𝑏 ∙ 1 = 𝑎𝑎 + 𝑏𝑏 ������� + 𝑏𝑏 = 𝑎𝑎�𝑏𝑏� 𝐶𝐶̅ 𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑎𝑎 𝑆𝑆 ⊕ 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = ������������� �𝑎𝑎�𝑏𝑏� + 𝑎𝑎𝑎𝑎�(𝑎𝑎 + 𝑏𝑏) + (𝑎𝑎�𝑏𝑏� + 𝑎𝑎𝑎𝑎)(𝑎𝑎 + 𝑏𝑏) = �𝑎𝑎𝑏𝑏� + 𝑎𝑎�𝑏𝑏�(𝑎𝑎 + 𝑏𝑏) + (𝑎𝑎�𝑏𝑏� + 𝑎𝑎𝑎𝑎)𝑎𝑎�𝑏𝑏� = 𝑎𝑎𝑏𝑏� + 𝑎𝑎�𝑏𝑏 + 𝑎𝑎�𝑏𝑏� = 𝑎𝑎� + 𝑏𝑏� 𝑆𝑆 ⊕ 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = 𝑎𝑎� + 𝑏𝑏� = 𝑎𝑎𝑎𝑎

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝐷𝐷0�𝑐𝑐̅𝑑𝑑̅� + 𝐷𝐷1(𝑐𝑐̅𝑑𝑑) + 𝐷𝐷2�𝑐𝑐𝑑𝑑̅� + 𝐷𝐷3(𝑐𝑐𝑐𝑐) = (𝑎𝑎𝑎𝑎)(𝑐𝑐̅𝑑𝑑̅) + (𝑎𝑎� + 𝑏𝑏�)(𝑐𝑐̅𝑑𝑑) + (𝑎𝑎 + 𝑏𝑏)�𝑐𝑐𝑑𝑑̅� + (𝑎𝑎�𝑏𝑏�)(𝑐𝑐𝑐𝑐) = 𝑎𝑎𝑎𝑎𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎�𝑐𝑐̅𝑑𝑑 + 𝑏𝑏�𝑐𝑐̅𝑑𝑑 + 𝑎𝑎𝑎𝑎𝑑𝑑̅ + 𝑏𝑏𝑏𝑏𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐𝑐𝑐 = 𝑎𝑎𝑎𝑎𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐̅𝑑𝑑 + 𝑎𝑎�𝑏𝑏𝑐𝑐̅𝑑𝑑 + 𝑎𝑎�𝑏𝑏�𝑐𝑐̅𝑑𝑑 + 𝑎𝑎𝑏𝑏�𝑐𝑐̅𝑑𝑑 + 𝑎𝑎𝑏𝑏�𝑐𝑐𝑑𝑑̅ + 𝑎𝑎𝑎𝑎𝑎𝑎𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏𝑏𝑏𝑑𝑑̅ + 𝑎𝑎𝑎𝑎𝑎𝑎𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐𝑐𝑐 = 𝛴𝛴𝛴𝛴(1,3,5,6,9,10,12,14)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.67 Given the circuit below, derive the output f (a, b, c, d ) in minterm list form. Consider B to be the MSB for both the decoder and the multiplexer. Assume positive logic (active-high inputs and outputs).

𝑓𝑓(𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝐷𝐷0�𝑐𝑐̅𝑑𝑑̅� + 𝐷𝐷1(𝑐𝑐̅𝑑𝑑) + 𝐷𝐷2�𝑐𝑐𝑑𝑑̅� + 𝐷𝐷3(𝑐𝑐𝑐𝑐) = 𝑎𝑎�𝑏𝑏�𝑐𝑐̅𝑑𝑑̅ + 𝑎𝑎�𝑏𝑏𝑐𝑐̅𝑑𝑑 + 𝑎𝑎𝑏𝑏�𝑐𝑐𝑑𝑑̅ + 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 = 𝛴𝛴𝛴𝛴(0,5,10,15)

3.68 Design a full adder module with data inputs A and B, carry input Cin, sum output S, and carry output Cout.

A B Cin 000 001 010 011 100 101 110 111 (a) Use a 3-to-8 decoder and NAND gates

Cout S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 (b) Use a four-input, 2-bit multiplexer

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.69 Three temperature sensors, shown below, indicate measured temperature with 8-bit binary values on their output lines, T7 to T0 . Show with a block diagram how to use multiplexer modules to allow an 8-bit microprocessor to read any one of these sensors using its data input lines, D7 to D0 , by issuing a 2-bit address, A1 A0 .

3.70 Design a 2-bit adder circuit using a two-level NAND gate circuit for each output. The inputs are the 2-bit binary numbers a1a0 and b1b0 . The outputs are the 2-bit binary sum s1s0 and the carry output c1 . a3a2 b1b0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

c1 s1 s0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.71 Design a 16-bit ripple-carry adder using 2-bit adder modules like the one designed in Problem 3.70. Compute add time in terms of gate delay, tg. Compare the add time to that of a 16-bit ripple-carry adder.

Assume a carry input is added to the module designed in Problem 3.70, to permit modules to be cascaded, with carry output of one module connected to the carry input of the next, forming a ripple carry adder. Each carry bit is produced after two gate delays, so the output of first state is valid after 2tg, after which the output of the second module is valid after another 2tg, and so on, with the output of the 8th stage valid after 8 × 2tg = 16tg.

3.72 Using only half-adders, design a circuit that will add 3 bits, xi , yi , zi , together, producing carry and sum bits ci , si as shown in the following table.

xi 0 0 0 0 1 1 1 1

yi 0 0 1 1 0 0 1 1

zi 0 1 0 1 0 1 0 1

ci 0 0 0 1 0 1 1 1

si 0 1 1 0 1 0 0 1

𝑠𝑠𝑖𝑖 = 𝑥𝑥𝑖𝑖 ⊕ 𝑦𝑦𝑖𝑖 ⊕ 𝑧𝑧𝑖𝑖 = ∑ 𝑚𝑚(1,2,4,7)

𝑐𝑐𝑖𝑖 = (𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 ) ⊕ (𝑥𝑥𝑖𝑖 ⊕ 𝑦𝑦𝑖𝑖 )𝑧𝑧𝑖𝑖 = (𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 ) ⊕ (𝑥𝑥𝑖𝑖 𝑦𝑦�𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥̅𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧𝑖𝑖 ) = (𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 )(𝑥𝑥𝑖𝑖 𝑦𝑦�𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥̅𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧𝑖𝑖 ) + (𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 )(𝑥𝑥𝑖𝑖 𝑦𝑦�𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥̅𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧𝑖𝑖 ) = 𝑥𝑥𝑖𝑖 𝑦𝑦�𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥̅𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 = 𝑥𝑥𝑖𝑖 𝑦𝑦�𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥̅𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧𝑖𝑖 + 𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧̅𝑖𝑖 + 𝑥𝑥𝑖𝑖 𝑦𝑦𝑖𝑖 𝑧𝑧𝑖𝑖 = ∑ 𝑚𝑚(3,5,6,7)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.73 Design a 4-bit full-adder using carry look-ahead, rather than ripple carry. 𝑔𝑔𝑖𝑖 = 𝑎𝑎𝑖𝑖 𝑏𝑏𝑖𝑖 (generate) 𝑝𝑝𝑖𝑖 = 𝑎𝑎𝑖𝑖 ⊕ 𝑏𝑏𝑖𝑖 (propagate)

𝑐𝑐0 = 𝑔𝑔0 + 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖 𝑐𝑐1 = 𝑔𝑔1 + 𝑝𝑝1 𝑐𝑐0 = 𝑔𝑔1 + 𝑝𝑝1 (𝑔𝑔0 + 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖 ) = 𝑔𝑔1 + 𝑝𝑝1 𝑔𝑔0 + 𝑝𝑝1 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖 𝑐𝑐2 = 𝑔𝑔2 + 𝑝𝑝2 𝑐𝑐1 = 𝑔𝑔2 + 𝑝𝑝2 (𝑔𝑔1 + 𝑝𝑝1 𝑔𝑔0 + 𝑝𝑝1 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖 ) = 𝑔𝑔2 + 𝑝𝑝2 𝑔𝑔1 + 𝑝𝑝2 𝑝𝑝1 𝑔𝑔0 + 𝑝𝑝2 𝑝𝑝1 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖 𝑐𝑐3 = 𝑔𝑔3 + 𝑝𝑝3 𝑐𝑐2 = 𝑔𝑔3 + 𝑝𝑝3 (𝑔𝑔2 + 𝑝𝑝2 𝑔𝑔1 + 𝑝𝑝2 𝑝𝑝1 𝑔𝑔0 + 𝑝𝑝2 𝑝𝑝1 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖 ) = 𝑔𝑔3 + 𝑝𝑝3 𝑔𝑔2 + 𝑝𝑝3 𝑝𝑝2 𝑔𝑔1 + 𝑝𝑝3 𝑝𝑝2 𝑝𝑝1 𝑔𝑔0 + 𝑝𝑝3 𝑝𝑝2 𝑝𝑝1 𝑝𝑝0 𝑐𝑐𝑖𝑖𝑖𝑖

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.74 Design a 1-bit full-subtracter module, using only NOR gates, and then construct a 4-bit subtracter using only these modules. x y bin 000 001 010 011 100 101 110 111

bout d 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 1

3.75 Describe the overflow condition as applied to two's complement addition and subtraction.

An overflow condition implies a result that is out of range. Let us assume that A and B are positive, n-bit values. (a) The maximum positive n-bit value is 2n-1 – 1. Note that bit (n-1) is 0 for positive values. If A + B ≥ 2n-1 – 1, then bit (n-1) will be 1, indicating an erroneous negative two’s complement value. Therefore, adding two n-bit positive values and producing a negative n-bit result indicates an overflow condition. (b) The maximum negative n-bit value is -2n-1 . Note that bit (n-1) is 1 for negative values. If -A - B < -2n-1, then bit (n-1) will be 0, indicating an erroneous positive two’s complement value.

Therefore, adding two n-bit negative values and producing a positive n-bit result indicates an overflow condition. (c) No overflow can be generated for A – B or B – A, since the magnitude of the result cannot be greater than both A and B.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.76 Design an overflow detection circuit for Fig. 3.54, assuming that the unit is to be used to add and subtract numbers in a 4-bit two's complement number system.

Referring to Fig. 3.54, overflow conditions exist when adder inputs A4 = B4 = 0 and ∑4 = 1 (adding two positive numbers produces a negative result), or when A4 = B4 = 1 and ∑4 = 0 (adding two negative numbers produces a positive result.

3.77 The four-bit adder module described in Fig. 3.54 is faster than a four-bit ripple-carry adder because the carry for each stage is calculated from all the inputs, rather than being propagated through each stage. Find the equation for the four-bit adder internal carry C 2 in terms of only the A(i ) , B(i ) , and C 0 inputs. Using A2A1 , B 2B1 , and C 0 as the numbers being added together to determine the carry (with A2 and B 2 as MSBs), find the combinations of ( A2, A1, B 2, B1, C 0) that result in C 2 = 1 . (Find the minterms for C 2 .) 𝐶𝐶2 = (𝐴𝐴2 + 𝐵𝐵2) + (𝐴𝐴2 ⋅ 𝐵𝐵2) ⋅ (𝐴𝐴1 ⋅ 𝐵𝐵1) + (𝐴𝐴2 ∙ 𝐵𝐵2) ⋅ (𝐴𝐴1 ⋅ 𝐵𝐵1) ∙ 𝐶𝐶0

= (𝐴𝐴2 + 𝐵𝐵2) ⋅ �(𝐴𝐴2 ⋅ 𝐵𝐵2) ⋅ (𝐴𝐴1 + 𝐵𝐵1)� ⋅ �(𝐴𝐴2 ∙ 𝐵𝐵2) ⋅ (𝐴𝐴1 ⋅ 𝐵𝐵1) ∙ 𝐶𝐶0�

= (𝐴𝐴2 + 𝐵𝐵2) ⋅ [𝐴𝐴2𝐵𝐵2 + 𝐴𝐴1 + 𝐵𝐵1] ⋅ [𝐴𝐴2𝐵𝐵2 + 𝐴𝐴1𝐵𝐵1 + 𝐶𝐶0] = (𝐴𝐴2 + 𝐵𝐵2) ⋅ (𝐴𝐴2𝐵𝐵2 + 𝐴𝐴1𝐵𝐵1 + 𝐴𝐴1𝐶𝐶0 + 𝐵𝐵1𝐶𝐶0) = 𝐴𝐴2𝐵𝐵2 + 𝐴𝐴2𝐴𝐴1𝐵𝐵1 + 𝐴𝐴2𝐴𝐴1𝐶𝐶0 + 𝐴𝐴2𝐵𝐵1𝐶𝐶0 + 𝐵𝐵2𝐴𝐴1𝐵𝐵1 + 𝐵𝐵2𝐴𝐴1𝐶𝐶0 + 𝐵𝐵2𝐵𝐵1𝐶𝐶0 = 𝐴𝐴2𝐵𝐵2 + 𝐴𝐴2𝐴𝐴1𝐶𝐶0 + 𝐴𝐴2𝐵𝐵1𝐶𝐶0 + 𝐵𝐵2𝐴𝐴1𝐶𝐶0 + 𝐵𝐵2𝐵𝐵1𝐶𝐶0

Minterms of function C2 can be easily identified by plotting the functionon a K-map.

𝑓𝑓(𝐴𝐴2, 𝐴𝐴1, 𝐵𝐵2, 𝐵𝐵1, 𝐶𝐶0) = � 𝑚𝑚(7,13,14,15,19,20 − 23, 25 − 31)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.78 Design a BCD adder that adds two unsigned BCD digits and produces a BCD result and a carry output. Implement your design using NAND gates.

6 must be added to the 4-bit binary sum if greater than 9, since 6 is the difference between a carry in base 10 and a carry in base 16. The condition for adding 6 is thus either a carry out of the 4-bit binary adder, or a sum between 10 and 15, inclusive. The following uses the 4-bit binary adder from Figure 3.54.

3.79 Write a behavioral Verilog and/or VHDL model of a two-digit BCD adder. //Verilog Problem 3.79: 2-digit BCD adder module Problem3_79_BCDadder (A, B, S, Cout); input [3:0] A, B; // BCD inputs inputs output [3:0] S; // BCD output output Cout; // carry output wire [4:0] Sbin,Sbcd; assign Sbin = A + B; //binary sum – bit 5 is carry assign Sbcd = (Sbin > 5’d9) ? Sbin + 4’d6 : Sbin; //add 6 if > 9 assign S = Sbcd[3:0]; // low 4 bits are BCD result assign Cout = Sbcd[4]; // bit 5 is BCD carry endmodule --VHDL Problem 3.79: 2-digit BCD adder library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Problem3_79_BCDadder is port (A,B: in std_logic_vector(3 downto 0); -- BCD inputs S: out std_logic_vector(3 downto 0); -- BCD output Cout: out std_logic); -- carry output end Problem3_79_BCDadder;

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Digital Logic Circuit Analysis and Design, 2nd Edition

architecture behavior of Problem3_79_BCDadder is signal Sbin,Sbcd: unsigned(4 downto 0); begin Sbin <= unsigned(‘0’ & A) + unsigned(B); -- 5-bit binary sum Sbcd <= Sbin when (Sbin < 10) else Sbin + 6; -- add 6 if > 9 S <= std_logic_vector(Sbcd(3 downto 0)); -- sum is low 4 bits Cout <= Sbcd(4); -- carry is 5th bit end;

3.80 Design a 3-bit magnitude comparator with inputs A = (a2 a1a0 ) 2 and B = (b2b1b0 ) 2 and with three outputs: EQ( A = B ), GT ( A > B ) , and LT ( A < B) . Implement your design with NAND and/or NOR gates. 𝐴𝐴 = 𝐵𝐵 ⇒ (𝑎𝑎2 ⊕ 𝑏𝑏2 )(𝑎𝑎1 ⊕ 𝑏𝑏1 )(𝑎𝑎0 ⊕ 𝑏𝑏0 ) 𝐴𝐴 > 𝐵𝐵 ⇒ 𝑎𝑎2 𝑏𝑏�2 + �𝑎𝑎2 ⊕ 𝑏𝑏2 �(𝑎𝑎1 𝑏𝑏�1 ) + (𝑎𝑎2 ⊕ 𝑏𝑏2 )(𝑎𝑎1 ⊕ 𝑏𝑏1 )(𝑎𝑎0 𝑏𝑏�0 ) 𝐴𝐴 < 𝐵𝐵 ⇒ 𝑎𝑎�2 𝑏𝑏2 + �𝑎𝑎2 ⊕ 𝑏𝑏2 �(𝑎𝑎�1 𝑏𝑏1 ) + (𝑎𝑎2 ⊕ 𝑏𝑏2 )(𝑎𝑎1 ⊕ 𝑏𝑏1 )(𝑎𝑎�0 𝑏𝑏0 )

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.81 Write a Verilog and/or VHDL model of a 3-bit magnitude comparator as above. //Verilog Problem 3.81: 3-bit magnitude comparator module Problem3_81_Comparator (A, B, EQ, GT, LT); input [2:0] A, B; // BCD inputs inputs output EQ, LT, GT; // carry output assign EQ = ~(A[2] ^ B[2]) & ~(A[1] ^ B[1]) & ~(A[0] ^ B[0]); assign GT = (A[2] & ~B[2]) | ~(A[2] ^ B[2]) & (A[1] & ~B[1]) | ~(A[2] ^ B[2]) & ~(A[1] ^ B[1]) & (A[0] & ~B[0]); assign LT = (~A[2] & B[2]) | ~(A[2] ^ B[2]) & (~A[1] & B[1]) | ~(A[2] ^ B[2]) & ~(A[1] ^ B[1]) & (~A[0] & B[0]); endmodule --VHDL Problem 3.81: 3-bit magnitude comparator library ieee; use ieee.std_logic_1164.all; entity Problem3_81_Comparator is port (A,B: in std_logic_vector(2 downto 0); -- 3-bit inputs EQ, GT, LT: out std_logic); -- compare results end Problem3_81_Comparator; architecture equations of Problem3_81_Comparator is begin EQ <= (A(2) xnor B(2)) and (A(1) xnor B(1)) and (A(0) xnor B(0)); GT <= (A(2) and not B(2)) or ((A(2) xnor B(2)) and (A(1) and not B(1))) or ((A(2) xnor B(2)) and (A(1) xnor B(1)) and (A(0) and not B(0))); LT <= (not A(2) and B(2)) or ((A(2) xnor B(2)) and (not A(1) and B(1))) or ((A(2) xnor B(2)) and (A(1) xnor B(1)) and (not A(0) and B(0))); end;

3.82 With appropriate gating and one 4-bit magnitude comparator, design a circuit that compares two 5-bit binary numbers A = (a4  a0 ) and B = (b4  b0 ) with f 3 = 1 when

A > B , f 2 = 1 when A = B , and f1 = 1 when A < B . ( Hint: Use the cascade inputs to compare the two most significant digits.)

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.83 Design a logic circuit to compare three 4-bit numbers X = ( x3 x2 x1 x0 ) 2 , Y = ( y3 y2 y1 y0 ) 2 , and

Z = ( z3 z 2 z1 z0 ) 2 that has the functionality described in the table below. Use four-bit magnitude comparators and logic gates to realize the circuit.

Condition

X >Y > Z X > Z >Y Y >X >Z Y >Z>X Z > X >Y Z >Y > X X =Y = Z Any other case

f0 1 0 0 0 0 0 0 0

f1 0 1 0 0 0 0 0 0

f2 0 0 1 0 0 0 0 0

f3 0 0 0 1 0 0 0 0

f4 0 0 0 0 1 0 0 0

f5 0 0 0 0 0 1 0 0

f6 0 0 0 0 0 0 1 0

f7 0 0 0 0 0 0 0 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.84 Write a Verilog and/or VHDL behavioral model of the comparator described in problem 3.83. //Verilog Problem 3.84: 3-number comparator module Problem3_84_CompareXYZ (X, Y, Z, F); input [3:0] X, Y, Z; // 4-bit inputs output reg [7:0] F; // Function outputs always @(*) begin if ((X > Y) && (Y > Z)) F = 8’b00000001; else // X > Y > Z if ((X > Z) && (Z > Y)) F = 8’b00000010; else // X > Z > Y if ((Y > X) && (X > Z)) F = 8’b00000100; else // Y > X > Z if ((Y > Z) && (Z > X)) F = 8’b00001000; else // Y > Z > X if ((Z > X) && (X > Y)) F = 8’b00010000; else // Z > X > Y if ((Z > Y) && (Y > X)) F = 8’b00100000; else // Z > Y > X if ((X == Y) && (Y == Z)) F = 8’b01000000; else // X = Y = Z F = 8’b10000000; // other end; endmodule --VHDL Problem 3.84: 3.84: 3-number comparator library ieee; use ieee.std_logic_1164.all; entity Problem3_84_CompareXYZ is port (X,Y,Z: in std_logic_vector(3 downto 0); -- 4-bit inputs F: out std_logic_vector(7 downto 0)); -- 8 function outputs end Problem3_84_CompareXYZ; architecture equations of Problem3_84_CompareXYZ is begin F <= “00000001” when ((X > Y) and (Y > Z)) else -- X > Y > Z “00000010” when ((X > Z) and (Z > Y)) else -- X > Z > Y “00000100” when ((Y > X) and (X > Z)) else -- Y > X > Z “00001000” when ((Y > Z) and (Z > X)) else -- Y > Z > X “00010000” when ((Z > X) and (X > Y)) else -- Z > X > Y “00100000” when ((Z > Y) and (Y > X)) else -- Z > Y > X “01000000” when ((X = Y) and (Y = Z)) else -- X = Y = Z -- other “10000000”; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.85 Design a logic circuit that multiplies two 2-bit numbers, (a1a0 ) 2 and (b1b0 ) 2 , using only NAND gates. The product should be a 4-bit number ( p3 p2 p1 p0 ) 2 . a1a0 b1b0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

p3p2p1p0 0000 0000 0000 0000 0000 0001 0010 0011 0000 0010 0100 0110 0000 0011 0110 1001

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.86 Design a logic circuit that multiplies two 4-bit numbers, (a3 a2 a1a0 ) 2 and (b3b2b1b0 ) 2 , using only AND gates and half- and full-adder modules. The product should be an 8-bit number ( p7 p6 p5 p4 p3 p2 p1 p0 ) 2 . ×

a3b3 p3 p2

a3b1 a3b2 a2b2 a2b3 a1b3 p1 p0

a3 b3 a3b0 a2b1 a1b2 a0b3 p3

a2 b2 a2b0 a1b1 a0b2

a1 a0 b1 b0 a1b0 a0b0 a0b1

p2

p1

p0

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.87 Design a logic circuit to test the equality of two 4-bit numbers, (a3 a2 a1a0 ) 2 and (b3b2b1b0 ) 2 .

The circuit output, e, should be 0 when the numbers are equal and 1 when they are not.

Draw a circuit diagram. 𝑒𝑒 = (𝑎𝑎3 ⊕ 𝑏𝑏3 ) + (𝑎𝑎2 ⊕ 𝑏𝑏2 ) + (𝑎𝑎1 ⊕ 𝑏𝑏1 ) + (𝑎𝑎0 ⊕ 𝑏𝑏0 )

3.88 Write a Verilog and/or VHDL model for problem 3.87. //Verilog Problem 3.88: 4-bit equality checker module Problem3_88_EqualAB (A, B, e); input [3:0] A, B; // 4-bit inputs output e; // equality output assign e = (A[3] ^ B[3]) | (A[2] ^ B[2]) | (A[1] ^ B[1]) | (A[0] ^ B[0]); endmodule --VHDL Problem 3.88: 4-bit equality checker library ieee; use ieee.std_logic_1164.all; entity Problem3_88_EqualAB is port (A,B: in std_logic_vector(3 downto 0); -- 4-bit inputs e: out std_logic); -- equality output end Problem3_88_EqualAB; architecture equations of Problem3_88_EqualAB is begin e <= (A(3) xor B(3)) or (A(2) xor B(2)) or (A(1) xor B(1)) or (A(0) xor B(0)); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.89 Design a decoder that converts unsigned 4-bit binary numbers to two BCD digits that represent the decimal value of the binary number. Describe your design as a Verilog and/or VHDL module. a3a2a1a0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

b7b6b5b4 b3b2b1b0 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Verilog Problem 3.89: 4-bit binary to 2-digit BCD module Problem3_89_Bin2BCD (A, B); input [3:0] A; // 4-bit binary input output [7:0] B; // 2-digit BCD output assign B[0] = A[0]; assign B[1] = (~A[3] & A[1]) | (A[3] & A[2] & ~A[1]); assign B[2] = (~A[3] & A[2]) | (A[2] & A[1]); assign B[3] = A[3] & ~A[2] & ~A[1]; assign B[4] = (A[3] & A[2]) | (A[3] & A[1]); assign B[7:5] = 3’b000; endmodule --VHDL Problem 3.89: 4-bit binary to 2-digit BCD library ieee; use ieee.std_logic_1164.all; entity Problem3_89_Bin2BCD is port (A: in std_logic_vector(3 downto 0); -- 4-bit binary input B: out std_logic_vector(7 downto 0)); -- 2-digit BCD output end Problem3_89_Bin2BCD; architecture equations of Problem3_89_Bin2BCD is signal S: std_logic_vector(4 downto 1); begin S(1) <= (not A(3) and A(1)) or (A(3) and A(2) and not A(1)); S(2) <= (not A(3) and A(2)) or (A(2) and A(1)); S(3) <= A(3) and not A(2) and not A(1); S(4) <= (A(3) and A(2)) or (A(3) and A(1)); B <= “000” & S & A(0); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.90 Design a decoder that converts unsigned 4-bit binary numbers to codes for displaying the decimal value of the binary number on two seven-segment displays. Leading zeros should be displayed as a blank display. Describe your design as Verilog and/or VHDL modules.

Let us assume that the display has active-low segment driver signals. The decoder output will have a BCD units digit, and a BCD tens digit that is either 0 or 1. //Verilog Problem 3.90: Four-Bit Binary to Two-Digit BCD Decoder Active Low module Problem3_90_Bin2BCDSegments ( input [3:0] binary, // 4-bit binary input output reg [6:0] d1, d0); // Tens and units 7-segment outputs always @ (binary [3:0]) case (binary [3:0]) // abcdefg abcdefg 4'b0000: begin d1 = 7'b1111111; d0 = 7'b0000001; end // 0 4'b0001: begin d1 = 7'b1111111; d0 = 7'b1001111; end // 1 4'b0010: begin d1 = 7'b1111111; d0 = 7'b0010010; end // 2 4'b0011: begin d1 = 7'b1111111; d0 = 7'b0000110; end // 3 4'b0100: begin d1 = 7'b1111111; d0 = 7'b1001100; end // 4 4'b0101: begin d1 = 7'b1111111; d0 = 7'b0100100; end // 5 4'b0110: begin d1 = 7'b1111111; d0 = 7'b0100000; end // 6 4'b0111: begin d1 = 7'b1111111; d0 = 7'b0001111; end // 7 4'b1000: begin d1 = 7'b1111111; d0 = 7'b0000000; end // 8 4'b1001: begin d1 = 7'b1111111; d0 = 7'b0000100; end // 9 4'b1010: begin d1 = 7'b1001111; d0 = 7'b0000001; end // 10 4'b1011: begin d1 = 7'b1001111; d0 = 7'b1001111; end // 11 4'b1100: begin d1 = 7'b1001111; d0 = 7'b0010010; end // 12 4'b1101: begin d1 = 7'b1001111; d0 = 7'b0000110; end // 13 4'b1110: begin d1 = 7'b1001111; d0 = 7'b1001100; end // 14 4'b1111: begin d1 = 7'b1001111; d0 = 7'b0100100; end // 15 endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem: Four-Bit Binary to Two-Digit BCD Decoder Active Low library ieee; use ieee.std_logic_1164.all; entity Problem3_90_Bin2BCDSegments is port ( binary: in std_logic_vector(3 downto 0); -- 4-bit binary input d1,d0: out std_logic_vector(6 downto 0)); -- Tens and units segment outputs end Problem3_90_Bin2BCDSegments; architecture equations of Problem3_90_Bin2BCDSegments is begin process ( binary) begin case (binary) is -abcdefg abcdefg when “0000” => d1 <= “1111111”; d0 <= “0000001”; -- 0 when “0001” => d1 <= “1111111”; d0 <= “1001111”; -- 1 when “0010” => d1 <= “1111111”; d0 <= “0010010”; -- 2 when “0011” => d1 <= “1111111”; d0 <= “0000110”; -- 3 when “0100” => d1 <= “1111111”; d0 <= “1001100”; -- 4 when “0101” => d1 <= “1111111”; d0 <= “0100100”; -- 5 when “0110” => d1 <= “1111111”; d0 <= “0100000”; -- 6 when “0111” => d1 <= “1111111”; d0 <= “0001111”; -- 7 when “1000” => d1 <= “1111111”; d0 <= “0000000”; -- 8 when “1001” => d1 <= “1111111”; d0 <= “0000100”; -- 9 when “1010” => d1 <= “1001111”; d0 <= “0000001”; -- 10 when “1011” => d1 <= “1001111”; d0 <= “1001111”; -- 11 when “1100” => d1 <= “1001111”; d0 <= “0010010”; -- 12 when “1101” => d1 <= “1001111”; d0 <= “0000110”; -- 13 when “1110” => d1 <= “1001111”; d0 <= “1001100”; -- 14 when “1111” => d1 <= “1001111”; d0 <= “0100100”; -- 15 when others => d1 <= “1111111”; d0 <= “1111111”; -- other blank end case; end process; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.91 Design a decoder that converts 4-bit 2’s complement numbers to codes for displaying the sign and decimal value of the binary number on two seven-segment displays. Describe your design as Verilog and/or VHDL modules.

Value

+0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1

a3a2a1a0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Sb3b2b1b0 00000 00001 00010 00011 00100 00101 00110 00111 11000 10111 10110 10101 10100 10011 10010 10001

//Verilog Problem 3.91: 4-Bit 2s complement to 7-segment BCD Decoder Active Low module Problem3_91_Signed2SignDigitSegments ( input [3:0] binary, // 4-bit twos complement input output reg [6:0] sign, digit); // Sign and digit 7-segment outputs always @ (binary [3:0]) case (binary [3:0]) // abcdefg abcdefg 4'b0000: begin sign = 7'b1111111; digit = 7'b0000001; end // 0 4'b0001: begin sign = 7'b1111111; digit = 7'b1001111; end // 1 4'b0010: begin sign = 7'b1111111; digit = 7'b0010010; end // 2 4'b0011: begin sign = 7'b1111111; digit = 7'b0000110; end // 3 4'b0100: begin sign = 7'b1111111; digit = 7'b1001100; end // 4 4'b0101: begin sign = 7'b1111111; digit = 7'b0100100; end // 5 4'b0110: begin sign = 7'b1111111; digit = 7'b0100000; end // 6 4'b0111: begin sign = 7'b1111111; digit = 7'b0001111; end // 7 4'b1000: begin sign = 7'b1111110; digit = 7'b0000000; end // -8 4'b1001: begin sign = 7'b1111110; digit = 7'b0001111; end // -7 4'b1010: begin sign = 7'b1111110; digit = 7'b0100001; end // -6 4'b1011: begin sign = 7'b1001110; digit = 7'b0100100; end // -5 4'b1100: begin sign = 7'b1001110; digit = 7'b1001100; end // -4 4'b1101: begin sign = 7'b1001110; digit = 7'b0000110; end // -3 4'b1110: begin sign = 7'b1001110; digit = 7'b0010010; end // -2 4'b1111: begin sign = 7'b1001110; digit = 7'b1001111; end // -1 endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem: Four-Bit Binary to Two-Digit BCD Decoder Active Low library ieee; use ieee.std_logic_1164.all; entity Problem3_91_Signed2SignDigitSegments is port ( binary: in std_logic_vector(3 downto 0); -- 4-bit 2s complement input sign,digit: out std_logic_vector(6 downto 0)); -- Sign and digit segment outputs end Problem3_91_Signed2SignDigitSegments; architecture behavior of Problem3_91_Signed2SignDigitSegments is begin process ( binary) begin case (binary) is -- abcdefg abcdefg when “0000” => sign <= “1111111”; digit <= “0000001”; -- 0 when “0001” => sign <= “1111111”; digit <= “1001111”; -- 1 when “0010” => sign <= “1111111”; digit <= “0010010”; -- 2 when “0011” => sign <= “1111111”; digit <= “0000110”; -- 3 when “0100” => sign <= “1111111”; digit <= “1001100”; -- 4 when “0101” => sign <= “1111111”; digit <= “0100100”; -- 5 when “0110” => sign <= “1111111”; digit <= “0100000”; -- 6 when “0111” => sign <= “1111111”; digit <= “0001111”; -- 7 when “1000” => sign <= “1111110”; digit <= “0000000”; -- -8 when “1001” => sign <= “1111110”; digit <= “0001111”; -- -7 when “1010” => sign <= “1111110”; digit <= “0100000”; -- -6 when “1011” => sign <= “1111110”; digit <= “0100100”; -- -5 when “1100” => sign <= “1111110”; digit <= “1001100”; -- -4 when “1101” => sign <= “1111110”; digit <= “0000110”; -- -3 when “1110” => sign <= “1111110”; digit <= “0010010”; -- -2 when “1111” => sign <= “1111110”; digit <= “1001111”; -- -1 when others => sign <= “1111111”; digit <= “1111111”; -- other blank end case; end process; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.92 Two-to-1 multiplexers are included in some cell libraries as primitive components. Use two-to-1 multiplexers plus AND, OR, and NOT gates, if needed, to realize the following logic functions. Use as few components as possible. (a) 𝐴𝐴𝐴𝐴 = 0 ⋅ 𝐵𝐵� + 𝐴𝐴𝐴𝐴

(d) 𝐴𝐴 ⊕ 𝐵𝐵 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴̅𝐵𝐵

(b) 𝐴𝐴𝐵𝐵� = 𝐴𝐴𝐵𝐵� + 0 ⋅ 𝐵𝐵

(c) 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴̅𝐵𝐵 + 1 ⋅ 𝐴𝐴 = 𝐴𝐴 + 𝐵𝐵

(e) 𝐴𝐴𝐶𝐶̅ + 𝐵𝐵𝐵𝐵

� 𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐶𝐶̅ + 𝐴𝐴̅𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵� 𝐶𝐶 (f) ∑𝑚𝑚(0,2,3,5) = 𝐴𝐴̅𝐵𝐵

= (𝐴𝐴̅𝐵𝐵� )𝐶𝐶̅ + (𝐴𝐴̅𝐵𝐵)(𝐶𝐶̅ + 𝐶𝐶̅ ) + (𝐴𝐴𝐵𝐵� )𝐶𝐶 + (𝐴𝐴𝐴𝐴) ⋅ 0

(g) 𝑎𝑎𝑏𝑏�𝑐𝑐̅ + 𝑎𝑎�𝑐𝑐 + 𝑏𝑏𝑏𝑏 = 𝑎𝑎𝑏𝑏� 𝑐𝑐̅ + 𝑎𝑎�𝑏𝑏�𝑐𝑐 + 𝑎𝑎�𝑏𝑏𝑏𝑏 + 𝑎𝑎�𝑏𝑏𝑏𝑏 + 𝑎𝑎𝑎𝑎𝑎𝑎 = �𝑎𝑎�𝑏𝑏��𝑐𝑐 + (𝑎𝑎�𝑏𝑏)𝑐𝑐 + �𝑎𝑎𝑏𝑏��𝑐𝑐̅ + (𝑎𝑎𝑎𝑎)𝑐𝑐

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Digital Logic Circuit Analysis and Design, 2nd Edition

� + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶𝐶𝐶 + 𝐴𝐴̅𝐵𝐵 𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴̅𝐵𝐵 𝐶𝐶̅ 𝐷𝐷 (h) ∑𝑚𝑚(0,1,2,3,4,5,9,13,14,15) = 𝐴𝐴̅𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 � + 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 +𝐴𝐴𝐵𝐵� 𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ 𝐷𝐷 + 𝐴𝐴𝐴𝐴𝐴𝐴𝐷𝐷 � + 𝐵𝐵� 𝐷𝐷 + 𝐵𝐵𝐷𝐷 � + 𝐵𝐵𝐵𝐵) + (𝐴𝐴̅𝐶𝐶 )(𝐵𝐵� 𝐷𝐷 � + 𝐵𝐵� 𝐷𝐷) = (𝐴𝐴̅𝐶𝐶̅ )(𝐵𝐵� 𝐷𝐷 � + 𝐵𝐵𝐵𝐵) +(𝐴𝐴𝐶𝐶̅ )(𝐵𝐵�𝐷𝐷 + 𝐵𝐵𝐵𝐵) + (𝐴𝐴𝐴𝐴)(𝐵𝐵𝐷𝐷

= (𝐴𝐴̅𝐶𝐶̅ )(1) + (𝐴𝐴̅𝐶𝐶)(𝐵𝐵�) + (𝐴𝐴𝐶𝐶̅ )(𝐷𝐷) + (𝐴𝐴𝐴𝐴)(𝐵𝐵)

3.93 Derive the truth table for the logic circuit described below.

Va 0 0 0 0 4.9 4.9 4.9 4.9

(a) Assuming positive logic a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

z 0 1 0 1 0 0 1 1

Vb 0 0 4.9 4.9 0 0 4.9 4.9

Vc 0 4.9 0 4.9 0 4.9 0 4.9

Vz 0 4.9 0 4.9 0 0 4.9 4.9

(b) Assuming negative logic a 1 1 1 1 0 0 0 0

b 1 1 0 0 1 1 0 0

c 1 0 1 0 1 0 1 0

z 1 0 1 0 1 1 0 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.94 Design Verilog and/or VHDL structural and datflow models for the circuit given in Problem 3.9.

//Verilog Problem 3.94 structural model module Problem3_94_Structure (f,A,B,C); input A,B,C; output f; wire D,E,G,H; xor xor1 (D, A, B); nand nand1 (E, A, C); nor nor1 (G, B, C); and and1 (H, D, E); or or1 (f, H, G); endmodule //Verilog Problem 3.94 dataflow model module Problem3_94_Dataflow (f,A,B,C); input A,B,C; output f; wire D,E,G,H; assign f = ((A ^ B) & (~(A & C))) | (~(B | C)); endmodule --VHDL Problem 3.94 dataflow model entity Problem3_94_Dataflow is port (A,B,C: in bit; -- inputs f: out bit); -- output end Problem3_94_Dataflow; architecture structure of Problem3_94_Dataflow is begin f <= ((A xor B) and (A nand C)) or (B nor C); end; --VHDL Problem 3.94 structural model entity Problem3_94_Structure is port (A,B,C: in bit; -- inputs f: out bit); -- output end Problem3_94_Structure;

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Digital Logic Circuit Analysis and Design, 2nd Edition

architecture structure of Problem3_94_Structure is component nand2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component nor2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component and2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component or2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; component xor2 -- gate model in my library port (b: out bit; a1,a2: in bit); end component; signal D,E,G,H: bit; -- internal wires begin XR1: xor2 port map (b=>D, a1=>A, a2=>B); ND1: nand2 port map (b=>E, a1=>A, a2=>C); NR1: nor2 port map (b=>G, a1=>B, a2=>C); AN1: and2 port map (b=>H, a1=>D, a2=>E); OR1: or2 port map (b=>f, a1=>G, a2=>H); end;

3.95 Design a Verilog and/or VHDL model for the XOR2x4 module used in the ALU design in section 3.4.4. //Verilog Problem 3.95: XOR2x4 module Problem3_95_XOR2x4 (Y,A,B); input [3:0] A,B; output [3:0] Y; assign Y = {(A[3] ^ B[3]), (A[2] ^ B[2]), (A[1] ^ B[1]), (A[0] ^ B[0])}; endmodule --VHDL Problem 3.95: XOR2x4 entity Problem3_95_XOR2x4 is port (A,B: in bit_vector(3 downto 0); -- inputs Y: out bit_vector(3 downto 0)); -- output end Problem3_95_XOR2x4; architecture dataflow of Problem3_95_XOR2x4 is begin Y <= (A(3) xor B(3)) & (A(2) xor B(2)) & (A(1) xor B(1)) & (A(0) xor B(0)); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.96 Compute the propagation delay for the circuits in Figure 3.16.

Assume each XOR gate has propagation delay tg.

The even parity bit generation circuit has three XOR gates between any input and output P, and therefore a propagation delay of 3tg.

The even parity bit check circuit has four XOR gates between the data inputs input and the Error output, and therefore a propagation delay of 4tg, whereas there is one gate delay, tg, between parity bit P and the Error output

3.97 Write a Verilog and/or VHDL model for the multiplexer described in Figure 3.44. //Verilog Problem 3.97: Quad 2-to-1 multiplexer module Problem3_97_Quad2to1Mux (A,B,Y,GN,S); input [3:0] A,B; //4-bit data inputs output reg [3:0] Y; //4-bit data output input GN,S; //enable and select inputs always @(*) if (GN == 1’b1) Y = 4’b0000; //mux disabled else if (S == 1’b0) Y = A; //mux enabled – select A inputs else Y = B; //mux enabled – select B inputs endmodule --VHDL Problem 3. 97: Quad 2-to-1 multiplexer entity Problem3_97_Quad2to1Mux is port ( A,B: in bit_vector(3 downto 0); -- 4-bit data inputs GN,S: in bit; -- enable and select inputs Y: out bit_vector(3 downto 0)); -- 4-bit output end Problem3_97_Quad2to1Mux; architecture behavior of Problem3_97_Quad2to1Mux is begin Y <= “0000” when GN = ‘1’ else -- mux disabled A when S = ‘0’ else -- mux enabled – select A inputs B when S = ‘1’; -- mux enabled – select B inputs end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.98 Given the seven-bit ASCII code defined in Table 1.10 in Chapter 1, design the following circuits assuming that you have only XOR2 gates available as logic elements. Draw schematics of each design. (a) A parity-bit generator for an odd-parity encoding. (b) An error detector for detecting single-bit errors assuming odd parity.

3.99 Repeat problem 3.95 for an even-parity encoding.

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.100 Given Hamming Code 1 defined in Table 1.14 of Chapter 1, write a Verilog and/or VHDL behavioral model of an encoder for the code. //Verilog Problem 3.100: Hamming Code 1 encoder module Problem3_100_Hamming1Encoder (i3, i2, i1, i0, c2, c1, c0); input i3, i2, i1, i0; // 4 information bits in output c2, c1, c0; // 3 check bits out assign c0 = (i3 ^ i1) ^ i0; // c0: i3, i1, i0 assign c1 = (i3 ^ i2) ^ i0; // c1: i3, i2, i0 assign c2 = (i3 ^ i2) ^ i1; // c2: i3, i2, i1 endmodule --VHDL Problem 3.100: Hamming Code 1 encoder entity Problem3_100_Hamming1Encoder is port ( i3, i2, i1, i0: in bit; -- 4 information bits in c2, c1, c0: out bit); -- 3 check bits out end Problem3_100_Hamming1Encoder; architecture behavior of Problem3_100_Hamming1Encoder is begin c0 <= (i3 xor i1) xor i0; -- c0: i3, i1, i0 c1 <= (i3 xor i2) xor i0; -- c0: i3, i2, i0 c2 <= (i3 xor i2) xor i1; -- c0: i3, i2, i1 end;

3.101 Write a Verilog and/or VHDL model of a decoder for Hamming Code 1. The decoder should detect and correct single errors. //Verilog Problem 3.101: Hamming Code 1 decoder module Problem3_101_Hamming1Decoder (i3, i2, i1, i0, c2, c1, c0, y3, y2, y1, y0); input i3, i2, i1, i0, c2, c1, c0; // 4 information and 3 check bits in output reg y3,y2, y1, y0; // corrected data bits out wire s2, s1, s0; // syndrome bits assign s0 = (i3 ^ i1) ^ (i0 ^ c0); // c0: i3, i1, i0 assign s1 = (i3 ^ i2) ^ (i0 ^ c1); // c1: i3, i2, i0 assign s2 = (i3 ^ i2) ^ (i1 ^ c2); // c2: i3, i2, i1 always @(*) case ({s2,s1,s0}) 3’b000: {y3,y2,y1,y0} = {i3, i2, i1, i0}; //no error 3’b001: {y3,y2,y1,y0} = {i3, i2, i1, i0}; //c0 error 3’b010: {y3,y2,y1,y0} = {i3, i2, i1, i0}; //c1 error 3’b011: {y3,y2,y1,y0} = {i3, i2, i1, ~i0}; //i0 error 3’b100: {y3,y2,y1,y0} = {i3, i2, i1, i0}; //c2 error 3’b101: {y3,y2,y1,y0} = {i3, i2, ~i1, i0}; //i1 error 3’b110: {y3,y2,y1,y0} = {i3, ~i2, i1, i0}; //i2 error 3’b111: {y3,y2,y1,y0} = {~i3, i2, i1, i0}; //i3 error endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem 3.101: Hamming Code 1 decoder entity Problem3_101_Hamming1Decoder is port ( i3, i2, i1, i0, c2, c1, c0: in bit; -- 4 information and 3 check bits in y3, y2, y1, y0: out bit); -- corrected information bits out end Problem3_101_Hamming1Decoder; architecture behavior of Problem3_101_Hamming1Decoder is signal s: bit_vector(2 downto 0); -- syndrome begin s(0) <= (i3 xor i1) xor (i0 xor c0); -- c0: i3, i1, i0 s(1) <= (i3 xor i2) xor (i0 xor c1); -- c0: i3, i2, i0 s(2) <= (i3 xor i2) xor (i1 xor c2); -- c0: i3, i2, i1 y3 <= not i3 when s = “111” else i3; -- syndrome for i3 error y2 <= not i2 when s = “110” else i2; -- syndrome for i2 error y1 <= not i1 when s = “101” else i1; -- syndrome for i1 error y0 <= not i0 when s = “011” else i0; -- syndrome for i0 error end;

3.102 Repeat problem 3.100 for Hamming Code 2. //Verilog Problem 3.102: Hamming Code 2 encoder module Problem3_102_Hamming2Encoder (i3, i2, i1, i0, c3, c2, c1, c0); input i3, i2, i1, i0; // 4 information bits in output c3, c2, c1, c0; // 4 check bits out assign c0 = (i3 ^ i1) ^ i0; // c0: i3, i1, i0 assign c1 = (i3 ^ i2) ^ i0; // c1: i3, i2, i0 assign c2 = (i3 ^ i2) ^ i1; // c2: i3, i2, i1 assign c3 = (i2 ^ i1) ^ i0; // c3: i2, i1, i0 endmodule --VHDL Problem 3.102: Hamming Code 2 encoder entity Problem3_102_Hamming2Encoder is port ( i3, i2, i1, i0: in bit; -- 4 information bits in c3, c2, c1, c0: out bit); -- 4 check bits out end Problem3_102_Hamming2Encoder; architecture behavior of Problem3_102_Hamming2Encoder is begin c0 <= (i3 xor i1) xor i0; -- c0: i3, i1, i0 c1 <= (i3 xor i2) xor i0; -- c0: i3, i2, i0 c2 <= (i3 xor i2) xor i1; -- c0: i3, i2, i1 c3 <= (i2 xor i1) xor i0; -- c0: i2, i1, i0 end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

3.103 Repeat problem 3.101 for Hamming Code 2. Additionally, the decoder should detect double errors. //Verilog Problem 3.103: Hamming Code 2 decoder module Problem3_103_Hamming2Decoder (i3, i2, i1, i0, c3, c2, c1, c0, y3, y2, y1, y0, de); input i3, i2, i1, i0, c3, c2, c1, c0; // 4 information and 4 check bits in output reg y3,y2, y1, y0; // corrected data bits out output reg de; // double error detected wire s3, s2, s1, s0; // syndrome bits assign s0 = (i3 ^ i1) ^ (i0 ^ c0); // c0: i3, i1, i0 assign s1 = (i3 ^ i2) ^ (i0 ^ c1); // c1: i3, i2, i0 assign s2 = (i3 ^ i2) ^ (i1 ^ c2); // c2: i3, i2, i1 assign s3 = (i2 ^ i1) ^ (i0 ^ c3); // c3: i2, i1, i0 always @(*) case ({s3, s2,s1,s0}) 4’b0000: begin {y3,y2,y1,y0} = {i3, i2, i1, i0}; de = 1’b0; end //no error 4’b0001: begin {y3,y2,y1,y0} = {i3, i2, i1, i0}; de = 1’b0; end //c0 error 4’b0010: begin {y3,y2,y1,y0} = {i3, i2, i1, i0}; de = 1’b0; end //c1 error 4’b0100: begin {y3,y2,y1,y0} = {i3, i2, i1, i0}; de = 1’b0; end //c2 error 4’b1000: begin {y3,y2,y1,y0} = {i3, i2, i1, i0}; de = 1’b0; end //c3 error 4’b1011: begin {y3,y2,y1,y0} = {i3, i2, i1, ~i0}; de = 1’b0; end //i0 error 4’b1101: begin {y3,y2,y1,y0} = {i3, i2, ~i1, i0}; de = 1’b0; end //i1 error 4’b1110: begin {y3,y2,y1,y0} = {i3, ~i2, i1, i0}; de = 1’b0; end //i2 error 4’b0111: begin {y3,y2,y1,y0} = {~i3, i2, i1, i0}; de = 1’b0; end //i3 error default: begin {y3,y2,y1,y0} = {i3, i2, i1, i0}; de = 1’b1; end //double error endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

--VHDL Problem 3.103: Hamming Code 2 decoder entity Problem3_103_Hamming2Decoder is port ( i3, i2, i1, i0, c3, c2, c1, c0: in bit; -- 4 information and 4 check bits in y3, y2, y1, y0: out bit; -- corrected information bits de: out bit); -- double error indicator end Problem3_103_Hamming2Decoder; architecture behavior of Problem3_103_Hamming2Decoder is signal s: bit_vector(3 downto 0); -- syndrome signal t: bit_vector(3 downto 0); -- temp output begin s(0) <= (i3 xor i1) xor (i0 xor c0); -- c0: i3, i1, i0 s(1) <= (i3 xor i2) xor (i0 xor c1); -- c1: i3, i2, i0 s(2) <= (i3 xor i2) xor (i1 xor c2); -- c2: i3, i2, i1 s(3) <= (i2 xor i1) xor (i0 xor c3); -- c3: i3, i2, i1 process (s, i3, i2, i1, i0, c3, c2, c1, c0) begin case (s) is when “0000” => t <= (i3, i2, i1, i0); de <= ‘0’; -- no errors when “0111” => t <= (not i3, i2, i1, i0); de <= ‘0’; -- i3 error when “1110” => t <= (i3, not i2, i1, i0); de <= ‘0’; -- i2 error when “1101” => t <= (i3, i2, not i1, i0); de <= ‘0’; -- i1 error when “1011” => t <= (i3, i2, i1, not i0); de <= ‘0’; -- i0 error when “0001” => t <= (i3, i2, i1, i0); de <= ‘0’; -- c0 error when “0010” => t <= (i3, i2, i1, i0); de <= ‘0’; -- c1 error when “0100” => t <= (i3, i2, i1, i0); de <= ‘0’; -- c2 error when “1000” => t <= (i3, i2, i1, i0); de <= ‘0’; -- c3 error when others => t <= (i3, i2, i1, i0); de <= ‘1’; -- double error end case end process; y3 <= t(3); y2 <= t(2); y1 <= t(1); y0 <= t(0); -- drive outputs end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

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Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 4 – Introduction to Sequential Circuits 4.1 Construct a state diagram from the following state table. What is the logic equation for the output variable z ?

𝑧𝑧 = 𝑥𝑥

4.2 Given the following state table, if the circuit starts in state A, find the output and state sequences for the input sequence 𝑥𝑥 = 01010101.

Time = 0 x= 0 y= A z= 0

1 1 D 1

2 0 C 0

3 1 B 0

4 0 B 0

5 1 C 0

6 0 C 0

7 1 B 0

8 B

4.3 For the following sequential circuit, draw a state diagram of the circuit and determine the output sequence for the input sequence x = 0010110101 , if the starting state is A.

Time = 0 x= 0 y= A z= 0

1 0 B 1

2 1 C 1

3 0 A 0

4 1 B 0

5 1 B 0

6 0 B 1

7 1 C 1

8 0 A 0

9 10 1 B B 0

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.4 For the following sequential circuit, draw a state diagram of the circuit and determine the output sequence for the input sequence 𝑥𝑥 = 100101000 if the starting state is A.

Time = 0 x= 1 y= A z= 0

1 0 B 0

2 0 A 0

3 1 C 1

4 0 C 1

5 1 D 0

6 0 C 1

7 0 D 0

8 0 B 0

9 A 0

4.5 The state diagrams in Figs. P4.5a and P4.5b are those of a Mealy model circuit M1, with output Z1, and a similar Moore model circuit M2, with output Z2. a. Derive state tables for each of these two models. b. Complete the timing diagram of Fig. P4.5c by determining the next states and outputs of the two circuits, assuming that both circuits receive the same input signal x and that state changes occur on the rising edge of the clock.

Figure P4.5 (a) Mealy model M1 (b) Moore model M2 (c) Timing diagram c. Discuss the differences in the next states and outputs of the two circuits.

Both circuits produce the same sequence of states, since their next states are identical for each current state and each value of input x. The output of the Mealy model is 1 only while in state C with x = 1, whereas the output of the Moore model is 1 while in state C, independent of the value of x.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.6 Derive the state diagram and characteristic equation of the latch circuit in Fig. P4.6.

Figure P4.6

4.7 Find the excitation table of the latch circuit in Fig. P4.7 and describe its behavior in words.

Figure P4.7

A 0 0 0 0 1 1 1 1

B Q 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

𝑄𝑄* 1 1 1 1 0 1 1 1

𝑄𝑄* 0 0 0 0 1 0 0 0

Function Set Set Hold Set

This is a "set latch". Once it sets to state 1 it cannot be reset to state 0. A is an active-low set input, and B is an active-high set input. When A = 1 and B = 0, the state holds. When either A = 0 or B = 1, the state sets to 1.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.8 Determine the state diagram and characteristic equation of the “latch” circuit in Fig. P4.8 and describe its behavior in words.

This is a “reset latch”. It can power up initially in either state 0 or 1. However, if it begins in state 1, it will remain in state 1 only if AB = 01, and will otherwise transition to state 0 for any other combination of AB. Once the circuit is in state 0, it will remain in that state for any combination of AB values.

4.9 Is the circuit of Fig. P4.9a a valid latch design? Explain. If it is a latch, complete the excitation table of Fig. P4.9b. Can it be used as a gated SR latch? If so, how?

It is a valid latch. It is a "gated SR latch": - C is the active-high gate input (latch enabled when C = 1).

- A is the active-high set input (latch sets when enabled and A = 1, B = 0).

- B is the active-high reset input (latch resets when enabled and B = 1, A = 0).

Note that A = B = 1 is not allowed when the latch is enabled.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.10 Construct state diagrams for the following flip-flop types.

4.11 Derive the characteristic state equations shown in Table 4.2 for the following components.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.12 Given the JK flip-flop of Fig. P4.12a, complete the timing diagram of Fig. P4.12b by determining the waveform of the output Q .

4.13 Given the SR flip-flop of Fig. P4.13a, complete the timing diagram of Fig. P4.13b by determining the waveform of the output Q . The condition S = R = 1 is produced twice by the inputs. Will this lead to unstable operation? Explain.

The condition S = R = 1 will not cause unstable operation since this condition does not exist at the time of any positive edge of the clock signal. Only the S and R values at these clock edges affect the state.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.14 The waveforms of Fig. P4.14 are applied to the inputs of a positive-edge-triggered JK flipflop with asynchronous present and clear inputs. Complete the timing diagram by drawing the waveforms of flip-flop outputs Q and Q .

4.15 The circuit of Fig. P4.15a contains a D latch, a positive-edge-triggered D flip-flop, and a negative-edge-triggered D flip-flop. Complete the timing diagram of Fig. P4.15b by drawing the waveforms of signals y1 , y2 , and y3 .

Figure P4.15: (a) Logic diagram. (b) Timing diagram.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.16 The circuit of Fig. P4.16a is initially in state 𝑄𝑄1 = 𝑄𝑄2 = 0. Sketch a timing diagram showing the states of signals Q1 and Q2 for a sequence of seven clock pulses.

Figure P4.16.

4.17 The circuit of Fig. P4.17a contains a JK flip-flop and a D flip-flop. Complete the timing diagram of Fig. P4.17b by drawing the waveforms of signals Q1 and Q2 .

Figure P4.17 (a) Logic diagram. (b) Timing diagram.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.18 Complete the timing diagram given below for the circuit in Fig. P4.18 by sketching the waveforms for X and Z. Assume initial values X = Z = 0.

Figure P4.18 4.19 Complete the following table of flip-flop excitation values required to produce the indicated flip-flop state changes, where y indicates the present state and Y the desired next state of the flip-flop.

Present State Next State y Y 0 0 0 1 1 0 1 1

JK flip-flop J K 0 d 1 d d 1 d 0

D flip-flop D 0 1 0 1

SR flip-flop S R 0 d 1 0 0 1 d 0

T flip-flop T 0 1 1 0

4.20 Discuss why the condition S = R = 1 leads to an unstable condition for an SR latch.

1. S = R = 1 forces both 𝑄𝑄 and 𝑄𝑄 outputs to 0.

2. When S and R return to 0, if gate propagation delays are equal then the two outputs becomes 1 simultaneously, which in turn changes them back to 0, then back to 1, and so on, i.e. the circuit oscillates.

3. If gate propagation delays are not" equal, then one output will change faster than the other and eventually further changes will be inhibited, with the circuit settling into some state, although one cannot accurately predict which state.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.21 Describe how the unstable condition S = R = 1 is avoided in the storage latch of the following: (a) D latch At the inputs to the internal SR latch, 𝐷𝐷 is applied to the S input and 𝐷𝐷 is applied to the R input, so one or the other of S and R will be 0 at all times. ( b) J K flip-flop At the inputs to the internal SR latch, 𝐽𝐽𝑄𝑄 is applied to the S input and 𝐾𝐾𝑄𝑄 is applied to the R input. The use of Q forces one or the other of S and R to be 0 at all times. (c) T flip-flop At the inputs to the internal SR latch, T = 0 results in S = R = 0. T = 1 results in 𝑆𝑆 = 𝑄𝑄 and 𝑅𝑅 = 𝑄𝑄. So S and R are either complementary values or both 0.

4.22 The circuit of Fig. P4.22 is intended to operate as a JK latch. Discuss whether or not this circuit is stable for the condition J = K = C = 1 . If the circuit is unstable, discuss what could be done to the clock signal, C , to make the circuit operate as expected.

Figure P4.22 The condition 𝐽𝐽 = 𝐾𝐾 = 𝐶𝐶 = 1 results in the S input of the internal SR latch being � and the R input being equal to 𝑄𝑄. When Q = 0, we have S = 1 and R equal to 𝑄𝑄 = 0, setting the latch. When Q = 1, we have S = 0 and R = 1, reset ting the latch. This is the desired toggle operation.

However, as long as 𝐽𝐽 = 𝐾𝐾 = 𝐶𝐶 = 1, the latch will toggle again and will continue to toggle. This is an unstable condition. This can be prevented by allowing C = 1 only for a very short time, i.e. by making C a short pulse. The time t hat C = 1. must be long enough to trigger a state change but short enough so that C = 0 before a second toggle can be initiated.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.23 Design a JK flip-flop with asynchronous present and clear inputs using only NOR gates.

4.24 Describe the operational difference between a clocked D-type latch and a D-type flip-flop as observed from the outputs of the devices.

•

In a latch, the state Q is set to input D whenever C = 1. Therefore, the Q output "follows" the D input while the latch is enabled, and holds while C = 0.

•

In a master-slave flip-flop, the output changes to the value present on the D input only at the instant of the clock transition that enables the slave latch, i.e. the flipflop is only sensitive to the D input at the exact instant of the clock transition.

Other changes on input D are effectively ignored.

4.25 Describe how a two-latch flip-flop circuit appears to operate as an edge-triggered device when observed from its external outputs.

Since the clocks to the control and output latches are complemented, there is always one latch in "gated" mode and the other in "hold" mode. When the control latch is enabled, the output latch is disabled, holding the overall output of the flipflop constant while the output of the control latch is determined by the flip-flop excitation inputs. When the output latch is enabled, the control latch is disabled, preventing the output of the control latch from changing. Since the control latch output is the input to the output latch, the output latch has a constant excitation input, and thus a constant output. Therefore, the overall flip-flop output will change only at the instant the output latch is enabled, and thus the flip-flop appears to be edge triggered when observed from its external output.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.26 Using the hazard-free D latch circuit structure shown in Fig. 4.29c, design a rising-edge triggered D flip-flop using only NAND gates and inverters.

Control latch is enabled and Output latch disabled when Clock = 0.

Control latch is disabled and Output latch enabled when Clock = 1.

Output Q changes when Output latch becomes enabled, when Clock changes from 0 to 1.

4.27 Examine the D flip-flop circuit of Fig. 4.31b and describe how it operates as an edgetriggered device.

• •

When CK = 0 the output latch is disabled, keeping it in its hold state. The Control latch is enabled, allowing it to capture the value of D as its state QC. When CK goes to 1, the Control latch enters its hold state. At the same instant, the the Output latch becomes enabled, causing its state to be determined by 𝑆𝑆 = 𝑄𝑄𝐶𝐶 and

𝑅𝑅 = 𝑄𝑄𝐶𝐶 , setting output 𝑄𝑄 to 1 if QC = 1 and to 0 if QC = 0. Since the Control latch is in its hold state, QC remains constant, and therefore Q will not change again, during the entire time the Output latch is enabled. Thus, the final state of the output latch is a function of the value on input D only at the instant CK changes from 0 to 1.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.28 Examine the SR latch circuit of Fig. 4.14, and then design a falling-edge-tiggered D flip-flop with an active-low asynchronous CLR input. Describe why the CLR input is referred to as an asynchronous input, while the D input is called a synchronous input.

𝐶𝐶𝐿𝐿𝐿𝐿 bypasses the clock signal to force the upper NOR gate outputs to 0 and the lower AND gate outputs to 0, which subsequently change the lower NOR gate outputs (QC and Q) to 0, thus resetting the states of the two latches. Since these changes are not synchronized to the clock, we refer to 𝐶𝐶𝐶𝐶𝐶𝐶 as an asynchronous input.

4.29 Connect a D flip-flop in such a manner that it will perform like a clocked T flip-flop.

4.30 Construct a D flip-flop using only a JK flip-flop and an inverter, but no additional gates.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.31 Using three rising-edge-triggered JK flip-flops and a minumum number of additional gates, construct a circuit that will operate as a binary counter with an enable signal E. When E = 1, the counter should increment from 0 to 7 on each clock pulse, with (flip-flop outputs Q2Q1Q0 = 000001-010-011-100-101-110-111) and then roll over to 000 and repeat the sequence. When E=0, the counter should stop and hold its current count.

When E = 1, Q0 toggles (J=K=1), Q1 toggles if Q0 = 1, and Q2 toggles if Q1 and Q0 are both 1.

When E = 0, all three flip-flops have J=K=0 and thus hold their states.

4.32 The circuit of Fig. P4.32 is similar to that used in some commercial programmable logic sequencer chips. It is designed to operate as either a JK flip-flop or as a D flip-flop according to the settings of switches SW1 and SW2 . Determine the settings (open or closed) of the two switches required for JK and D flip-flop operation, and describe how this operation is achieved.

Figure P4.32 JK Operation: Close switch SW1 and open switch SW2 to allow the A input to control the J excitation input and the B input to control the K excitation input of the flip-flop.

D Operation: Open switch SW1 and close switch SW2. This sets the J excitation input to A and the K excitation input to 𝐴𝐴. Thus, the A input is equivalent to the D excitation input of a D flip-flop.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.33 Using falling-edge-triggered D flip-flops with active-low asynchronous clear inputs, design and sketch a circuit for an 8-bit register. The register has data inputs D7 – D0, data outputs Q7Q0, clock CLK, and clear input CLR . On a clock transition, the data inputs should be captured in the register. When CLR is active, all outputs should reset to 0. Use logic symbols for the D flipflops and not gate-level schematics.

4.34 Design a 3-bit parallel-load shift register (logic symbol shown in Fig. P4.34) using D flip flops and multiplexers. When EN = 1 and L/S* = 1, the shift register is to be loaded with the parallel inputs. When EN = 1 and L/S* = 0, the register is to shift right one bit, with S_IN (serial input) loaded into the left-most bit. When EN = 0, the contents of the shift register should not change.

Synchronize all operations to the rising edge of the clock.

Figure P4.34

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.35 Use a 2-to-4 decoder, NAND gates, and edge-triggered D flip-flops to design a 4-bit shift register module that has the following function table, and draw a logic diagram for your module.

S1 S0 Mode 0 0 Shift right (all 4 bits) 0 1 Shift left (all 4 bits) 1 0 Synchronous common clear 1 1 Synchronous parallel load

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.36 Use a 3-to-8 decoder, NAND gates, and edge-triggered D flip-flops to design a 4-bit shift register module that has the following function table. Draw a logic diagram for your module.

S2 S1 S0 Mode 0 0 0 Shift right (all 4 bits) 0 0 1 Shift left (all 4 bits) 0 1 0 Synchronous common clear 0 1 1 Synchronous parallel load 1 0 0 Synchronous preset MSB to 1 and clear other bits 1 0 1 Synchronous data hold 1 1 0 Ring counter ( Q output of LSB fed back as serial input to the MSB) 1 1 1 Twisted-ring counter ( Q output of LSB fed back as serial input to the MSB)

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.37 Use D flip-flops to design a synchronous modulo-15 counter.

At each clock transition: Reset to 0000 if Q3Q2Q1 = 1 (Count = 14), Otherwise: Q0 toggles; Q1 toggles if Q0 = 1; Q2 toggles if Q1Q0 = 1; Q3 toggles if Q2Q1Q0 = 1

4.38 Use D flip-flops to design an asynchronous modulo-15 counter.

Asynchronous reset to 0000 if Q3Q2Q1Q0 = 1 (Count = 1).

Otherwise, at each clock transition: Q0 toggles; Q1 toggles if Q0 = 1; Q2 toggles if Q1Q0 = 1; Q3 toggles if Q2Q1Q0 = 1

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.39 Use D flip-flops to design an eight-state ring counter. Provide an asynchronous initialize control signal.

4.40 Use appropriate modules to design a 14-state ring counter. Provide an asynchronous initialize control signal.

Load 1 into bit A and 0 into the other 13 bits when Initialize = 1.

Otherwise shift right, with bit Q14 fed back to Q1.

Note that Initialize is synchronous in this case.

Asynchronous initialize requires asynchronous set for bit Q1 and clear for the other bits.

4.41 Use appropriate modules to design an eight-state twisted-ring counter. Provide an asynchronous initialize control signal.

SR4 = 4-bit right-shift register with asynchronous clear.

Initialize clears all bits to 0000, 1st clock sets bits to 1000, 2nd clock sets bits to 1100, etc.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.42 Use appropriate modules to design a 14-state twisted-ring counter. Provide an asynchronous initialize control signal.

SR4 = 4-bit right-shift register with asynchronous clear.

Initialize clears bits to 0000000. 1st clock produces 1000000, etc.

4.43 Use counter and decoder modules to design an eight-state ring-counter equivalent similar to Fig. 4.70. Provide an asynchronous initialize control signal.

3-bit binary counter outputs 000 – 111 activate (low) decoder outputs 0 – 7 in sequence.

4.44 Use counter and decoder modules to design a 14-state ring-counter equivalent similar to Fig. 4.70. Provide an asynchronous initialize control signal.

Counter asynchronously rests when count = 14. The count activates (low) outputs 0-13 of the decoder, to produce the 14 pulses.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.45 Design three equivalent timing signal generators using the counters of Problems 4.39, 4.41, and 4.43. The outputs of the three circuits should generate a pulse on the first and fifth clock pulses after the initialize signal. The sequence should repeat every eight clock pulses. a. After the first clock pulse, the 8-bit ring counter outputs 01000000 (LSB to MSB), and after the 5th clock pulse the outputs will be 00000100. Therefore, OR outputs Q2 and Q6.

b. For the twisted-ring counter, the output is 1000 (LSB to MSB) after the first clock pulse and 0111 after the 5th clock pulse. The equation representing the sum of these two conditions is: 𝑂𝑂𝑂𝑂𝑂𝑂 = 𝑄𝑄1 𝑄𝑄2 𝑄𝑄3 𝑄𝑄4 + 𝑄𝑄1 𝑄𝑄2 𝑄𝑄3 𝑄𝑄4 = �𝑄𝑄1 + 𝑄𝑄2 + 𝑄𝑄3 + 𝑄𝑄4 � + 𝑄𝑄1 𝑄𝑄2 𝑄𝑄3 𝑄𝑄4

c. NOR active-low decoder outputs 1 and 2, corresponding to ring counter states x2 and x6, which are entered on clock pulses 1 and 5, respectively.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.46 Design three equivalent timing signal generators using the counters of Problems 4.40, 4.42, and 4.44. The outputs of the nine circuits (three for each problem) should match the example of Fig. 4.77, except that the timing waveforms will be repeated every 14 clock pulses instead of every 16 pulses.

a. The 14-state ring counter pulses one output per clock period. Output f1 is to pulse on the leading edge of the 2nd clock pulse, which pulses counter output Q3. Output f2 is to pulse on the leading edge of the 8th clock pulse, which pulses output Q9. Output f3 is to pulse on the leading edge of the 11th clock pulse, which pulses output Q12. Therefore f1 = Q3, f2 = Q9, f3 = Q12.

b. For the twisted-ring counter, outputs Q1Q2Q3Q4Q5Q6Q7 are 1100000 after the 2nd clock pulse, so 𝑓𝑓1 = 𝑄𝑄2 𝑄𝑄3 . The outputs are 0111111 after the 8th clock pulse, so 𝑓𝑓2 = 𝑄𝑄1 𝑄𝑄2 , and the outputs are 0000111 after the 11th clock pulse, so 𝑓𝑓3 = 𝑄𝑄4 𝑄𝑄5 .

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Digital Logic Circuit Analysis and Design, 2nd Edition

c. For the 14-bit ring counter comprising a Modulo-14 counter and a decoder, the desired

outputs at clock pulses 2, 8, and 11 are produced on active-low decoder outputs 3, 9, and

12, respectively, so 𝑓𝑓1 = 𝑄𝑄3 , 𝑓𝑓2 = 𝑄𝑄9 , and 𝑓𝑓3 = 𝑄𝑄12 .

4.47 Use appropriate modules to implement a digital fractional rate multiplier with an output to input ratio of 5/10. 𝑁𝑁

5 with an n-bit 10 𝑖𝑖 𝐵𝐵 binary counter with rate constant B such that 𝑁𝑁𝑂𝑂 = 𝑛𝑛 𝑁𝑁𝑖𝑖 .

2

We can produce output to input ratio 𝑁𝑁𝑜𝑜 =

For n=4, B = (B3B2B1B0) = (1000)2 = 8.

Given binary counter outputs (Q3Q2Q1Q0) and a desired rate constant B, output 𝑌𝑌 = ∑ 𝐵𝐵𝑖𝑖 𝑃𝑃𝑖𝑖 , where: 𝑃𝑃1 = 𝑄𝑄3 𝑄𝑄2 𝑄𝑄1 𝑄𝑄0 ; 𝑃𝑃2 = 𝑄𝑄2 𝑄𝑄1 𝑄𝑄0 ; 𝑃𝑃1 = 𝑄𝑄1 𝑄𝑄0 ; 𝑃𝑃4 = 𝑄𝑄0 Therefore, we have 𝑌𝑌 = ∑ 𝐵𝐵𝑖𝑖 𝑃𝑃𝑖𝑖 = 𝐵𝐵3 𝑃𝑃3 = 𝑄𝑄0 .

4.48 Use appropriate modules to implement a digital fractional rate multiplier with an output to input ratio of 11/80.

•

11 𝑁𝑁 . Instead of using a modulo-80 counter, we can 80 𝑖𝑖 11 88 8 11 𝑁𝑁 = � � � � 𝑁𝑁𝑖𝑖 . Thus we cascade two smaller rate counters by choosing 𝑁𝑁𝑂𝑂 = 𝑁𝑁𝑖𝑖 = 80 640 𝑖𝑖 10 64

Referring to Problem 4.47, we need 𝑁𝑁𝑂𝑂 =

cascade a decade counter with B = 8 = (1000)2 and a 6-bit binary counter (modulo-64 counter) with B = 11 = (001011)2.

• For a decade counter with outputs (Q3Q2Q1Q0), it can be shown that 𝑌𝑌 = 𝐵𝐵3 𝑄𝑄2 + 𝐵𝐵2 𝑄𝑄0 + 𝐵𝐵1 𝑄𝑄1 𝑄𝑄0 + 𝐵𝐵0 𝑄𝑄3 𝑄𝑄2 .

For B=(1000)2, output 𝑌𝑌 = 𝐵𝐵3 𝑄𝑄2 , which serves as the clock input to the modulo-64 counter.

• For a 6-bit binary counter with B = (001011)2, we have 𝑌𝑌 = ∑ 𝐵𝐵𝑖𝑖 𝑃𝑃𝑖𝑖 = 𝑃𝑃3 + 𝑃𝑃1 + 𝑃𝑃0 = 𝑄𝑄2 𝑄𝑄1 𝑄𝑄0 + 𝑄𝑄4 𝑄𝑄3 𝑄𝑄2 𝑄𝑄1 𝑄𝑄0 + 𝑄𝑄5 𝑄𝑄4 𝑄𝑄3 𝑄𝑄2 𝑄𝑄1 𝑄𝑄0 • The resulting circuit is shown below.

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Digital Logic Circuit Analysis and Design, 2nd Edition

4.49 Design a timing generator using the structure of Fig. P4.49a. The unit should generate four signals as shown in Fig. P4.49b to meet the following specification: f1 goes low on clock pulses 2, 9, 17, 30, and 60 f2 goes high on clock pulses 2, 8, 15, 35, and 56 f3 goes low on clock pulses 1, 8, 16, 37, and 63 f4 goes high on clock pulses 3, 27, 39, 41, and 63

Figure P4.49 (a) Block diagram. (b) Timing diagram.

A straightforward approach is to use a 6-to-64 decoder and logic gates to produce: 𝑓𝑓1 (𝐹𝐹, 𝐸𝐸, 𝐷𝐷, 𝐶𝐶, 𝐵𝐵, 𝐴𝐴) = � 𝑚𝑚(2,9,17,30,60) 𝑓𝑓2 (𝐹𝐹, 𝐸𝐸, 𝐷𝐷, 𝐶𝐶, 𝐵𝐵, 𝐴𝐴) = � 𝑚𝑚(2,8,15,35,56)

𝑓𝑓3 (𝐹𝐹, 𝐸𝐸, 𝐷𝐷, 𝐶𝐶, 𝐵𝐵, 𝐴𝐴) = � 𝑚𝑚(1,8,16,37,63)

𝑓𝑓4 (𝐹𝐹, 𝐸𝐸, 𝐷𝐷, 𝐶𝐶, 𝐵𝐵, 𝐴𝐴) = � 𝑚𝑚(3,27,39,41,63)

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Digital Logic Circuit Analysis and Design, 2nd Edition

Alternatively, a 64 x 4 PROM could be used, with the counter outputs connected to the PROM address lines, with each output producing one function. The patterns in the following table are stored at the indicated addresses (specified in hexadecimal) to produce the four functions.

FEDCBA 1 2 3 8 9 F 10 11 1B 23 25 26 27 29 38 3C 3F Others

f1 f1 f1 f1 1 0 0 0 = 8 0 1 1 0 = 6 1 0 1 1 = B 1 1 0 0 = C 0 0 1 0 = 2 1 1 1 0 = E 1 0 0 0 = 8 0 0 1 0 = 2 1 0 1 1 = B 1 1 1 0 = E 1 0 0 0 = 8 0 0 1 0 = 2 1 0 1 1 = B 1 0 1 1 = B 1 1 1 0 = E 0 0 1 0 = 2 1 0 0 1 = 9 1 0 1 0 = A

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Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 5 – Synchronous Sequential Circuit Analysis and Design 5.1 For the synchronous sequential circuit of Fig. P5.1, find: (a) The state table using K-maps and state assignment A ≡ 0, B ≡ 1. (b) The state diagram. (c) The timing diagram for an input sequence x = 00100110 and starting state y = 1.

Figure P5.1

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.2 Derive state diagrams for the Moore and Mealy circuits shown in Figure P5.2(a) and (b), and then complete the timing diagram for those circuits.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.3 For the sequential circuit in Fig. P5.3, find: (a) The state table ( A ≡ 0, B ≡ 1) . (b) The state diagram. (c) A timing diagram if the starting state is y = 0 and x = 001011000 .

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.4 From the following switching functions, 𝑧𝑧 = 𝐷𝐷1 = 𝑥𝑥𝑦𝑦�2 𝐷𝐷2 = 𝑥𝑥⨁𝑦𝑦1 (a) Draw the logic diagram for a synchronous sequential circuit using T flip-flops (b) Find a state diagram of the circuit using the assignment

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.5 For a sequential circuit realizing the following logic equations: 𝑌𝑌1 = 𝑥𝑥̅ ⊕ 𝑦𝑦1 Y2 = x + y1 + y2 z = xy1 y2 (a) Draw the logic diagram for a D flip-flop implementation of the circuit. (b) Find a binary state table for this circuit.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.6 Analyze the synchronous sequential circuit of Fig. P5.6. Assume the inputs are binary levels and that the following state assignment is used: Use K-maps to find: (a) The state table. (b) The state diagram.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.7 If the sequential circuit of Fig. P5.7 yields an output sequence z = 11011111 when we apply the input sequence x = 01101010 what is the starting state?

The initial values in the given input and output sequence are x = 0 and z = 1.

From the binary state table, if z = 1 when x = 0, the circuit can only be in state 1.

Therefore, starting state y = 1.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.8 Find the state table for the sequential circuit in Fig. P5.8.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.9 Consider a sequential circuit consisting of two cascaded circuits illustrated in Fig. P5.9. If the starting state is y1 = y2 = 0, what is the output sequence generated by the input sequence x = 0110111010

Time = 0 1 2 3 4 5 6 7 8 9 10 x= 0 1 1 0 1 1 1 0 1 0 y= A A C D A C A C D A A z1z2 = 00 11 10 00 11 00 11 10 00 00

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.10 Find the state diagram for the sequential circuit of Fig. P5.10 using the state assignment

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5.11 Find the state diagram for the sequential circuit of Fig. P5.11 using the indicated state assignment.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.12 Identify each of the state diagrams in Fig. P5.12 as being a Moore model or a Mealy model FSM and design a synchronous sequential circuit to realize each of the state diagrams. Use D flip-flops, and minimize each circuit as much as possible.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.13 Find the D flip-flop implementation for the sequential circuit defined by the following state table. Use the state assigment listed. Draw the logic circuit diagram.

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5.14 Obtain a D flip-flop realization for the synchronous sequential circuit specified by the following state table. Use the indicated state assignment. Write the combinational logic equations.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.15 Obtain a JK flip-flop realization of the synchronous sequential circuit described in problem 5.14.

The output equation is unchanged. The JK flip-flop excitation equations are derived as follows.

5.16 Determine four state diagrams for synchronous sequential circuits as specified by the following requirements. Each circuit has a single input line x and a single output line z . (a) The first circuit must produce an output z = 1 when two consecutive logic 1 inputs x have occurred. The next input after the two logic ones resets the output to logic 0. For example, x = 01100111110 z = 00100010100 State A: Looking for first 1.

State B: Last input was 1; looking for 2nd 1.

Start over in A after sequence 11 or 10

(b) The second circuit must detect the input sequence 101 by producing z = 1 as the last 1 occurs. The output z is reset to 0 on the next clock pulse. Two 101 sequences may overlap. For example, x = 010101101 z = 000101001 State A: Looking for first 1.

State B: Last input was 1; looking for 0.

State C: Last two inputs were 1-0, looking for 1.

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) Repeat Problem 5.16b but do not permit overlapping sequences. For example, x = 010101101 z = 000100001 State A: Looking for first 1.

State B: Last input was 1; looking for 0.

State C: Last two inputs were 1-0, looking for 1.

Start over after 1-0-1 received.

(d) The fourth circuit detects a 01 sequence. The sequence sets z = 1, which is reset only by a 00 input sequence. For all other cases, z = 0. For example, x = 010100100 z = 011110110 State A: Looking for first 0.

State B: Last input was 0; looking for 2nd 0.

State C: Last input was 1; looking for 1st 0.

The following state diagram is equivalent. It has a state D, but it can be shown that states B and D are equivalent, and thus D can be removed to derive the preceding state diagram.

State A: looking for 1st 0.

State B: last input was 0; looking for 1.

State C: last input was 1; looking for 0.

State D: last input was 0; looking for 0.

5.17 Derive the minimum state diagram of a clocked sequential circuit that recognizes the input sequence 1010. Sequences may overlap. For example, x = 00101001010101110 z = 00000100001010000 States: A: Looking for 1st 1.

B: Last input 1, looking for 0.

C: Last inputs 10, looking for 1.

D: Last inputs 101, looking for 0.

Overlap by returning from D to C.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.18 Find the state table of a synchronous sequential circuit that detects the input sequence 0101. The sequences may overlap as follows: x = 010101001101011 z = 000101000000010 States: A: Looking for 1st 0.

B: Last input 0, looking for 1.

C: Last inputs 01, looking for 0.

D: Last inputs 010, looking for 1.

Overlap by returning from D to C. 5.19 Obtain a minimum state diagram for a clocked sequential circuit that recognizes the input sequence 1001 including overlap. For example: x = 0101001000110010010 z = 0000001000000010010 States: A: Looking for 1st 1.

B: Last input 1, looking for 0.

C: Last inputs 10, looking for 0.

D: Last inputs 100, looking for 1.

Overlap by returning from D to B. 5.20 A synchronous sequential circuit is to have one input, X, and one output, Z. The circuit is to recognize the input sequence 11011 - output Z is to go to 1 whenever the last five inputs (values of X at the last 5 clock transitions) match this sequence, and Z is to be 0 otherwise. Design a minimal state diagram for this circuit, using a Mealy model.

States: A: Looking for 1st 1.

B: Last input 1, looking for 1.

C: Last inputs 11, looking for 0.

D: Last inputs 110, looking for 1.

E: Last inputs 1101, looking for 1.

Overlap by returning from E to C.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.21 Derive the logic equations to implement the four-state sequential circuit defined by the following state table, using the indicated state assignment and: (a) D flip-flops. (b) JK flip-flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.22 For the following circuit with the given state assignment, find a JK flip-flop implementation. Write the logic equations and sketch the logic diagram.

5.23 Implement the circuit of Problem 5.22 using D flip-flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.24 Given the following reduced state table and assignment, find the logic equations and logic diagram: (a) Using D flip-flops. (b) Using JK flip-flops.

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5.25 Find the logic diagram of an implementation of the following sequential circuit, given the state assignment and: (a) D flip-flops. (b) JK flip-flops.

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5.26 Find a JK flip-flop realization for the following reduced state table and assignment:

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5.27 Design a synchronous sequential circuit with two inputs, A and B, one output, Z, and a clock input, CLK. The circuit is to change states only on the rising edge of the clock. The circuit is to be designed as a Mealy model, using D flip-flops, and is to behave as follows.

• • •

On reset, Z=0.

Whenever Z=0, Z changes to 1 if and only if, while A=1, the values of B at two consecutive clock transitions are 0-1 (in that order). Z should change as soon as B becomes 1 in the second clock period.

Whenever Z=1, Z changes back to 0 if and only if, while B=0, the values of A at two consecutive clock transitions are 0-1. Z should change as soon as A becomes 1 in the second clock period.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.28 Design a synchronous sequential circuit with two inputs, I and J, one output, Z, and a clock input, CLK. The circuit is to change states only on the falling edge of the clock. The circuit is to be designed as a Moore model, using D flip-flops, and is to behave as follows.

• • •

On reset, Z=0.

Whenever Z=0, Z changes to 1 if and only if I and J are complementary values at two consecutive clock transitions.

Whenever Z=1, Z changes back to 0 if and only if I and J are both 0.

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5.29

Design the synchronous sequential circuit described in problem 5.28 using JK flip flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.30 Design a 2-bit binary up/down, modulo-3 up/down counter with the following function table, using JK flip-flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.31 Use D flip-flops to design a 3-bit counter/pseudorandom number generator. The circuit has one control input x . When x = 0 , the circuit should operate as a binary up-counter.

Otherwise, it should operate as a pseudorandom number generator according to the following function table.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.32 Use JK flip-flops to design a multifunction two-bit counter, where the count function is selected by two control signals, s1 and s0, as follows.

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5.33 Design the multifunction counter defined in Problem 5.32 using D flip-flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.34 Design a serial subtractor that will perform the operation A − B , where A = an −1  a1a0 and B = bn −1  b1b0 . The operands are applied to the serial subtractor sequentially, beginning with bits a0 and b0 . Use JK flip-flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

5.35 Design a serial parity generation circuit. The circuit receives a sequence of bits and determines whether the sequence contains an even or odd number of ones. The circuit output p should be 0 for even parity, that is, if the sequence contains an even number of ones, and 1 for odd parity.

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5.36 Design a logic circuit to implement the candy machine control unit designed in Figure 5.47. You may use either D or JK flip-flops.

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5.37 Design a logic circuit for the binary multiplier control unit whose ASM diagram was designed in Figure 5.48 using a minimum number of JK flip-flops.

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5.38 Modify the binary multiplier design of Figure 5.48 so that it will perform a binary division operation, dividing an 8-bit dividend by a 4-bit divisor using a sequence of subtract and shift operations. The dividend should initially be loaded into the A and Q registers and the divisor placed in the M register. At the end of the algorithm, the quotient should be in the Q register and the remainder in the A register.

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5.39 Find a minimized state table for the following synchronous sequential circuit by (a) Inspection. (b) Implication table.

(a) By inspection, states A and D produce identical outputs and are equivalent if B = E. States B and E produce identical outputs, and are equivalent if A = D. Therefore we can conclude that A = D and B = E. Removing rows D and E from the state table produces the reduced state table above. (b) The implication table is as follows. From this table, we identify equivalent pairs AD and BE, and thus we remove rows D and E to produce the reduced state table above.

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5.40 Reduce the following state tables by inspection: States A and B produce identical outputs, and their next states require only that A = B for them to be equivalent. Therefore we conclude that A = B. Removing row B produces the reduced state table.

• • • •

States A. D. amd F produce identical outputs. A and F do not depend on other states being equivalent, therefore A = F. For D to be equivalent to A or F requires E =G, which is not the case.

States B and E produce equivalent outputs and do not depend on any other states being equivalent, so B = E States C and G produce identical outputs and do not depend on any other states being equivalent, so C =G. The table is reduced by removing rows E, F, and G.

States A, B, E, and F produce identical outputs. A = B if E = D, and E = F if A = B. A and E require B = D, which is not the case; therefore A and E are not equivalent. We conclude that A = B and E = F. The state table is reduced by removing rows B and F, to produce the reduced state table above.

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5.41 Reduce the state tables of Problem 5.40 using implication tables.

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5.42 Find a reduced state table for each of the following synchronous sequential circuits:

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5.43 Using an implication table, reduce the following sequential circuit to a minimum number of states and draw the reduced state table.

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5.44 Reduce the number of states of the following sequential circuit using an implication table, and draw the reduced state table.

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5.45 Find a D flip-flop realization for the following sequential circuit using each of the three possible unique assignments for four-state circuits:

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5.46 For the following state table, find circuit implementations with each of the three possible unique state assignments for four-state circuits and memory elements of: (a) D flip-flops. (b) JK flip-flops.

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5.47 Derive the logic equations to implement the four-state sequential circuit defined by the following state table, using each of the three possible unique state assignments and: (a) D flip-flops. (b) JK flip-flops.

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5.48 A really old vending machine sells canned drinks for 15 cents, and accepts only nickels and dimes. Design a synchronous sequential circuit to control this vending machine according to the following specifications.

• The controller inputs are a clock CLK and two signals from a coin detector: N=1 if a nickel is deposited and D=1 if a dime is deposited. N and D return to 0 after the next clock transition.

• The controller is to have two outputs, A and C. If the amount deposited is greater than or equal to 15 cents, A should become 1 to activate the drink release mechanism. If the amount deposited is more than 15 cents, C should become 1 to activate a mechanism to release a nickel in change. After activating, A and C should return to 0 at the next clock transition.

• The controller is to be a Mealy model circuit, with the controller returning to is initial state after the amount deposited has reached at least 15 cents.

Design the controller using D flip-flops.

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5.49 Repeat the design of the vending machine controller in Problem 5.48 using a Moore model synchronous sequential circuit and D flip-flops.

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5.50 The Datapath of a digital system comprises three registers, R1, R2, and R3, connected as shown in Fig. P5.50a and enabled by control signals E1, E2, and E3, respectively. A Controller activates these control signals to enable register transfers according to the Control Algorithm defined by the ASM diagram in Fig. P5.50b. The Controller has three states (S0, S1, S2), an external input X, and the three outputs E1, E2, E3. The Controller is to change states on the rising edge of CLK. Use the one-hot design method to design a circuit to realize the control algorithm. (Do not design the Datapath – only the Controller.)

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Chapter 6 – Asynchronous Sequential Circuit Analysis and Design 6.1 Analyze the pulse-mode circuit shown in Fig. P6.1. (a) Determine a state table. (b) Construct a timing diagram for the circuit in response to the following input sequence.

Include x1 , x2 , x3 , y1 , y2 , J1 , K1 , J 2 , K 2 , Y1 , Y2 , and z in your diagram.

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6.2 Analyze the pulse-mode circuit shown in Fig. P10.2. Determine a state table.

Figure P6.2 Determine the output response to the input sequence x1 -- x2 -- x1 -- x1 -- x1 -- x1 -- x2 -- x2 if the starting state is 00. What form (level or pulse) will an output of z = 1 have? Why?

(b) Input pulses: State: Next state: Ouput:

x1 x2 x1 x1 x1 x1 x2 x2 A B A B D C A A B A B D C A A A 0 0 0 0 0 1 0 0

(c) The output will be a PULSE, since z = x1y1y2 and x1 is a pulse.

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6.3 Determine a realization of the following pulse-mode state table. Use JK flip-flops with AND, OR, and NOT gates.

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Digital Logic Circuit Analysis and Design, 2nd Edition

6.4 Design a pulse-mode circuit that meets the following specifications. Use AND, OR, and NOT gates with SR latches to realize the circuit. The circuit will have two inputs x1 and x2 and one output z . An output pulse will be produced simultaneously with the last of a sequence of three input pulses if and only if the sequence contained at least two x1 pulses.

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6.5 A pulse-mode sequential circuit is needed that satisfies the following requirements. Two input lines x1 and x2 will be provided along with one output line z . An output transition from 0 to 1 will be produced only on the occurrence of the last x2 pulse in the sequence x1 -- x2 -- x1 -- x2 . The output will be reset from 1 to 0 only by the first x1 pulse that occurs following the 0 to 1 output transition. Allow overlapping sequences. Design the circuit using T flip-flops with AND, OR, and NOT gates.

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6.6 Analyze the fundamental-mode circuit shown in Fig. P6.6. Determine the excitation table and output table. Construct a flow table. Use the flow table to determine the output response to the input sequence

x1 x2 : 00--01--11--10--00--01--00--10. Assume initially that x1 = x2 = y1 = y2 = Y1 = Y2 = 0 .

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6.7 Consider the circuit in Fig. P6.7a. Analyze the circuit as follows: Construct a timing diagram for the input sequence of Fig. P6.7b. Assume no delay in the logic gates. Also assume that initially y1 = Y1 = 1 and y2 = Y2 = 0 . Include x1 , x2 , y1 , y2 , Y1 , Y2 , and z in the timing diagram.

1 Repeat part (a) assuming that each logic gate has a delay of ∆t .

2

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6.8 Determine a primitive flow table for a fundamental-mode circuit that has the following requirements. One input x and one output z are needed. The output should follow the input on every other 0--1--0 transition, as indicated in Fig. P6.8.

6.9 A fundamental-mode circuit must be designed to satisfy the following requirements.

Two inputs ( x1 , x2 ) and one output (z ) are required. The output z = 0 will always be produced when x1 = x2 . When x1 = 0 and x2 changes from 0 to 1, an output z = 1 must occur. When x1 = 1 and x2 changes from 1 to 0, an output z = 1 must occur. Otherwise, no input change will cause an output change. Determine a primitive flow table for the circuit.

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Digital Logic Circuit Analysis and Design, 2nd Edition

6.10 Construct a primitive flow table for a fundamental-mode circuit with the following specifications. The circuit must have two inputs ( x1 , x2 ) and two outputs ( z1 , z 2 ) .

When x1 = x2 = 0 , the outputs must be z1 = z 2 = 0 . If x1 = 1 and x2 changes from 0 to 1, an output z1 = 0 , z 2 = 1 will be produced. If x2 = 1 and x1 changes from 0 to 1, an output z1 = 1, z 2 = 0 will be produced. Outputs are reset to z1 = z 2 = 0 only when both x1 and x2 equal 0. No output change is produced by any other input change.

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6.11 Reduce the following primitive flow table to a minimum flow table.

6.12 Repeat Problem 6.11 for the following primitive flow table.

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6.13 Determine a circuit realization for the following reduced flow table. Use the indicated state assignment. Assume AND, OR, and NOT gates are available for use in the realization.

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6.14 Determine a minimum row flow table compatible with the following primitive flow table.

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6.15 Repeat Problem 6.13 for the following flow table, but assume that only NAND gates are available for use in the circuit.

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6.16 Repeat Problem 6.13 for the following reduced flow table.

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6.17 Given the excitation table below. Find all race conditions in the table. Are the races critical or noncritical? Do any cycles exist in the table?

(a) Race conditions in the table: Race: x1x2y1y2 = 0100 → 1100 If y1 changes first, erroneous stable state 1110 is entered.

If y2 changes first, state 1101 is entered, with the possibility then of either going on to correct stable state 1111 or back to transient state 1100, which is an oscillatory condition.

Race: x1x2y1y2 = 0101 → 1101 Also: x1x2y1y2 = 1001 → 1101 If y1 changes first, circuit stabilizes in erroneous state 1111.

If y2 changes first, transient state 1100 is entered, after which the circuit could either go on to the correct stable state of 1110 or else return to transient state 1101, which is an oscillatory condition. (b) All three race conditions are critical. (c) One cycle: 0011 → 0111 → 0110 → 0100

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Digital Logic Circuit Analysis and Design, 2nd Edition

6.18 Analyze the circuit in Fig. P6.18 to determine if the circuit has a critical race. If so, draw a timing diagram to show the effect that the race can have on the circuit response.

Race: x1x2y1y2 = 0111 → 0011 Also: x1x2y1y2 = 1011 → 0011 If y1 changes first, erroneous stable state 0001 is entered.

If y2 changes first, state 0010 is entered, and then the correct stable state 0000.

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6.19 Repeat Problem 10.18 for the circuit shown in Fig. P6.19.

Critical race: x1x2y1y2 = 0101 → 1101 If y2 changes first, erroneous stable state 1100 is entered.

If y1 changes first, unstable state 1111 is entered and then the circuit wil either go to the correct state 1110, or else return to unstable state 1111, which would result in oscillation.

Critical race: x1x2y1y2 = 0111 → 1111 Also: x1x2y1y2 = 1011 → 1111 If y2 changes first, erroneous stable state 1110 is entered.

If y1 changes first, unstable state 1101 is entered and then the circuit wil either go to the correct state 1100, or else return to unstable state 1111, which would result in oscillation.

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6.20 Determine a critical race-free state assignment for the following reduced flow table.

Construct the corresponding excitation table.

6.21 Repeat Problem 6.20 for the following reduced flow table.

6.22 Given the following reduced flow table.

(a) Use method 1 to find a critical race-free assignment for the table. Construct the corresponding excitation table.

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(b) Repeat part (a) using method 2.

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6.23 A fundamental-mode circuit is to be designed to function as an electronic lock. The lock has two switch inputs (x1 and x2 ) . Design the circuit so that an open signal (z = 1) is produced only after the following conditions have been satisfied.

1. Begin with x1 = x2 = 0 .

2. While x2 = 0, x1 is turned on, then off twice.

3. While x1 remains off, x2 is turned on to open the lock.

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6.24 A fundamental-mode asynchronous sequential circuit is defined in Fig. P6.24 and the following equations.

Y1 = x2 y2 + x1 y1 + x1 x2 Y2 = x1 y2 + x1 x2 + x2 y1 z = x1 x2 + x2 y1 + x1 y2 (a) Find a flow table.

(b) Using the flow table developed in part (a), find the output sequence for the input sequence x1 x2 = 00, 01, 11, 10, 11, 01, 00, 10 if the delay lines are initially at zero (stable state x1 = x2 = y1 = y2 = 0) . x1x2 = 00 01 11 10 11 01 00 10 y1y2 = 00 01 00 10 11 01 11 10 z= 0 1 1 1 0 1 1 1

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6.25 Given the following reduced flow table, find a critical race-free secondary state assignment for this asynchronous sequential circuit. Find a two-level NOR realization using inertial delay elements.

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6.26 Find a two-level NAND realization for the following primitive flow table.

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6.27 Find a two-level NOR implementation for a fundamental-mode asynchronous sequential circuit with two inputs ( x1 , x2 ) and one output (z ) that satisfies the following conditions: First, z is always zero when x2 = 1 . The output z changes to logic 1 on the first 0 → 1 transition of x1 when x2 = 0 and remains at logic 1 until x2 goes to logic 1 and forces z back to logic 0.

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6.28 Find a two-level NAND realization of a fundamental-mode circuit that has two inputs ( x1 , x2 ) and one output ( z ) that satisfies the following conditions: First, z = 0 when x1 = 0 . The output z goes to logic 1 on the first 1 → 0 transition of x2 when x1 = 1 .

The output remains at logic 1 until x1 returns to 0.

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6.29 Consider the asynchronous sequential circuit presented in Fig. P6.29. If the circuit input is synchronous pulses, determine the following. (a) The state table if A ≡ 0, B ≡ 1. (b) The state diagram. (c) The timing diagram for x = 010011010 and y 0 = 0.

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Digital Logic Circuit Analysis and Design, 2nd Edition

6.30 Analyze the asynchronous sequential circuit of Fig. P6.30. This circuit has synchronous pulses as its input x. Construct the following. (a) A timing diagram for the input sequence x = 01101000 and y 0 = 0. (b) A state table. (c) A state diagram.

In your solution you may define the pulse widths of the input x to be equal to the time delay of the T flip-flop. Discuss what effect the following condition will have on the operation of this sequential circuit: Allow the input pulse to be somewhat longer than the flip-flop time delay. Show your conclusions on the timing diagram for part (a).

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Digital Logic Circuit Analysis and Design, 2nd Edition

6.31 Analyze the asynchronous sequential circuit of Fig. P6.31 if the circuit input x is in the form of synchronous pulses. Find the following. (a) The timing diagram if x = 01010010100 and y10 y20 = 11. (b) The state table. (c) The state diagram.

Hint: K-maps yield incorrect results because assumption 3 for pulse-type circuits is violated.

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Digital Logic Circuit Analysis and Design, 2nd Edition

6.32 Given the digital combination lock designed in Section 6.2.2 as a pulse-mode circuit.

Redesign the machine as a fundamental-mode circuit.

From the critical transition graph, we can make the state assignment shown in the above table that which satisfies all adjacency requirements except for state pairs e-m, g-l, and i-l. Using a few unspecified next states in the flow table, the following cycles can be created to avoid race conditions: e-j-k-l, g-n-k-l, and i-j-k-l. The resulting race-free excitation table is shown below, with the cycles indicated in blue. For better visibility, the four columns corresponding to all don’t-care conditions are not shown.

Logic equations can be derived from the excitation for next state variables Y3, Y2, Y1, Y0. By inspection, z = 1 for exactly one condition (state j with a 1 on input x2), giving 𝑧𝑧 = 𝑥𝑥2 𝑦𝑦3 𝑦𝑦�2 𝑦𝑦1 𝑦𝑦0 .

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6.33 Given the Vending machine controller in Section 6.5.2. Redesign the controller so that it gives change when $1.25 or $1.50 is deposited.

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6.34 Redesign the Vending machine controller of Section 6.5.2 as a pulse-mode circuit. Use JK flip-flops for memory.

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6.35 Realize Arbiter3 with AND, OR, and NOT gates.

Rearranging the excitation and output tables in Gray Code order produces:

We can use six-variable K-maps to generate next state and output equations:

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The AND-OR-NOT circuit is on the next page.

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6.36 Use Method 2 to find a race-free excitation table for Arbiter3, designed in Section 6.5.3.

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Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 7 – Programmable Digital Logic Devices 7.1

From a manufacturer’s web site, look up and compare information about two commercial FPGA devices, one “low end” and one “high end” device. For each device, list the number of logic cells, input/output pins, and embedded modules within the FPGA (memory, DSP, embedded processor, communication modules, etc.), as well as the programming technology (SRAM, antifuse, etc.)

Example: Feature Logic cells I/O pins Block memory DSP blocks Clock management Configuration bits

7.2

Xilinx Virtex UltraScale+ VU19P 9,938 2,072 224Mbits 3,840 40 tiles

From a manufacturer’s web site, look up and compare information about two commercial CPLD devices, one “low end” and one “high end” device. For each device, summarize its features (logic elements, input/output pins, and embedded modules such as RAM, DSP, embedded processors, etc.) , as well as the device programming technology (SRAM, antifuse, etc.).

Example: Feature Logic elements I/O pins User flash memory Clobal clocks Configuration

7.3

Xilinx Spartan 7 XC7S6 6,000 100 180Kbits 10 2 tiles SRAM

Intel MAX II – EPM240 Intel Max V – 5M2210Z 6,000 2,210 80 271 8Kbits 8Kbits 2 4 SRAM loaded from flash memory

The 22V10 programmable logic device has been manufactured in different technologies by different vendors. Loop up a data sheet for one 22V10 device and summarize its characteristics, including number of inputs and outputs, number of products per sum term in the PAL of the device, and output macrocell options.

Example: Lattice Semiconductor GAL22V10.

• 10 macrocells with programmable I/O pins • 12 dedicated inputs • 44 total inputs to the AND array • Sum of products: 2 macrocells each with 8, 10, 12, 14, 16 product terms • Outputs configurable as combinational or flip-flop, active-high or active-low.

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7.4

For one vendor’s FPGA development suite of tools, describe the implementation steps that must be performed by the tools to implement a design in a selected FPGA device, from the development of an HDL model of a design to programming the selected FPGA device.

Example: Xilinx Vivado: • Enter the HDL model(s).

• Perform behavioral simulation to verify the design.

• Synthesize the HDL model into generic digital components.

• Map and optimize the synthesized design onto FPGA primitive components.

• Place components onto specific elements within the FPGA array.

• Route connections between the placed components.

• Simulate the final implemented design to verify behavior and timing.

• Generate a configuration file for programming the FPGA • Download the configuration file to the FPGA to program it.

7.5

Design a BCD to two-out-of-five code converter (refer to Chapter 1) using: (a) FPGA lookup tables (specify the contents of each as a truth table) Decimal Two-Out-Of Five 4-input lookup tables (LUTs) are required. Each Digit -Five Code provides one bit ck of the two-out-of-five code. The BCD d3d2d1d0 c4c3c2c1c0 code bits are the LUT address inputs and the LUT contents 0000 0 0 0 1 1 are as indicated in this truth table. Addresses 10-15 of 0001 0 0 1 0 1 each LUT are unused, and their contents are don’t cares.

0010 0 1 0 0 1 0011 1 0 0 0 1 0100 0 0 1 1 0 0101 0 1 0 1 0 0110 1 0 0 1 0 0111 0 1 1 0 0 1000 1 0 1 0 0 1001 1 1 0 0 0 LUT4 LUT3 LUT2 LUT1 LUT0

(b) PLA (list the product and sum terms) Plotting the truth table of part (a) on K-maps produces the following output equations, comprising 14 unique product terms and five sums. Multiple-output minimization methods can reduce the total number of product terms to 11 as follows. 𝑐𝑐0 = 𝑑𝑑̅3 𝑑𝑑̅2 = 𝑃𝑃1 𝑐𝑐1 = 𝑑𝑑̅3 𝑑𝑑1̅ 𝑑𝑑̅0 + 𝑑𝑑2 𝑑𝑑1̅ + 𝑑𝑑2 𝑑𝑑̅0 = 𝑑𝑑̅3 𝑑𝑑1̅ 𝑑𝑑̅0 + 𝑑𝑑2 𝑑𝑑1̅ 𝑑𝑑̅0 + 𝑑𝑑2 𝑑𝑑1̅ 𝑑𝑑0 + 𝑑𝑑2 𝑑𝑑1 𝑑𝑑̅0 = 𝑃𝑃2 + 𝑃𝑃3 + 𝑃𝑃4 + 𝑃𝑃5 𝑐𝑐2 = 𝑑𝑑3 𝑑𝑑̅0 + 𝑑𝑑2 𝑑𝑑1̅ 𝑑𝑑̅0 + 𝑑𝑑2 𝑑𝑑1 𝑑𝑑0 + 𝑑𝑑̅3 𝑑𝑑̅2 𝑑𝑑1̅ 𝑑𝑑0 = 𝑃𝑃6 + 𝑃𝑃3 + 𝑃𝑃7 + 𝑃𝑃8 𝑐𝑐3 = 𝑑𝑑3 𝑑𝑑0 + 𝑑𝑑2 𝑑𝑑0 + 𝑑𝑑̅2 𝑑𝑑1 𝑑𝑑̅0 = 𝑑𝑑3 𝑑𝑑0 + 𝑑𝑑2 𝑑𝑑1̅ 𝑑𝑑0 + 𝑑𝑑2 𝑑𝑑1 𝑑𝑑0 + 𝑑𝑑̅2 𝑑𝑑1 𝑑𝑑̅0 = 𝑃𝑃9 + 𝑃𝑃4 + 𝑃𝑃7 + 𝑃𝑃10 𝑐𝑐4 = 𝑑𝑑3 + 𝑑𝑑̅2 𝑑𝑑1 𝑑𝑑0 + 𝑑𝑑2 𝑑𝑑1 𝑑𝑑̅0 = 𝑑𝑑3 𝑑𝑑̅0 + 𝑑𝑑3 𝑑𝑑0 + 𝑑𝑑̅2 𝑑𝑑1 𝑑𝑑0 + 𝑑𝑑2 𝑑𝑑1 𝑑𝑑̅0 = 𝑃𝑃6 + 𝑃𝑃9 + 𝑃𝑃11 + 𝑃𝑃5

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) PROM (list the minterms in each sum term) – Minterms are from the truth table in part (a).

(d) PAL (list the product and sum terms) A PAL with four products per sum term is required (for at least one of the otuputs), since c2 has four product terms. The product and sum terms are the first set of terms listed in part (a).

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7.6

Implement the following three functions using the following approaches.

𝑓𝑓1 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(0,1,2,3,6,9,11) 𝑓𝑓2 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(0,1,6,8,9) 𝑓𝑓3 (𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = Σ𝑚𝑚(2,3,8,9,11)

(a) 4-input FPGA lookup tables (list the contents of each as a truth table) A B C D f1 f2 f3 0000 1 1 0 0001 1 1 0 0010 1 0 1 0011 1 0 1 0100 0 0 0 0101 0 0 0 0110 1 1 0 0111 0 0 0 1000 0 1 1 1001 1 1 1 1010 0 0 0 1011 1 0 1 1100 0 0 0 1101 0 0 0 1110 0 0 0 1111 0 0 0 LUT1 LUT2 LUT3

(b) PLA (determine the number of product and sum terms and list them) Examining K-maps of the three functions, minimization of the three functions independently produces eight unique product terms, including the first expressions below for f1 and f2.

However, minimized the three functions concurrently, expanding f1 and f2 as shown in the second expression below each map, we can see that the three functions can be implemented in a PLA with a total of six product terms, with several product terms used in multiple functions.

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) PROM (determine the number of product and sum terms, and list the sum terms) The given minterm lists are combined as shown here to produce each of the three functions.

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) PAL (determine the number of product and sum terms and list them) Using the first expressions in the K-maps of part (b), we require three sums containing, three, two, and three product terms as follows:

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.7

Realize the following set of three switching functions. 𝑓𝑓1 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑎𝑎𝑏𝑏�𝑐𝑐 + 𝑏𝑏�𝑑𝑑 + 𝑎𝑎�𝑐𝑐𝑐𝑐 = ∑ 𝑚𝑚(1,3,7,9,10,11)

𝑓𝑓2 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = �𝑎𝑎 + 𝑏𝑏� + 𝑐𝑐��𝑏𝑏� + 𝑑𝑑�(𝑎𝑎� + 𝑐𝑐 + 𝑑𝑑) = ∏ 𝑀𝑀(4,5,6,8,12,14) = Σ𝑚𝑚(0,1,2,3,7,9,10,11,13,15) 𝑓𝑓3 (𝑎𝑎, 𝑏𝑏, 𝑐𝑐, 𝑑𝑑) = 𝑎𝑎𝑏𝑏�(𝑐𝑐̅ + 𝑑𝑑) + 𝑏𝑏(𝑎𝑎�𝑑𝑑 + 𝑐𝑐𝑐𝑐) = ∑ 𝑚𝑚(5,7,8,9,11,15)

(a) 4-input FPGA lookup tables (list the contents of each in the form of a truth table).

ABCD f1 f2 f3 0000 0 1 0 0001 1 1 0 0010 0 1 0 0011 1 1 0 0100 0 0 0 0101 0 0 1 0110 0 0 0 0111 1 1 1 1000 0 0 1 1001 1 1 1 1010 1 1 0 1011 1 1 1 1100 0 0 0 1101 0 1 0 1110 0 0 0 1111 0 1 1 LUT1 LUT2 LUT3

(b) A PLA (determine the number of product and sum terms and list them).

Note that f1 and f2 share their first product term, for PLA implementation.

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Digital Logic Circuit Analysis and Design, 2nd Edition

(c) A PROM (determine the number of product and sum terms and list the sum terms).

Combine minterms from the truth table in part (a).

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Digital Logic Circuit Analysis and Design, 2nd Edition

(d) A PAL (determine the number of product and sum terms and list them).

Using the K-maps from part (a), we need a PAL with 3 OR functions, combining, 4, and 3 product terms for the three functions.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.8

Use a 32× 6 PROM to convert a 6-bit binary number to its corresponding 2-digit BCD representation.

(a5 a4 a3a2 a1a0 ) 2 = [( x3 x2 x1 x0 ) BCD ( y3 y2 y1 y0 ) BCD ]10 Show the PROM's contents in a truth table format. ( Hint: x3 = 0 , and y0 = a0 .) a5a4a3a2a

x2 x1 x0

y3 y2 y1

a5a4a3a2a1

x2 x1 x0

y3 y2 y1

1

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 FPGA LUTS:

7.9

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 4 7 10 13 16

10000 0 0 1 0 1 1 10001 0 0 1 0 1 1 10010 0 0 1 1 0 0 10011 0 0 1 1 0 0 10100 0 1 0 0 0 0 10101 0 1 0 0 0 0 10110 0 1 0 0 0 1 10111 0 1 0 0 0 1 11000 0 1 0 0 1 0 11001 0 1 0 0 1 0 11010 0 1 0 0 1 1 11011 0 1 0 0 1 1 11100 0 1 0 1 0 0 11101 0 1 0 1 0 0 11110 0 1 1 0 0 0 11111 0 1 1 0 0 0 LUTS: 2 5 8 11 14 17

Repeat problem 7.8 using an FPGA with 4-input lookup tables (LUTs). Sketch the LUTs and their interconnections and list the contents of each LUT as a truth table.

The design requires 18 LUTs, configured as six sets of three LUTs arranged to create a 32-to-1 LUT. The first LUT in each set of three contains the 16 bits of the truth table indicated above, for a5 = 0.

The second LUT in the set contains the 16 truth table bits for a5 = 1. LUTs 3, 6, 9, 12, 15 and 18 are programmed as 2-to-1 multiplexers, as in the following truth table, selecting the lower LUT output when a5 = 0 and the upper LUT output when a5 = 1.

2-to-1 Multiplexer (A2 is the select line) A3A2A1A0

Y

0000 0001 0010 0011 0100 0101 0110 0111 others

0 1 0 1 0 0 1 1 -

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.10 Using only four-input lookup tables, design an FPGA implementation of a five-input ``majority voter'', with inputs A, B, C, D, E, and output V, where output V is to be 1 if a majority of the inputs is 1; the V output is otherwise to be 0. Sketch the lookup tables and their interconnections, and list the contents of each lookup table as a truth table.

ABCDE

Y

ABCDE

Y

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111

0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1

10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1

LUT1 contains the 16 bits in the first column of the truth table, for A = 0, and LUT2 contains the 16 bits in the second column of the truth table, for A = 1.

LUT3 is configured as a 2-to-1 multiplexer to select the output of LUT1/LUT2 for A = 0/1, respectively.

(Truth table for LUT 3 is provided in problem 7.9.

7.11 Repeat the majority voter design of problem 7.10 for a PLA device.

• Specify the parameters of the required PLA (number of inputs, products, and sums).

• List the product and sum terms that would be implemented in the PLA. 𝑉𝑉 = 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐶𝐶𝐶𝐶𝐶𝐶

The PLA requires 5 inputs, 10 product terms, and one sum term.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.12 Design the four-state synchronous sequential circuit defined by the following state table for implementation in an FPGA, using the indicated state assignment. This FPGA contains configurable logic blocks as shown in Figure 7.10, each containing a three-input lookup table (LUT) and a D flipflop. Sketch a diagram showing LUTs and flip-flops and their inteconnections, including input and output signals, and write truth tables of the logic functions to be implemented in the LUTs.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.13 Design the synchronous sequential circuit of Problem 7.12 for a registered PAL device, similar to the one shown in Figure 7.71, by driving appropriate logic equations that can be implemented in the AND-OR array of the PAL. You may assume that each OR function has a sufficient number of product terms to accommodate this design.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.14 Design an FPGA implementation of a synchronous sequential circuit with one input x and one output z that recognizes the input sequence 1010. Sequences may overlap. For example,

x = 00101001010101110 z = 00000100001010000

The FPGA contains configurable logic blocks as shown in Figure 7.10, each containing a lookup table (LUT) and a D flip-flop. You may assume that the LUTs have a sufficient number of inputs to accommodate this design. Sketch a diagram showing LUTs and flip-flops and their inteconnections, including input and output signals, and write truth tables of the logic functions to be implemented in the LUTs.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.15 Given the following reduced state table and assignment of a synchronous sequential circuit logic, design the circuit using: (a) An FPGA containing configurable logic blocks as shown in Figure 7.10, which each containing a three-input lookup table (LUT) and a D flip-flop. Sketch a diagram showing connections between the LUTs and flip-flops, and list the LUT contents as truth tables.

(b) A registered PAL with one combinational output and two registered outputs. The latter are also fed back to the AND array. List logic equations for each flip-flop input and the output, as they would be implemented in the PAL.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.16 Design the Moore model sequential circuit described by the state table and state assignment given below, using the following devices (do not use combinational outputs). (a) An FPGA containing configurable logic blocks as shown in Figure 7.10, which each containing a three-input lookup table (LUT) and a D flip-flop. Sketch a diagram showing connections between the LUTs and flip-flops, and list the LUT contents as truth tables.

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(b) A registered PAL with one combinational output and two registered outputs. The latter are also fed back to the AND array. List logic equations for each flip-flop input and the output, as they would be implemented in the PAL.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.17 For the reduced state table and the one-hot state assignment shown below, determine how this would be implemented in: (a) An FPGA containing configurable logic blocks as shown in Figure 7.10, which each containing a three-input lookup table (LUT) and a D flip-flop. Sketch a diagram showing connections between the LUTs and flip-flops, and list the LUT contents as truth tables.

For the one-hot state assignment, the state table can be redrawn by substituting the active state variable for each symbolic state name. LUTs for each next state and the output can be derived by inspection from the converted state table by noting the condition that results in entering each state, and the conditions that set the output. Note that next state C is entered from states B, C, and E, and is thus dependent on input x and three state variables. Since the LUTs have only 3 inputs, LUT3 generates partial term P3 from x, y2 and y3, and then LUT4 produces Y3 from P3, x and the third state variable y5. Likewise, output z depends on x and 4 state variables. In this case, partial terms Z1 and Z2 are created with LUT5 and LUT9, and LUT10 ORs these to create ouput z.

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(b) A registered PAL with six registered outputs that are also fed back to the AND array. List logic equations for each flip-flop input, as they would be implemented in the PAL. The following logic expressions can be derived by inspection of the converted state table: State A: 𝑌𝑌1 = 𝑥𝑥̅ 𝑦𝑦2 + 𝑥𝑥𝑦𝑦5 State B: 𝑌𝑌2 = 𝑥𝑥̅ 𝑦𝑦1 + 𝑥𝑥̅ 𝑦𝑦4 State C: 𝑌𝑌3 = 𝑥𝑥𝑦𝑦2 + 𝑥𝑥𝑦𝑦3 + 𝑥𝑥̅ 𝑦𝑦5 State D: 𝑌𝑌4 = 𝑥𝑥𝑦𝑦1 + 𝑥𝑥̅ 𝑦𝑦3 State E: 𝑌𝑌5 = 𝑥𝑥𝑦𝑦4 + 𝑥𝑥̅ 𝑦𝑦6 State F: 𝑌𝑌6 = 𝑥𝑥𝑦𝑦6 Ouptut: 𝑧𝑧 = 𝑥𝑥𝑦𝑦2 + 𝑥𝑥̅ 𝑦𝑦3 + 𝑥𝑥𝑦𝑦4 + 𝑥𝑥̅ 𝑦𝑦4 + 𝑥𝑥𝑦𝑦6 = 𝑥𝑥𝑦𝑦2 + 𝑥𝑥̅ 𝑦𝑦3 + 𝑦𝑦4 + 𝑥𝑥𝑦𝑦6

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.18 A Moore model synchronous sequential circuit has one input A, one output Z, and a clock CLK (the state changes on the rising edge of CLK). Z is to become 1 whenever A is 0 on one clock transition, followed by 1 on the next clock transition. Z is to be 0 otherwise. Design an HDL behavioral model of this circuit and use FPGA development tools to implement it in an FPGA. Determine the number of components used in the implementation (LUTs, flip-flops, and input/output pins.)

Implementation of the following HDL models in a Xilinx Artix-7 FPGA, using the Xilinx Vivado tool, resulted in a circuit comprising: two input pins with input buffers (IBUF) for inputs A and CLK, a global clock buffer BUFG), two D flip-flops for the state variables, three LUTs (one for each D flipflop input and one for output Z), and one output pin with buffer (OBUF) for output Z. -- VHDL Problem 7.18 Moore model sequential circuit entity Problem7_18_Moore is port (A: in bit; -- signal input Z: out bit; -- output CLK: in bit); -- clock input end Problem7_18_Moore; architecture behavior of Problem7_18_Moore is type states is (S0, S1, S2); -- state names signal state: states := S0; -- state of the circuit begin Z <= ‘1’ when state = S2 else ‘0’; -- Z=1 only in state S2 process (CLK) begin if rising_edge(CLK) then case (state) is when S0 => if A = ‘0’ then state <= S1; -- last A = 0 else state <= S0; -- wait for A = 0 end if; when S1 => if A = ‘0’ then state <= S1; -- last A still 0 else state <= S2; -- 0 followed by 1 end if; when S2 => if A = ‘0’ then state <= S1; -- last A = 0 else state <= S0; -- start over end if; end case; end if; end process; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Verilog Problem 7.18 Moore model sequential circuit module Problem7_18_Moore (A, Z, CLK); input A, CLK; output Z; reg [1:0] state; parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10; //state names assign Z = (state == S2) ? 1’b1 : 1’b0; // Z=1 in state S2 initial state <= S0; // Start in S0 always @(posedge CLK) begin case (state) S0: if (A == 1’b0) state <= S1; else state <= S0; //to S1 if A=0 S1: if (A == 1’b0) state <= S1; else state <= S2; //to S2 if A=1 S2: if (A == 1’b0) state <= S1; else state <= S0; //back to S1 if A=0 endcase end endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.19 Design a 4-bit bidirectional shift register for implementation in a registered PAL by deriving logic equations that can be implemented in the AND-OR array for each flip-flop input. The shift register is to have serial inputs Sin-Right and Sin-Left, parallel inputs A, B, C, D, parallel outputs QA, QB, QC, QD, a clock input CLK, and two function select inputs S1S0. The shift register functions are defined in the following table: S1 0 0 1 1

S2 0 1 0 1

Mode No operation Load Shift right, QA = Sin-Right Shift left, QD = Sin-Left

By inspection from the function table: 𝐷𝐷𝐴𝐴 = (𝑆𝑆1̅ 𝑆𝑆2̅ )𝑄𝑄𝐴𝐴 + (𝑆𝑆1̅ 𝑆𝑆2 )𝐴𝐴 + (𝑆𝑆1 𝑆𝑆2̅ )𝑆𝑆𝑅𝑅 + (𝑆𝑆1 𝑆𝑆2 )𝑄𝑄𝐵𝐵 𝐷𝐷𝐵𝐵 = (𝑆𝑆1̅ 𝑆𝑆2̅ )𝑄𝑄𝐵𝐵 + (𝑆𝑆1̅ 𝑆𝑆2 )𝐵𝐵 + (𝑆𝑆1 𝑆𝑆2̅ )𝑄𝑄𝐴𝐴 + (𝑆𝑆1 𝑆𝑆2 )𝑄𝑄𝐶𝐶 𝐷𝐷𝐶𝐶 = (𝑆𝑆1̅ 𝑆𝑆2̅ )𝑄𝑄𝐶𝐶 + (𝑆𝑆1̅ 𝑆𝑆2 )𝐶𝐶 + (𝑆𝑆1 𝑆𝑆2̅ )𝑄𝑄𝐵𝐵 + (𝑆𝑆1 𝑆𝑆2 )𝑄𝑄𝐷𝐷 𝐷𝐷𝐷𝐷 = (𝑆𝑆1̅ 𝑆𝑆2̅ )𝑄𝑄𝐷𝐷 + (𝑆𝑆1̅ 𝑆𝑆2 )𝐷𝐷 + (𝑆𝑆1 𝑆𝑆2̅ )𝑄𝑄𝐶𝐶 + (𝑆𝑆1 𝑆𝑆2 )𝑆𝑆𝐿𝐿

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.20 Design a 4-bit up/down, modulo-12 counter for implementation in a PAL device, in which each output is provided by a macrocell of the structure of Figure 7.72. The counter is to have parallel inputs D, C, B, A, outputs QD, QC, QB, QA, clock input CLK, and two function select inputs S1S0. The counter functions are defined in the following table: S1 0 0 1 1

S2 0 1 0 1

Mode No operation Load Count up Count down

(a) Derive logic equations suitable for implementation in the AND-OR array of a PAL device. 𝐷𝐷𝐴𝐴 = 𝑆𝑆1̅ 𝑆𝑆2̅ 𝑄𝑄𝐴𝐴 + 𝑆𝑆1̅ 𝑆𝑆2 𝐴𝐴 + 𝑆𝑆1 𝑆𝑆2̅ (𝑄𝑄�𝐴𝐴 ) + 𝑆𝑆1 𝑆𝑆2 (𝑄𝑄�𝐴𝐴 ) 𝐷𝐷𝐵𝐵 = 𝑆𝑆1̅ 𝑆𝑆2̅ 𝑄𝑄𝐵𝐵 + 𝑆𝑆1̅ 𝑆𝑆2 𝐵𝐵 + 𝑆𝑆1 𝑆𝑆2̅ (𝑄𝑄�𝐵𝐵 𝑄𝑄𝐴𝐴 + 𝑄𝑄𝐵𝐵 𝑄𝑄�𝐴𝐴 ) + 𝑆𝑆1 𝑆𝑆2 (𝑄𝑄�𝐵𝐵 𝑄𝑄�𝐴𝐴 + 𝑄𝑄𝐵𝐵 𝑄𝑄𝐴𝐴 ) 𝐷𝐷𝐶𝐶 = 𝑆𝑆1̅ 𝑆𝑆2̅ 𝑄𝑄𝐶𝐶 + 𝑆𝑆1̅ 𝑆𝑆2 𝐶𝐶 + 𝑆𝑆1 𝑆𝑆2̅ (𝑄𝑄�𝐶𝐶 𝑄𝑄𝐴𝐴 + 𝑄𝑄𝐶𝐶 𝑄𝑄�𝐴𝐴 + 𝑄𝑄�𝐷𝐷 𝑄𝑄�𝐶𝐶 𝑄𝑄𝐵𝐵 𝑄𝑄𝐴𝐴 ) + 𝑆𝑆1 𝑆𝑆2 (𝑄𝑄𝐶𝐶 𝑄𝑄𝐴𝐴 + 𝑄𝑄𝐶𝐶 𝑄𝑄𝐵𝐵 + 𝑄𝑄𝐷𝐷 𝑄𝑄�𝐵𝐵 𝑄𝑄�𝐴𝐴 ) 𝐷𝐷𝐷𝐷 = 𝑆𝑆1̅ 𝑆𝑆2̅ 𝑄𝑄𝐷𝐷 + 𝑆𝑆1̅ 𝑆𝑆2 𝐷𝐷 + 𝑆𝑆1 𝑆𝑆2̅ (𝑄𝑄𝐷𝐷 𝑄𝑄�𝐵𝐵 + 𝑄𝑄𝐷𝐷 𝑄𝑄�𝐴𝐴 + 𝑄𝑄𝐶𝐶 𝑄𝑄𝐵𝐵 𝑄𝑄𝐴𝐴 ) + 𝑆𝑆1 𝑆𝑆2 (𝑄𝑄𝐷𝐷 𝑄𝑄𝐴𝐴 + 𝑄𝑄𝐷𝐷 𝑄𝑄𝐵𝐵 + 𝑄𝑄�𝐷𝐷 𝑄𝑄�𝐶𝐶 𝑄𝑄�𝐵𝐵 𝑄𝑄�𝐴𝐴 )

The first term in each expression above represents the hold condition and the second term is the load condition. The third and fourth terms represent the count-up and count-down conditions, respectively, which can be determined from the count sequences and K-maps. (b) Indicate the characteristics of the registered PAL required to implement the counter: number of inputs, number of product terms in each OR function, and the options selected in each macrocell.

The PAL requires six input (D, C, B, A, S1 and S0). The OR functions for flip-flop inputs QA, QB, QC, and QD require 4, 6, 8 and 8 product terms, respectively. Each of the four macrocells should connect the flip-flop output to its respective output pin, and feed back both the complemented and uncomplemented flip-flop state to the AND array.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.21 Design a serial subtractor circuit that will perform the operation A – B, where A = an-1 … a1a0 and B = bn-1 … b1b0, producing result R = rn-1 … r1r0 The two operands are applied to the serial subtractor inputs sequentially producing one result bit per clock period, beginning with bits a0 and b0 to produce r0. Determine how the circuit would be implemented in: (a) One or two of the FPGA configurable logic blocks shown in Figure 7.10. Sketch the circuit diagram, including all signals, and list the contents of the lookup table(s) in truth table format.

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Digital Logic Circuit Analysis and Design, 2nd Edition

(b) A PAL with one registered output and one combinational output. Derive and list the logic equations that would be implemented to provide the flip-flop input and the circuit output.

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.22 Design an HDL model of a 4-bit arithmetic and logic unit (ALU) that implements the four functions defined in the table below. The ALU has two 4-bit inputs, A and B, a 4-bit output R, and two function select inputs S1S0. Simulate the model to verify its correctness, synthesize and implement the model using your FPGA design tools, and test the model on an FPGA board by performing each of the four operations on several pairs of inputs.

S1 0 0 1 1

S2 0 1 0 1

Function R=A+B R=A–B R=A&B R=A|B

(logical AND) (logic OR)

-- VHDL Problem 7.22 4-bit ALU library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- contains arithmetic ops for unsigned #s entity Problem7_22_ALU is port (A, B: in std_logic_vector (3 downto 0); -- A and B data inputs R: out std_logic_vector (3 downto 0); -- ALU result S: in std_logic_vector (1 downto 0)); -- Function select end Problem7_22_ALU; architecture behavior of Problem7_22_ALU is begin R <= std_logic_vector (unsigned(A) + unsigned(B)) when S = "00" else std_logic_vector (unsigned(A) - unsigned(B)) when S = "01" else A and B when S = "10" else A or B when S = "11"; end; //Verilog Problem 7.22 4-bit ALU module Problem7_22_ALU (S, A, B, R); input [1:0] S; // function select input [3:0] A,B; // 4-bit inputs output reg [3:0] R; // 4-bit output always @(*) begin case (S) 2’b00: R = A + B; // A+B 2’b01: R = A - B; // A-B 2’b10: R = A & B; // A&B 2’b11: R = A | B; // A|B endcase end endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.23 Write an HDL model for an 8-bit “left/right shift register” with 8-bit output Q and six input signals: CLEAR, CLOCK, ENABLE, LEFT_RIGHTN, SERinL and SERinR. If CLEAR=1, the register should asynchronously reset to all 0’s. If CLEAR = 0 and ENABLE=1, the register should shift one bit position on the falling edge of CLOCK, shifting left if LEFT_RIGHTN = 1, with the right-most bit replaced by SERinR, and shifting right if LEFT_RIGHTN = 0, with the left-most bit replaced by SERinL. Simulate the HDL model to verify its correctness, synthesize and implement the model using your FPGA design tools, and test the model on an FPGA board by performing a series of shift operations.

-- VHDL Problem 7.23 8-bit shift register library ieee; use ieee.std_logic_1164.all; entity Problem7_23_ShiftReg is port ( Q: out std_logic_vector (7 downto 0); -- shift register output CLEAR: in std_logic; -- Asyncronous reset to 0 CLOCK: in std_logic; -- Clock (falling edge) ENABLE: in std_logic; -- Enable shifting LEFT_RIGHTN: in std_logic; -- Shift left (1) or right (0) SERinL: in std_logic; -- Replace left bit on shift right SERinR: in std_logic); -- Replace right bit on shift left end Problem7_23_ShiftReg; architecture behavior of Problem7_23_ShiftReg is signal Qint: std_logic_vector (7 downto 0); -- shift register state begin process (CLOCK, CLEAR) begin if CLEAR = ‘1’ then Qint <= “00000000”; -- async clear elsif (falling_edge(CLOCK)) and (ENABLE = ‘1’) then if LEFT_RIGHTN = ‘1’ then Qint <= Qint(6 downto 0) & SERinR; --shift left else Qint <= SERinL & Qint(7 downto 1); -- shift right end if; end if; end process; Q <= Qint; -- drive the output end; //Verilog Problem 7.23 8-bit shift register module Problem7_23_ShiftReg (Q, CLEAR, CLOCK, ENABLE, LEFT_RIGHTN, SERinL, SERinR); output reg [7:0] Q; // 8-bit output input CLEAR, CLOCK, ENABLE, LEFT_RIGHTN, SERinL, SERinR; // control inputs always @(posedge CLEAR or negedge CLOCK) begin if (CLEAR == 1’b1) Q <= 8’b00000000; // async clear else if ((CLOCK == 1’b0) && (ENABLE == 1’b1)) begin if (LEFT_RIGHTN == 1’b1) Q <= {Q[6:0], SERinR}; //left shift else Q <= {SERinL, Q[7:1]}; //left shift end end endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.24 Write an HDL model of a 10-bit “binary up/down counter” and implement it in an FPGA. The counter is to have 10-bit output Y, 10-bit input D, three control signals CLRN, LD_CNTN, UP_DN, and clock CLK. The counter is to have the following functions, with the clear function asynchronous and the other functions triggered on the falling edge of CLK. CLRN 0 1 1 1

LD_CNTN X 0 0 1

UP_DN X 0 1 X

Function Asynchronous clear Count down Count up Load D

-- VHDL Problem 7.24 10-bit binary up/down counter library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- contains arithmetic ops for unsigned #s entity Problem7_24_Counter is port (D: in std_logic_vector (9 downto 0); -- parallel inputs Y: out std_logic_vector (9 downto 0); -- counter outputs CLRN: in std_logic; -- Asynchronous clear LD_CNTN: in std_logic; -- Count (0) vs load (1) UP_DN: in std_logic; -- Up (1) vs down (0) CLK: in std_logic); -- clock signal end Problem7_24_Counter; architecture behavior of Problem7_24_Counter is signal Yint: unsigned(9 downto 0); -- internal counter state begin process (CLK, CLRN) begin if (CLRN = ‘0’) then Yint <= “0000000000”; -- async clear elsif falling_edge(CLK) then if LD_CNTN = ‘1’ then Yint <= unsigned(D); -- load input elsif UP_DN = ‘1’ then Yint <= Yint + 1; -- count up else Yint <= Yint – 1; -- count down end if; end if; end process; Y <= std_logic_vector(Yint); -- drive outputs end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Verilog Problem 7.24 10-bit binary up/down counter module Problem7_24_Counter (D, Y, CLRN, LD_CNTN, UP_DN, CLK); input [9:0] D; // 10-bt parallel input output reg [9:0] Y; // 10-bit output input CLRN, LD_CNTN, UP_DN, CLK; //control inputs always @(negedge CLK or negedge CLRN) begin if (CLRN == 1’b0) Y <= 10’b0000000000; // async clear else if (CLK == 1’b0) begin if (LD_CNTN == 1’b1) Y <= D; // load else if (UP_DN == 1’b1) Y <= Y + 1; // count up else Y <= Y – 1; // count down end; end; endmodule

7.25 Write a parameterized HDL model for an N-bit “down counter” with N-bit data input A, Nbit output Y, clock input CLK, and two control signals: CNT and LOAD. Operations should occur on the falling edge of CLK as follows.

• If LOAD = CNT = 0 the counter state should not change.

• If LOAD=1, data input A should be loaded into the counter.

• If LOAD=0 and CNT=1 the counter value should decrement by 1, resetting to its maximum value if it decrements when the count value is 0.

Using appropriate development tools, simulate, synthesize, implement and test the HDL model in a FPGA, using appropriate development tools. Look up and record the resources used to implement the design (number of lookup tables, flip-flops, and input/output pins.) //Verilog Problem 7.25 N-bit binary down counter module Problem7_25_Counter (A, Y, LOAD, CNT, CLK); parameter N = 4; // register width parameter with default value input [N-1:0] A; // N-bit parallel input output reg [N-1:0] Y; // N-bit output input LOAD, CNT, CLK; //control inputs always @(negedge CLK) begin if (LOAD == 1’b1) Y <= A; // load else if (CNT == 1’b1) Y <= Y – 1; // count down end endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- VHDL Problem 7.25 N-bit binary up/down counter library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- contains arithmetic ops for unsigned #s entity Problem7_25_Counter is generic (N: integer := 4); -- register width port ( A: in std_logic_vector (N-1 downto 0); -- parallel inputs Y: out std_logic_vector (N-1 downto 0); -- counter outputs CNT: in std_logic; -- count enable LOAD: in std_logic; -- load enable CLK: in std_logic); -- clock signal end Problem7_25_Counter; architecture behavior of Problem7_25_Counter is signal Yint: unsigned(N-1 downto 0); -- internal counter state begin process (CLK) begin if falling_edge(CLK) then if LOAD = ‘1’ then Yint <= unsigned(A); -- load input elsif CNT = ‘1’ then Yint <= Yint – 1; -- count down end if; end if; end process; Y <= std_logic_vector(Yint); -- drive outputs end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.26 The “accumulator” in Figure P7.26 comprises a 4-bit adder and 4-bit register that accumulates the sum of a series of numbers applied to 4-bit input N, with the result on 6bit output R (carries can be discarded in this exercise.) The register is rising-edge triggered by clock input CLK, with synchronous “clear” and “load” functions enabled by CLR and LD, respectively. The register input is provided by adder output A. The controller should clear the register when its Reset input is activated, and then add the number on input N to the contents of the register at each pulse on the Clock input. Write an HDL model of this system, simulate it, and implement it for a target FPGA with your design tools, and test it on an FPGA board.

Figure P7.26 //Verilog Problem 7.26: Accumulator module Problem7_26_Accumulator (CLK, Reset, N, R); input CLK, Reset; // control signals input [3:0] N; // 4-bit data in output reg [3:0] R; // 4-bit data out wire LD, CLR; // register control signals wire [3:0] A; // adder output reg [1:0] state; // controller state parameter Halt = 2’b00, Clear = 2’b01, Add = 2’b10; //state names initial state <= Halt; // Start in Halt state assign A <= R + N; //Adder always @(posedge CLK) begin // Register if (CLR == 1’b1) R <= 4’b0000; // reset if CLR=1 else if (LD == 1’b1) R <= A; // load if LD=1 end always @(posedge CLK) begin // controller state if (state == Halt) begin // if in Halt state if (Reset == 1’b1) state <= Clear; // reset from Halt to Clear end else state <= Add; // Otherwise from Clear/Add to Add state end assign CLR = (state == Clear) ? 1’b1 : 1’b0; // Clear register in Clear state assign LD = (state == Add) ? 1’b1 : 1’b0; // Load register in Load state endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- VHDL Problem 7.26: Accumulator library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Problem7_26_Accumulator is port ( CLK, Reset: in std_logic; -- controller inputs N: in std_logic_vector(3 downto 0); -- 4-bit N input R: out std_logic_vector(5 downto 0)); -- 6-bit R output end Problem7_26_Accumulator; architecture behavior of Problem7_26_Accumulator is type states is (Halt, Clear, Add); -- data type of state names signal state: states := Halt; signal A: unsigned(5 downto 0); -- 6-bit adder output signal Rint: unsigned(5 downto 0); -- 6-bit register signal CLR, LD: std_logic; -- controller outputs begin A <= Rint + unsigned(N); -- adder output Reg: process (CLK) begin if rising_edge(CLK) then if CLR = ‘1’ then Rint <= “000000”; -- reset the register else if LD = ‘1’ then Rint <= A; -- load adder output end if; end if; end process; R <= std_logic_vector(Rint);

-- drive the output

LD <= '1' when state = Add else '0'; CLR <= '1' when state = Clear else '0';

-- activate LD in Add state -- activate CLR in Clear state

process (CLK) begin -- state transitions on rising CLK edge if rising_edge(CLK) then case (state) is when Halt => if Reset = ‘1’ then state <= Clear; -- go to Clear if Reset active else state <= Halt; -- stay in Halt otherwise end if; when CLEAR => state <= Add; -- begin adding when ADD => state <= Add; -- continue adding end case; end if; end process; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.27 4-bit registers R1, R2, and R3 are connected as shown in Figure P7.27 and enabled by control signals E1, E2, and E3, respectively, provided by a controller. An algorithm that manipulates these registers is defined by the flow chart in the figure. Design an HDL model that implements this datapath and controller, simulate the model to verify its operation, implement the model for a target FPGA with your design tool(s), and test the design on an FPGA board by performing a series of register transfers for different values of 4-bit input N, as selected by controller input X.

Figure P7.27 //Verilog Problem 7.27: Controller module Problem7_27_Controller (CLK, X, E1, E2, E3, N, R3); input CLK, X; // controller inputs output E1, E2, E3; // controller outputs input [3:0] N; // datapath input output reg [3:0] R3; // datapath output reg [3:0] R1, R2; // internal datapath reg outputs reg [1:0] state; // controller state parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10; //state names initial state <= S0; // Start in state S0 always @(posedge CLK) begin // controller state if (state == S0) begin if (X == 1’b0) state <= S1; // S0 to S1 else state <= S2; // S0 to S2 end else state <= S0; // S1 or S2 to S0 end assign E1 = (state == S0) ? 1’b1 : 1’b0; // Enable R1 in S0 assign E2 = (state == S1) ? 1’b1 : 1’b0; // Enable R2 in S1 assign E3 = (state == S2) ? 1’b1 : 1’b0; // Enable R3 in S2 always @(posedge CLK) begin // Datapath registers if (E1 == 1’b1) R1 <= N; // R1 enabled if (E2 == 1’b1) R2 <= R1; // R2 enabled if (E3 == 1’b1) R3 <= R2; // R3 enabled end endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- VHDL Problem 7.27: Controller library ieee; use ieee.std_logic_1164.all; entity Problem7_27_Controller is port ( CLK, X: in std_logic; -- controller inputs E1, E2, E3: out std_logic; -- controller outputs N: in std_logic_vector(3 downto 0); -- datapath input R3: out std_logic_vector(3 downto 0)); -- datapath output end Problem7_27_Controller; architecture behavior of Problem7_27_Controller is type states is (S0, S1, S2); -- data type of state names signal state: states := S0; -- state of the controller signal R1, R2: std_logic_vector(3 downto 0); -- internal register states begin E1 <= ‘1’ when state = S0 else ‘0’; -- Moore model outputs E2 <= ‘1’ when state = S1 else ‘0’; E3 <= ‘1’ when state = S2 else ‘0’; process (CLK) begin -- controller if rising_edge(CLK) then case (state) is when S0 => if X = ‘0’ then state <= S1; -- go to S1 if X is 0 else state <= S2; -- go to S2 if X is 1 end if; when S1 => state <= S0; -- return to S0 from S1 when S2 => state <= S0; -- return to S0 from S2 end case; end if; end process; process (CLK) begin -- datapath if rising_edge(CLK) then if (E1 = ‘1’) then R1 <= N; end if; -- load R1 in state S0 if (E2 = ‘1’) then R2 <= R1; end if; -- load R2 in state S1 if (E3 = ‘1’) then R3 <= R2; end if; -- load R3 in state S2 end if; end process; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.28 The datapath and control algorithm shown in Figure P7.28 perform the binary division operation D1 ÷ D2, where D1 and D2 are 6-bit and 4-bit numbers, respectively. The algorithm defined in the ASM diagram in the figure performs the division operation by counting the number of times D2 can be subtracted from D1 (discarding the remainder).

Data and control signals are labeled on the datapath. EN1/EN2 are clock enables (enabling the registers to be loaded), CLR/INC enable clear and increment functions, and GTZ indicates R1 > 0 (GTZ is the sign bit of register R1). All signals are active high, and registers change on the rising edge of CLK. Write an HDL model of this circuit, including the controller, simulate the model to verify its operation, implement the model for a target FPGA with your design tool(s), and test the design on an FPGA board by performing a series of divide operations.

Figure P7.28 -- VHDL Problem 7.28: Divider library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Problem7_28_Divider is port ( CLK, RESET: in std_logic; -- controller inputs D1: in std_logic_vector(5 downto 0); -- 6-bit dividend D2: in std_logic_vector(3 downto 0); -- 4-bit divisor Quotient: out std_logic_vector(5 downto 0); -- quotient DONE: out std_logic); -- algorithm DONE indicator end Problem7_28_Divider; architecture behavior of Problem7_28_Divider is type states is (Init, Sub, Tmp, Count, Halt); -- data type of state names signal state: states := Init; -- state of the controller signal SEL, EN1, EN2, CLR, INC, GTZ: std_logic; -- between datapath and controller signal CNT: unsigned(5 downto 0); -- quotient counter signal Mux, R1, Subtract: unsigned(6 downto 0); -- 7 bits to include dividend sign signal R2: unsigned(3 downto 0); -- dividend register

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Digital Logic Circuit Analysis and Design, 2nd Edition

begin

end;

-- drive the output Quotient <= std_logic_vector(CNT); DONE <= ‘1’ when state = Halt else ‘0’; -- Moore model outputs SEL <= ‘1’ when state = Init else ‘0’; -- select Subtractor or D1 EN1 <= ‘1’ when state = Init or State = Sub else ‘0’; -- enable R1 load EN2 <= ‘1’ when state = Init else ‘0’; -- enable R2 load CLR <= ‘1’ when state = Init else ‘0’; -- reset counter INC <= ‘1’ when state = Count else ‘0’; -- increment counter process (CLK) begin -- state transitions on rising CLK edge if rising_edge(CLK) then case (state) is when Init => state <= Sub; -- initialize registers when Count => state <= Sub; -- increment counter when Sub => state <= Tmp; -- wait for R1 to load before testing when Tmp => if GTZ = ‘1’ then -- check previous result state <= Count; -- increment count if positive else state <= Halt; -- halt if negative end if; when Halt => if RESET = ‘1’ then state <= Init; -- wait for RESET signal end if; end case; end if; end process; Mux <= Subtract when SEL = ‘0’ else unsigned(‘0’ & D1); -- R1 input mux Subtract <= R1 – R2; -- subtractor output including borrow/sign bit GTZ <= not R1(6); -- GTZ = 1 if positive result (sign bit 0) process (CLK) begin if rising_edge(CLK) then if EN1 = ‘1’ then R1 <= Mux; end if; -- load R1 if EN2 = ‘1’ then R2 <= unsigned(D2); end if; -- load R2 if CLR = ‘1’ then CNT <= “000000”; -- reset count elsif INC = ‘1’ then CNT <= CNT + 1; -- increment count end if; end if; end process;

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Verilog Problem 7.28: Divider module Problem7_28_Divider (CLK, RESET,D1, D2, Quotient, DONE); input CLK, RESET; // controller inputs input [5:0] D1; // dividend input [3:0] D2; // divisor output [5:0] Quotient; // quotient output DONE; // division DONE indicator reg [6:0] R1; // dividend register (including borrow/sign) wire [6:0] Mux, Subtract; // mux and subtractor outputs reg [3:0] R2; // divisor register reg [5:0] CNT; // quotient counter wire GTZ, SEL, EN1, EN2, CLR, INC; reg [2:0] state; // controller state parameter Init = 3’b000, Sub = 3’b001, Tmp = 3’b010, Count = 3’b011, Halt = 3’b100; initial state <= Halt; // Start in Halt until reset always @(posedge CLK) begin // controller state case (state) Init: state <= Sub; // initialize registers Count: state <= Sub; // increment counter Sub: state <= Tmp; // load R1 from subtractor Tmp: if (GTZ == 1’b1) state <= Count; //count if R1>-=0 else state <= Halt; //halt if R1 < 0 Halt: if (RESET == 1’b1) state <= Init; //wait for reset endcase end assign DONE = (state == Halt) ? 1’b1 : 1’b0; // Signal DONE in halt state assign SEL = (state == Init) ? 1’b1 : 1’b0; // Select D1 or Subtract for R1 assign EN1 = ((state == Init) || (state == Sub)) ? 1’b1 : 1’b0; // Enable R1 assign EN2 = (state == Init) ? 1’b1 : 1’b0; // Enable R2 assign CLR = (state == Init) ? 1’b1 : 1’b0; // Clear counter assign INC = (state == Count) ? 1’b1 : 1’b0; // Increment counter assign Mux = (SEL == 1’b0) ? Subtract : {1’b0,D1}; // select R1 input assign Subtract = R1 – R2; assign Quotient = CNT; assign GTZ = ~R1[6]; always @(posedge CLK) begin // Datapath registers if (EN1 == 1’b1) R1 <= Mux; // Mux to R1 if (EN2 == 1’b1) R2 <= D2; // Divisor to R2 if (CLR == 1’b1) CNT <= 6’b000000; // Clear CNT if (INC == 1’b1) CNT <= CNT + 1; // Increment CNT end endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.29 Modify the multiplexed display controller described in the summative design example of Section 7.4.2 to control an 8-digit display. Simulate the HDL model to verify its operation, implement the model for a target FPGA with your design tool(s), and test the design on an FPGA board by performing a series of divide operations.

The VHDL models presented in Section 7.4.2 are extended by increasing the number of anode control signals from 4 to 8 and the size of the register file from 4 to 8 registers, which requires changing the register file read and write addresses from 2 to 3 bits. The number of states in the FSM must therefore be doubled to generate a 3-bit read address, instead of a 2-bit address, and 8 instead of 4 anode select bits. These changes are reflected in the top-level model, the register file model, the FSM model, and the component declarations package, as follows. The binary to seven-sgement decoder and counter models do not require changes.

-- Top-level Display Controller – Modified for 8-digit display library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.DisplayComps.all; --component declarations entity DisplayControl is port ( DigitVal: in std_logic_vector(3 downto 0); --reg data input DigitNum: in std_logic_vector(2 downto 0); --reg write address (3 bits instead of 2) WriteEnable: in std_logic; --reg write enable SEG: out std_logic_vector(6 downto 0); --Seg7 data AN: out std_logic_vector(7 downto 0); --Seg7 anodes (8 instead of 4) Reset: in std_logic; --system reset Clock: in std_logic ); --system clock end DisplayControl; architecture Behavioral of DisplayControl is signal Count: std_logic_vector(7 downto 0); --counter output signal RegOut: std_logic_vector(3 downto 0); --data from reg file signal FSM_Count: std_logic_vector(2 downto 0); --encoded FSM state, reg read address begin RF: regfile port map (DataIn => DigitVal, DataOut => RegOut, WriteAddress => DigitNum, ReadAddress => FSM_Count, WriteEnable => WriteEnable); FSM: Display_FSM port map (RST => Reset, CLK => Clock, AN => AN, RA => FSM_Count); DEC: bcd2seg7 port map( BCD => RegOut, SEG => SEG); CNT: Counter generic map (N => 8) port map (CLK => Clock, RST => Reset, Q => Count); end Behavioral; -- Display Controller Finite State Machine – Modified for 8-digit display library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Display_FSM is port ( RST : in STD_LOGIC; CLK : in STD_LOGIC; AN : out STD_LOGIC_VECTOR (7 downto 0); -- 8 instead of 4-bit AN RA : out STD_LOGIC_VECTOR (2 downto 0) ); -- 3 instead of 2-bit RA end Display_FSM;

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Digital Logic Circuit Analysis and Design, 2nd Edition

architecture Behavioral of Display_FSM is signal state: STD_LOGIC_VECTOR (2 downto 0) := "000"; --8 instead of 4 states begin process(CLK) -- define state transitions begin if rising_edge(CLK) then --all operations synchronous if (RST = '1') then --reset to S0 State <= "000"; else case State is --state changes when "000" => State <= "001"; when "001" => State <= "010"; when "010" => State <= "011"; when "011" => State <= "100"; when "100" => State <= "101"; when "101" => State <= "110"; when "110" => State <= "111"; when "111" => State <= "000"; when others => State <= "000"; end case; end if; end if; end process; RA <= state; --state number to register file with State select --active-low outputs (one-cold encoding) AN <= "11111110" when "000", -- Digit 0 -- 8 instead of 4 digits "11111101" when "001", -- Digit 1 "11111011" when "010", -- Digit 2 "11110111" when "011", -- Digit 3 "11101111" when "100", -- Digit 4 "11011111" when "101", -- Digit 5 "10111111" when "110", -- Digit 6 "01111111" when "111", -- Digit 7 "11111111" when others; end Behavioral; -- Display Controller Register File – Modified for 8-digit display library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RegFile is port ( DataIn: in std_logic_vector (3 downto 0); DataOut: out std_logic_vector (3 downto 0); WriteAddress: in std_logic_vector (2 downto 0); -- 3 instead of 2 address bits ReadAddress: in std_logic_vector (2 downto 0); WriteEnable: in std_logic ); end RegFile;

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Digital Logic Circuit Analysis and Design, 2nd Edition

architecture Behave of RegFile is type MEMY is array (0 to 7) of std_logic_vector(3 downto 0); -- 8 instead of 4 registers signal Rfile: MEMY; begin DataOut <= Rfile(TO_INTEGER(UNSIGNED(ReadAddress))); process (WriteEnable) --Flip-flop based begin if falling_edge(WriteEnable) then --Flip-flop based Rfile(TO_INTEGER(UNSIGNED(WriteAddress))) <= DataIn; end if; end process; end; -- Display Controller Component Declarations Package – Modified for 8-digit display library IEEE; use IEEE.STD_LOGIC_1164.ALL; package DisplayComps is component Counter generic (N: natural := 8); port(CLK: in std_logic; --FPGA clock RST: in std_logic; --Asynchronous reset Q: out std_logic_vector(N-1 downto 0)); --Output data end component; component RegFile port ( DataIn: in std_logic_vector (3 downto 0); DataOut: out std_logic_vector (3 downto 0); WriteAddress: in std_logic_vector (2 downto 0); -- 3 instead of 2 address bits ReadAddress: in std_logic_vector (2 downto 0); WriteEnable: in std_logic ); end component; component bcd2seg7 port ( BCD: in std_logic_vector(3 downto 0); SEG: out std_logic_vector(6 downto 0) ); --Segments GFEDCDA end component; component Display_FSM port ( RST : in STD_LOGIC; CLK : in STD_LOGIC; AN : out STD_LOGIC_VECTOR (7 downto 0); RA : out STD_LOGIC_VECTOR (2 downto 0) ); -- 3 instead of 2 address bits end component; end DisplayComps;

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Digital Logic Circuit Analysis and Design, 2nd Edition

7.30 Show how to modify the PROM-based high-speed multiplier of Example 7-17 to multiply a pair of 12-bit numbers. You may assume the availability of PROM devices with up to 25 inputs. 𝑃𝑃23−0 = 𝐴𝐴11−0 × 𝐵𝐵11−0 = ((𝐴𝐴11−6 × 26 ) + 𝐴𝐴5−0 ) × ((𝐵𝐵11−6 × 26 ) + 𝐵𝐵5−0 ) = (𝐴𝐴11−6 × 𝐵𝐵11−6 ) × 212 + �(𝐴𝐴11−6 × 𝐵𝐵5−0 ) + (𝐴𝐴5−0 × 𝐵𝐵11−6 )� × 26 + 𝐴𝐴5−0 × 𝐵𝐵5−0

This operation can be done with four 6-bit by 6-bit multipliers to compute partial products of sixbit halves of each operand and three binary adders to add the partial products. The multiplications by 26 and 212 can be done by simply shifting the corresponding terms to the left by 6 and 12 bits, respectively. Note that the multiplication table for a 6-bit by 6-bit multiplication has 212 rows, and 12 bits for the product. We can view the sum of the partial products as follows, where the notation Mnk refers to the kth bit of the nth partial product, and Pk refers to the kth bit of the final product. The three adder PROMs combine two 6-bit numbers, one 12-bit and one 13-bit number, and one 6-bit number and a 1-bit number, as indicated in the diagram.

M0BM0AM09M08M07M06M05M04M03M02M01M00 + M1BM1AM19M18M17M16M15M14M13M12M11M100 0 0 0 0 0 + M2BM2AM29M28M27M26M25M24M23M22M21M200 0 0 0 0 0 + M3BM3AM39M38M37M36M35M34M33M32M31M300 0 0 0 0 0 0 0 0 0 0 0 --------------------------------------------------------P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

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Digital Logic Circuit Analysis and Design, 2nd Edition

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Digital Logic Circuit Analysis and Design, 2nd Edition

Chapter 8 – Design of Digital Systems 8.1.

Develop a hierarchy diagram for the TRISC4 processor described in Section 8.2.1 of this book. The lowest level should consist of the basic functional blocks such as registers, multiplexers, ALUs, and RAMs.

8.2.

Develop a hierarchy diagram for the One-Lane Traffic Controller described in Section 8.2.2 of this book. The lowest level should consist of the basic building blocks such as gates, flip-flops, counters, etc.

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.3.

Develop a hierarchy diagram for the UART described in Section 8.2.3 of this book. The lowest level should consist of the basic Verilog modules and blocks.

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.4.

The TRISC4 processor design utilizes parallel-in/parallel-out registers and counters for several functions such as the program counter (PC) and general purpose ALU registers.

Design a component using Verilog or VHDL that can be used to realize these devices. //Problem 8.4 Verilog: Four-bit register with load, increment and clear module reg4 (Rin,Rout,Ld,Clr,Inc); input [3:0] Rin; // data in input Ld,Clr,Inc; // active-low control pulses output reg [3:0] Rout; // data out always @ (negedge Clr) Rout <= 4'b0; // clear register always @ (negedge Ld) Rout <= Rin; // load register always @ (negedge Inc) Rout <= Rout + 1'b1; // increment register endmodule --Problem 8.4 VHDL: Four-bit register with load, increment and clear library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity reg4 is port( Rin: in std_logic_vector(3 downto 0); --Data in Rout: out std_logic_vector(3 downto 0); --Data out Ld, Clr, Inc: in std_logic); --active-low control pulses end reg4; architecture rtl of reg4 is signal Q: std_logic_vector(3 downto 0); begin process(Clr,Inc,Ld) begin if falling_edge(Clr) then Q <= "0000"; -- clear elsif falling_edge(Inc) then Q <= std_logic_vector(unsigned(Q) + 1); -- increment elsif falling_edge(Ld) then Q <= Rin; --load end if; end process; Rout <= Q; -- drive the outputs end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.5.

Design the TRISC4 general-purpose register unit, Figure 8.8, using Verilog or VHDL. //Problem 8.5 Verilog TRISC4 General Purpose Registers Fig. 8.8 module RegUnit (ALUR,MDO,ALUA,ALUB,MDI,IS,OS,LA,IA,CA,LB,IB,CB); input [3:0] ALUR,MDO; input IS,OS,LA,IA,CA,LB,IB,CB; output [3:0] ALUA,ALUB,MDI; wire [3:0] MUXout; //Instantiated mux2 (Problem 8.7) and reg4 (Problem 8.4) mux2 InMUX (ALUR,MDO,MUXout,IS); reg4 A (MUXout,ALUA,LA,CA,IA); reg4 B (MDO,ALUB,LB,CB,IB); mux2 OutMUX (ALUA,ALUB,MDI,OS); endmodule --Problem 8.5 VHDL TRISC4 General Purpose Registers Fig. 8.8 library ieee; use ieee.std_logic_1164.all; entity RegUnit is port ( ALUR,MDO: in std_logic_vector(3 downto 0); ALUA,ALUB,MDI: out std_logic_vector(3 downto 0); InS,OutS,LA,IA,CA,LB,IB,CB: in std_logic); end RegUnit; architecture rtl of RegUnit is component reg4 port( Rin: in std_logic_vector(3 downto 0); --register inputs Rout: out std_logic_vector(3 downto 0); --register outputs Clr, Inc, Ld: in std_logic); --control pulses end component; component mux2 port (In0,In1: in std_logic_vector(3 downto 0); Mout: out std_logic_vector(3 downto 0); Sel: in std_logic); end component; signal MUXout: std_logic_vector(3 downto 0); begin --Instantiated mux2 (Problem 8.7) and reg4 (Problem 8.4) RA: reg4 port map(MUXout, ALUA, CA, IA, LA); -- register A RB: reg4 port map(MDO, ALUB, CB, IB, LB); -- register B MI: mux2 port map(ALUR, MDO, Muxout, InS); -- input mux MO: mux2 port map(ALUA, ALUB, MDI, OutS); -- output mux end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.6.

Design the TRISC4 ALU, Figure 8.9, using Verilog or VHDL. //Problem 8.6. Four-bit, four-function ALU. ADD, SUB, AND, XOR. module alu4 (A,B,R,s1,s0,Z,N,V,C); input [3:0] A,B; input s1,s0; output reg [4:0] R; output Z,N,V,C; parameter ADD = 2'b00,SUB = 2'b01,AND = 2'b10,XOR = 2'b11; always @ (A,B,s1,s0) case ({s1,s0}) ADD: R = A + B; SUB: R = A + (-B); AND: R = A & B; XOR: R = A ^ B; endcase assign Z = (R[3:0]==4'b0); assign N = R[3]; assign V = (~s1&~s0)&(A[3]&B[3]&~R[3]|~A[3]&~B[3]&R[3])| (~s1&s0)&(A[3]&~B[3]&~R[3]|~A[3]&B[3]&R[3]); assign C = R[4]; endmodule --Problem 8.6 VHDL Four-bit, four-function ALU. ADD, SUB, AND, XOR. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu4 is port ( A,B: in std_logic_vector(3 downto 0); R: out std_logic_vector(3 downto 0); s1,s0: in std_logic; Z,N,V,C: out std_logic); end alu4; architecture rtl of alu4 is signal Rint: std_logic_vector(4 downto 0); signal S: std_logic_vector(1 downto 0); begin S <= s1 & s0; Rint <= std_logic_vector(signed(A(3) & A) + signed(B)) when (S = "00") else std_logic_vector(signed(A(3) & A) - signed(B)) when (S = "01") else '0' & (A and B) when (S = "10") else '0' & (A xor B) when (S = "11"); R <= Rint(3 downto 0); Z <= '1' when R <= "0000" else '0'; N <= R(3);

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Digital Logic Circuit Analysis and Design, 2nd Edition

end;

8.7.

C <= Rint(4); V <= '0' when s1 = '1' else (R(3) and not A(3) and not B(3)) or (not R(3) and A(3) and B(3)) when s0 = '0' else (R(3) and not A(3) and B(3)) or (not R(3) and A(3) and not B(3));

Design a quad two-to-one multiplexer for use in realizing TRISC4. Use Verilog or VHDL. //Problem 8.7. Two-to-one four-bit multiplexer. module mux2(In0,In1,Out,Sel); input [3:0] In0,In1; // 4-bit inputs input Sel; //Mux select output reg [3:0] Out; // 4-bit output always @ (In0,In1,Sel) if (Sel==0) Out = In0; else Out = In1; endmodule --Problem 8.7 VHDL Two-to-one four-bit multiplexer. library ieee; use ieee.std_logic_1164.all; entity mux2 is port (In0,In1: in std_logic_vector(3 downto 0); Mout: out std_logic_vector(3 downto 0); Sel: in std_logic); end mux2; architecture rtl of mux2 is begin Mout <= In0 when Sel = '0' else In1; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.8.

Design a fixed-logic realization of an instruction decoder for the TRISC4 instruction set, Table 8.1.

8.9.

Design a Verilog or VHDL realization of an instruction decoder for the TRISC4 instruction set, Table 8.1.

//Problem 8.9. TRISC4 Instruction Decoder. Active-high outputs. module InsDecoder ( input [3:0] IR, output reg LDA,LDB,STA,STB,ADD,SUB,AND,XOR,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV); always @ (IR[3:0]) case ({IR[3],IR[2],IR[1],IR[0]}) 4'b0000:begin LDA=1'b1;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0; INB=1'b0; CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0001:begin LDA=1'b0;LDB=1'b1;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0010:begin LDA=1'b0;LDB=1'b0;STA=1'b1;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0011:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b1;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0100:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b1;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0101:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b1;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0110:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b1;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b0111:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b1; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b1000:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b1;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b1001:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0;

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Digital Logic Circuit Analysis and Design, 2nd Edition

INA=1'b0;INB=1'b1;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b1010:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b1;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b1011:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b1;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b1100:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b1;BRZ=1'b0;BRN=1'b0;BRV=1'b0;end 4'b1101:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b1;BRN=1'b0;BRV=1'b0;end 4'b1110:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b1;BRV=1'b0;end 4'b1111:begin LDA=1'b0;LDB=1'b0;STA=1'b0;STB=1'b0;ADD=1'b0;SUB=1'b0;AND=1'b0;XOR=1'b0; INA=1'b0;INB=1'b0;CLA=1'b0;CLB=1'b0;JMP=1'b0;BRZ=1'b0;BRN=1'b0;BRV=1'b1;end endcase endmodule --Problem 8.9 VHDL. TRISC4 Instruction Decoder. Active-high outputs. library ieee; use ieee.std_logic_1164.all; entity InsDecoder is port (IR : in std_logic_vector(3 downto 0); LDA,LDB,STA,STB,ADD,SUB,AN,XR,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV: out std_logic); end InsDecoder; architecture rtl of InsDecoder is signal Y: std_logic_vector(15 downto 0); begin with IR select Y <= “0000000000000001” when “0000”, “0000000000000010” when “0001”, “0000000000000100” when “0010”, “0000000000001000” when “0011”, “0000000000010000” when “0100”, “0000000000100000” when “0101”, “0000000001000000” when “0110”, “0000000010000000” when “0111”, “0000000100000000” when “1000”, “0000001000000000” when “1001”, “0000010000000000” when “1010”, “0000100000000000” when “1011”, “0001000000000000” when “1100”, “0010000000000000” when “1101”, “0100000000000000” when “1110”, “1000000000000000” when “1111”, “0000000000000000” when others; LDA <= Y(0); LDB <= Y(1); STA <= Y(2); STB <= Y(3); ADD <= Y(4); SUB <= Y(5); AN <= Y(6); XR <= Y(7); INA <= Y(8); INB <= Y(9); CLA <= Y(10); CLB <= Y(11); JMP <= Y(12); BRZ <= Y(13); BRN <= Y(14); BRV <= Y(15); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.10. Design a control unit for TRISC4 that realizes all instructions in the TRISC4 instruction set, Table 8.1. //Problem 8.10 Verilog TRISC4 Controller for LDA, STA, ADD, CLA, INA, and JMP. module Controller ( input SysClock,Reset, //external inputs LDA,LDB,STA,STB,ADD,SUB,AND,XOR,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV, //Decoded instructions output reg CPC,AddSel,IPC,LIR,CA,CB,IA,IB,LPC,IS,OS,LA,LB,WE,S1,S0,LBR,LCCR, output RW); //Outputs. reg [4:0] State,NextState; //State and next state variables. reg CC; // select condition code for JMP/BRZ/BRN/BRV wire IR1 = STA | STB | AND | XOR | CLA | CLB | BRN | BRV; //OR to get bit 0 of IR to select operation/reg wire IR0 = LDB | STB | SUB | XOR | INB | CLB | BRZ | BRV; //OR to get bit 1 of IR reg RY; // combine with clock for RW pulses //Make state assignments. parameter A=5'b00000,B=5'b00001,C=5'b00010,D=5'b00011,E=5'b00100,F=5'b00101,G=5'b00110,H=5'b00111; parameter I=5'b01000,I1=5'b01001,I2=5'b01010,I3=5'b01011,J=5'b01100; parameter J1=5'b01101,J2=5'b01110,J3=5'b01111,K=5'b10000,K1=5'b10001,K2=5'b10010,K3=5'b10011; //Trigger state change on SysClock or Reset. always @ (negedge SysClock, negedge Reset) begin if (Reset==0) State <= A; else State <= NextState; end //Transition to state A on Reset, o/w NextState //Select condition to be tested by jump/branch always @ * case ({IR1,IR0}) 2'b00 : CC = 1'b1; //Branch unconditionally for JMP 2'b01 : CC = BRZ; //Branch if Z=1 (zero) 2'b10 : CC = BRN; //Branch if N=1 (negative) 2'b11 : CC = BRV; //Branch if V=1 (overflow) endcase assign RW = RY & SysClock; //RW needs to be pulses in consecutive states //Derive NextState which depends on present State and input. always @ * case (State) //Initialize PC. A: begin CPC=1'b1;AddSel=1'b0;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState = B; end //Begin instruction fetch from RAM by loading address into MAR from PC. B: begin CPC=1'b0;AddSel=1'b0;RY=1'b1;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState = C; end // RAM[MAR] is placed in MDR. C: begin CPC=1'b0;AddSel=1'b0;RY=1'b1;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState = D; end // IR is loaded with opcode from MDR. D: begin CPC=1'b0;AddSel=1'b0;RY=1'b0;IPC=1'b0;LIR=1'b1;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState = E; end //PC is incremented and decoded IR is tested for next state.

E: begin CPC=1'b0;AddSel=1'b0;RY=1'b0;IPC=1'b1;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0;

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Digital Logic Circuit Analysis and Design, 2nd Edition

//Derive NextState depending upon instruction to be executed. if (CLA | CLB) NextState = F; else if (INA | INB) NextState = G; //register ops else if (JMP | BRZ | BRN | BRV) NextState = H; //jump or branch else if (LDA| LDB) NextState = I; else if (STA | STB) NextState = J; //load or store register else if (ADD | SUB | AND | XOR) NextState = K; //ALU ops else NextState = A; end //reset if not valid instruction // Clear reg selected by CLA or CLB F: begin CPC=1'b0;AddSel=1'b0;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=CLA;CB=CLB;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=B; end // Increment reg selected by INA or INB G: begin CPC=1'b0;AddSel=1'b0;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=INA;IB=INB;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=B; end //JMP, BRZ, BRN, BRV testing selected condition code bit CC H: begin CPC=1'b0;AddSel=1'b0;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=CC; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=B; end // load register from memory with address from instruction and reg selected by LDA or LDB I: begin CPC=1'b0;AddSel=1'b1;RY=1'b1;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b1;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=I1; end I1: begin CPC=1'b0;AddSel=1'b1;RY=1'b1;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b1;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=I2; end I2: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b1;OS=1'b0;LA=LDA;LB=LDB;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=I3; end I3: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b1;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b1; NextState=B; end // store register in memory, address from instruction, reg selected by OS (1 for STB, 0 for STA) J: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=STB;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=J1; end J1: begin CPC=1'b0;AddSel=1'b1;RY=1'b1;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=STB;LA=1'b0;LB=1'b0;WE=1'b1;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=J2; end J2: begin CPC=1'b0;AddSel=1'b1;RY=1'b1;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=STB;LA=1'b0;LB=1'b0;WE=1'b1;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=J3; end J3: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b1; NextState=B; end // ALU operation selected by opcode bits IR1 and IR0 K: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=IR1;S0=IR0;LBR=1'b0;LCCR=1'b0; NextState=K1; end K1: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=IR1;S0=IR0;LBR=1'b1;LCCR=1'b0; NextState=K2; end K2: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b1;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b0; NextState=K3; end K3: begin CPC=1'b0;AddSel=1'b1;RY=1'b0;IPC=1'b0;LIR=1'b0;CA=1'b0;CB=1'b0;IA=1'b0;IB=1'b0;LPC=1'b0; IS=1'b0;OS=1'b0;LA=1'b0;LB=1'b0;WE=1'b0;S1=1'b0;S0=1'b0;LBR=1'b0;LCCR=1'b1; NextState=B; end endcase endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- Problem 8.10 VHDL: TRISC4 Controller library ieee; use ieee.std_logic_1164.all; entity Controller is port ( SysClock,Reset: in std_logic; LDA,LDB,STA,STB,ADD,SUB,AND1,XOR1,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV : in std_logic; -- Instruc inputs CPC,AddSel,IPC,LIR,CA,CB,IA,IB,LPC,ISn,OSn,LA,LB,WE,S1,S0,LBR,LCCR,RW : out std_logic ); -- Control outputs end Controller; architecture rtl of Controller is type states is (A,B,C,D,E,F,G,H,I,I1,I2,I3,J,J1,J2,J3,K,K1,K2,K3); -- controller state names signal State : states := A; --state variable signal NextState : states := A; --next state variable signal CC: std_logic; -- select condition code for branch test signal IR: std_logic_vector(1 downto 0); -- bits 1 and 0 of opcode begin IR(1) <= STA or STB or AND1 or XOR1 or CLA or CLB or BRN or BRV; -- Bit IR(1) IR(0) <= LDB or STB or SUB or XOR1 or INB or CLB or BRZ or BRV; -- Bit IR(0) with IR select CC <= BRZ when "01", --Branch if Z=1 (zero) BRN when "10", --Branch if N=1 (negative) BRV when "11", --Branch if V=1 (overflow) '1' when others; --JMP unconditional -- Moore model outputs CPC <= '1' when state = A else '0'; --clear PC in state A LPC <= '1' when ((state = H) and (CC = '1')) else '0'; --load PC for branch or jump in state H IPC <= '1' when state = E else '0'; --increment PC in state E of fetch LIR <= '1' when state = D else '0'; --load IR in state D of fetch CA <= '1' when ((state = F) and (CLA = '1')) else '0'; --clear A or B in state F CB <= '1' when ((state = F) and (CLB = '1')) else '0'; IA <= '1' when ((state = G) and (INA = '1')) else '0'; --increment A or B in state G IB <= '1' when ((state = G) and (INB = '1')) else '0'; LA <= '1' when (((state = I2) and (LDA = '1')) or (state = K2)) else '0'; --load A or B in state I2, A in K2 LB <= '1' when ((state = I2) and (LDB = '1')) else '0'; ISn <= '1' when ((state = I) or (state = I1) or (state = I2) or (state = I3)) else '0'; OSn <= '1' when ((STB = '1') and ((state = J) or (state = J1) or (state = J2))) else '0'; AddSel <= '1' when ((state = I) or (state = I1) or (state = J1) or (state = J2)) else '0'; RW <= SysClock when ((state = B) or (state = C) or (state = I) or (state = I1) or (state = J1) or (state = J2)) else '0'; WE <= '1' when ((state = J1) or (state = J2)) else '0'; S1 <= IR(1) when ((state = K) or (state = K1)) else '0'; --ALU function from IR S0 <= IR(0) when ((state = K) or (state = K1)) else '0'; LBR <= '1' when (state = K1) else '0'; -- load ALU result to buffer reg LCCR <= '1' when ((state = I3) or (state = J3) or (state = K3)) else '0'; -- load CCR after ALU-LD-ST process (SysClock, Reset) begin --State change on SysClock or Reset if Reset = '0' then state <= A; elsif falling_edge(SysClock) then State <= NextState;

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Digital Logic Circuit Analysis and Design, 2nd Edition

end if; end process; --Derive NextState which depends on present State and input.

NextState <= B when ((state = A) or (state = F) or (state = G) or (state = H) or (state = I3) or (state = J3) or (state = K3)) else C when (state = B) else D when (state = C) else E when (state = D) else F when ((state = E) and ((CLA = '1') or (CLB = '1'))) else G when ((state = E) and ((INA = '1') or (INB = '1'))) else H when ((state = E) and ((JMP = '1') or (BRZ = '1') or (BRN = '1') or (BRV = '1'))) else I when ((state = E) and ((LDA = '1') or (LDB = '1'))) else I1 when (state = I) else I2 when (state = I1) else I3 when (state = I2) else J when ((state = E) and ((STA = '1') or (STB = '1'))) else J1 when (state = J) else J2 when (state = J1) else J3 when (state = J2) else K when ((state = E) and ((ADD = '1') or (SUB = '1')or (AND1 = '1')or (XOR1 = '1'))) else K1 when (state = K) else K2 when (state = K1) else K3 when (state = K2) else A; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.11. Realize the TRISC4 processor by integrating the various components designed above and/or in Section 8.2.1. // Problem 8.11 Verilog TRISC4 16 x 8 RAM module RAM ( input [3:0] in0, in1, //addresses from PC and instruction input [7:0] DataIn, //data in from selected register output [7:0] DataOut, //data out to PC or selected register input Sel, RW, WE); //control inputs wire [3:0] AddrMux; //select in0 or in1 reg [3:0] MAR; // memory address reg reg [7:0] MBR; // memory buffer reg reg [7:0] RAMarray [15:0]; // 16 x 8 memory array initial begin //load test program at startup RAMarray[4'h0] = 8'h0E; //LDA from M[4’hE] RAMarray[4'h1] = 8'h1F; //LDB from M[4’hF] RAMarray[4'h2] = 8'h2F; //STA to M[4’hF] RAMarray[4'h3] = 8'h3E; //STB to M[4’hE] RAMarray[4'h4] = 8'h40; //ADD RAMarray[4'h5] = 8'h50; //SUB RAMarray[4'h6] = 8'h60; //AND RAMarray[4'h7] = 8'h70; //XOR RAMarray[4'h8] = 8'h8C; //INA RAMarray[4'h9] = 8'h9C; //INB RAMarray[4'hA] = 8'hAC; //CLA RAMarray[4'hB] = 8'hBC; //CLB RAMarray[4'hC] = 8'hCE; //JMP to M[4’hE] RAMarray[4'hD] = 8'hDF; //BRZ to M[4’hF] RAMarray[4'hE] = 8'hE5; //BRN to M[4’h5] RAMarray[4'hF] = 8'hFD; //BRV to M[4’hD] endmodule // Problem 8.11 Verilog: Top-level TRISC4 model module TRISC4 (input SysClock, SysReset); wire [7:0] MDI; //Memory data input wire [7:0] MDO; //Memory data output wire [3:0] PC; //PC output to memory wire [3:0] IR; //IR output to control unit wire [4:0] R; //ALU output to buffer register wire [3:0] ALUR; //ALU buffer register output to register unit wire [3:0] CCR; //CCR output to control unit wire [3:0] ALUA, ALUB; //Register A and B outputs to memory and ALU wire CA,CB,CBR,CCCR,CIR,CPC,IA,IB,IPC,IS,OS,LA,LB,LBR,LCCR,LIR,LPC,RW,S1,S0,WE; //controller outputs wire LDA,LDB,STA,STB,ADD,SUB,AND,XOR,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV; //instruction decoder outputs // instantiate modules

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Digital Logic Circuit Analysis and Design, 2nd Edition

RAM Memory alu4 ALU RegUnit Registers

(.in0(PC), .in1(MDO[3:0]), .DataIn(MDI), .DataOut(MDO), .Sel(AddSel), .RW(RW), .WE(WE)); (.A(ALUA),.B(ALUB), .R(R), .s1(S1), .s0(S0), .Z(Z), .N(N), .V(V), .C(C)); (.ALUR(ALUR),.MDO(MDO[3:0]),.ALUA(ALUA),.ALUB(ALUB),.MDI(MDI[3:0]),.IS(IS),.OS(OS), .LA(LA),.IA(IA),.CA(CA),.LB(LB),.IB(IB),.CB(CB) ); reg4 BufferRegister (.Rin(R[3:0]),.Rout(ALUR), .Ld(LBR), .Clr(CBR), .Inc(1'b0)); reg4 ProgramCounter (.Rin(MDO[3:0]), .Rout(PC), .Ld(LPC), .Clr(CPC), .Inc(IPC)); reg4 ConditionCodes (.Rin({V,C,N,Z}), .Rout(CCR), .Ld(LCCR), .Clr(CCCR), .Inc(1'b0)); reg4 InstructionRegister (.Rin(MDO[7:4]), .Rout(IR), .Ld(LIR), .Clr(CIR), .Inc(1'b0)); InsDecoder InstructionDecode (.IR(IR),.LDA(LDA),.LDB(LDB),.STA(STA),.STB(STB),.ADD(ADD),.SUB(SUB), .AND(AND),.XOR(XOR),.INA(INA),.INB(INB),.CLA(CLA),.CLB(CLB), .JMP(JMP),.BRZ(BRZ),.BRN(BRN),.BRV(BRV)); Controller ControlUnit (.SysClock(SysClock),.Reset(SysReset), .LDA(LDA),.LDB(LDB),.STA(STA),.STB(STB),.ADD(ADD),.SUB(SUB),.AND(AND),.XOR(XOR), .INA(INA),.INB(INB),.CLA(CLA),.CLB(CLB),.JMP(JMP),.BRZ(BRZ),.BRN(BRN),.BRV(BRV), .CPC(CPC),.AddSel(AddSel),.RW(RW),.IPC(IPC),.LIR(LIR),.CA(CA),.CB(CB),.IA(IA),.IB(IB), .LPC(LPC),.IS(IS),.OS(OS),.LA(LA),.LB(LB),.WE(WE),.S1(S1),.S0(S0),.LBR(LBR),.LCCR(LCCR)); endmodule

-- Problem 8.11 VHDL TRISC4 16 x 8 RAM library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RAM is port (in0, in1: in std_logic_vector(3 downto 0); DataIn: in std_logic_vector(7 downto 0); DataOut: out std_logic_vector(7 downto 0); Sel, RW, WE: in std_logic); end RAM; architecture rtl of RAM is type MemType is array(0 to 15) of std_logic_vector(7 downto 0); signal RAMarray: MemType := --LDA LDB STA STB ADD SUB AND XOR (x"0E", x"1F", x"2F", x"3E", x"40", x"50", x"60", x"70", --INA INB CLA CLB JMP BRZ BRN BRV x"8C", x"9C", x"AC", x"BC", x"CE", x"DF", x"E5", x"FD"); signal AddrMux: std_logic_vector(3 downto 0); signal MAR: std_logic_vector(3 downto 0); signal MBR: std_logic_vector(7 downto 0); signal Addr: integer; begin AddrMux <= in0 when (Sel = '0') else in1; --Select PC or MDO address process (RW) begin if rising_edge(RW) then MAR <= AddrMux; --Load MAR on RW=1 end if; end process; Addr <= to_integer(unsigned(MAR)); --Memory index must be integer process (RW) begin if rising_edge(RW) then -- operate RW pulse

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Digital Logic Circuit Analysis and Design, 2nd Edition

end;

if WE = '1' then RAMarray(Addr) <= DataIn; -- write to RAM else MBR <= RAMarray(Addr); -- read from RAM end if; end if; end process; DataOut <= MBR; --MBR drives data out

-- Problem 8.11 VHDL - Component declaration package for TRISC4 library ieee; use ieee.std_logic_1164.all; package TRISC_Components is component reg4 is port (Rin: in std_logic_vector(3 downto 0); --Register inputs Rout: out std_logic_vector(3 downto 0); --Register outputs Clr, Inc, Ld: in std_logic); --Control pulses end component; component RegUnit is port (ALUR,MDO: in std_logic_vector(3 downto 0); -- in from ALU or memory ALUA,ALUB,MDI: out std_logic_vector(3 downto 0); -- A, B, or selected output InS,OutS,LA,IA,CA,LB,IB,CB: in std_logic); -- select and reg controls end component; component alu4 is port ( A,B: in std_logic_vector(3 downto 0); -- operands R: out std_logic_vector(3 downto 0); -- result s1,s0: in std_logic; -- function select Z,N,V,C: out std_logic); -- condition flags end component; component mux2 is port ( In0,In1: in std_logic_vector(3 downto 0); -- data in Mout: out std_logic_vector(3 downto 0); -- selected ouput Sel: in std_logic); -- select signal end component; component InsDecoder is port ( IR : in std_logic_vector(3 downto 0); -- instruction code in and decoder outputs LDA,LDB,STA,STB,ADD,SUB,AN,XR,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV: out std_logic); end component; component Controller is port ( SysClock,Reset: in std_logic; LDA,LDB,STA,STB,ADD,SUB,AND1,XOR1,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV : in std_logic; -- Instr inputs CPC,AddSel,IPC,LIR,CA,CB,IA,IB,LPC,ISn,OSn,LA,LB,WE,S1,S0,LBR,LCCR,RW : out std_logic ); -- Ctrls out end component; component RAM is port ( in0, in1: in std_logic_vector(3 downto 0); -- two address sources DataIn: in std_logic_vector(7 downto 0); -- 8-bit write data DataOut: out std_logic_vector(7 downto 0); -- 8-bit read data Sel, RW, WE: in std_logic); -- address select, RW pulse, write enable end component; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- Problem 8.11 VHDL: Top-level TRISC4 model library ieee; use ieee.std_logic_1164.all; use work.TRISC_Components.all; entity TRISC4 is port (SysClock, SysReset: in std_logic); -- only clock and reset inputs end TRISC4; architecture rtl of TRISC4 is signal MDI: std_logic_vector(7 downto 0); -- memory data input signal MDO: std_logic_vector(7 downto 0); -- memory data output signal PC: std_logic_vector(3 downto 0); -- PC output signal IR: std_logic_vector(3 downto 0); -- IR output signal R: std_logic_vector(3 downto 0); -- ALU output signal ALUR: std_logic_vector(3 downto 0); -- ALU buffer reg output signal CondCodes, CCR: std_logic_vector(3 downto 0); -- CCR inputs and output signal ALUA,ALUB: std_logic_vector(3 downto 0); -- Registers A and B outputs signal CA,CB,CBR,CCCR,CIR,CPC,IA,IB,IPC,ISn,OS,LA,LB,LBR,LCCR,LIR,LPC,RW,S1,S0,WE, AddSel: std_logic; signal LDA,LDB,STA,STB,ADD,SUB,AND1,XOR1,INA,INB,CLA,CLB,JMP,BRZ,BRN,BRV: std_logic; signal Z,N,C,V: std_logic; --Condition codes begin Memory: RAM port map (in0=>PC, in1=>MDO(3 downto 0), DataIn=>MDI, DataOut=>MDO, Sel=>AddSel, RW=>RW, WE=>WE); ArithLogic: alu4 port map (A=>ALUA, B=>ALUB, R=>R, s1=>S1, s0=>S0, Z=>Z, N=>N, V=>V, C=>C); CondCodes <= Z & N & C & V; Registers: RegUnit port map (ALUR=>ALUR,MDO=>MDO(3 downto 0),ALUA=>ALUA,ALUB=>ALUB, MDI=>MDI(3 downto 0),InS=>ISn,OutS=>OS, LA=>LA,IA=>IA,CA=>CA,LB=>LB,IB=>IB,CB=>CB); BufferRegister: reg4 port map (Rin=>R, Rout=>ALUR, Ld=>LBR, Clr=>CBR, Inc=>'0'); ProgramCounter: reg4 port map (Rin=>MDO(3 downto 0), Rout=>PC, Ld=>LPC, Clr=>CPC, Inc=>IPC); ConditionCodes: reg4 port map (Rin=>CondCodes, Rout=>CCR, Ld=>LCCR, Clr=>CCCR, Inc=>'0'); InstructionRegister: reg4 port map (Rin=>MDO(7 downto 4), Rout=>IR, Ld=>LIR, Clr=>CIR, Inc=>'0'); Decoder: InsDecoder port map (IR=>IR,LDA=>LDA,LDB=>LDB,STA=>STA,STB=>STB,ADD=>ADD,SUB=>SUB, AN=>AND1,XR=>XOR1,INA=>INA,INB=>INB,CLA=>CLA,CLB=>CLB, JMP=>JMP,BRZ=>BRZ,BRN=>BRN,BRV=>BRV); ControlUnit: Controller port map (SysClock=>SysClock,Reset=>SysReset, LDA=>LDA,LDB=>LDB,STA=>STA,STB=>STB,ADD=>ADD,SUB=>SUB, AND1=>AND1,XOR1=>XOR1, INA=>INA,INB=>INB,CLA=>CLA,CLB=>CLB, JMP=>JMP,BRZ=>BRZ, BRN=>BRN,BRV=>BRV, CPC=>CPC,AddSel=>AddSel,RW=>RW,IPC=>IPC,LIR=>LIR, CA=>CA,CB=>CB, IA=>IA,IB=>IB, LPC=>LPC,ISn=>ISn,OSn=>OS,LA=>LA,LB=>LB,WE=>WE,S1=>S1,S0=>S0,LBR=>LBR,LCCR=>LCCR); end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.12. Design a Verilog or VHDL realization of the Cars-On-Road detector used in the One-Lane Traffic Controller of Section 8.2.2. // Verilog Problem 8.12: Cars on Road Detector module CarsOnRoad(Clear, CountUp, CountDown, RoadClear); input Clear, CountUp, CountDown; // reset and clock pulses output RoadClear; // 1 if no cars on road reg UpDn; // latch direction from clock pulses wire Clk = CountUp | CountDown; // combine clock pulses reg [3:0] Q; //4-bit count always @(posedge CountUp or posedge CountDown) begin //up or down pulse? if (CountUp) UpDn = 1'b1; //latch up condition else UpDn = 1'b0; //latch down condition end always @(posedge Clear or negedge Clk ) begin if (Clear) Q = 4'h0; //clear counter else if (UpDn == 1'b1) Q = Q + 1; //increment else if (UpDn == 1'b0) Q = Q - 1; //decrement end assign RoadClear = (Q == 4'b0000) ? 1'b1 : 1'b0; // Road clear if count = 0 endmodule // VHDL Problem 8.12: Cars on Road Detector library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity CarsOnRoad is port(Clear: in std_logic; -- Reset the counter CountUp: in std_logic; -- Count up on neg edge CountDown: in std_logic; -- Count down on neg edge RoadClear: out std_logic); -- Road clear if count = 0 end Problem8_12_CarsOnRoad; architecture rtl of Problem8_12_CarsOnRoad is signal Q: unsigned(3 downto 0); -- 4-bit counter signal Clk: std_logic; -- internal clock signal UpDn: std_logic; -- latch up/down condition begin Clk <= CountUp or CountDown; -- create one clock pulse process (CountUp, CountDown) begin -- latch the direction if (CountUp = '1') then UpDn <= '1'; --latch up direction elsif (CountDown = '1') then UpDn <= '0'; --latch down direction end if; end process;

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Digital Logic Circuit Analysis and Design, 2nd Edition

process(Clear, Clk) begin -- counter control if (Clear = '1') then Q <= "0000"; -- clear the counter elsif falling_edge(Clk) then -- pulse on CountUp or CountDown if (UpDn = '1') then Q <= Q + 1; -- increment count else Q <= Q - 1; -- decrement count end if; end if; end process; RoadClear <= '1' when (Q = "0000") else '0'; -- Road clear if count 0 end;

8.13. Design a Verilog or VHDL realization of the Traffic Counter used in the One-Lane Traffic Controller. // Verilog Problem 8.13: Traffic Counter module TrafficCounter(Pulse5Min, RESET, S1, G1, G2, Q8); input Pulse5Min, RESET, S1, G1, G2; output Q8; // counter bit 4 (value 8) wire Clear = RESET | Pulse5Min; //reset on signal or every 5 minutes wire CountUp = ~(S1 & G1); //sensor 1 low pulse during Green 1 wire CountDown = ~(S1 & G2); //sensor 1 low pulse during Green 2 wire Clk = CountUp & CountDown; //combine pulses for counter clock reg UpDn; //latch up/down count direction reg [3:0] Q; //4-bit count always @(negedge CountUp or negedge CountDown) begin //up or down pulse? if (~CountUp) UpDn = 1'b1; //latch up condition else UpDn = 1'b0; //latch down condition end always @(posedge Clear or posedge Clk ) begin if (Clear) Q = 4'h0; //clear counter else if (UpDn == 1'b1) Q = Q + 1; //increment else if (UpDn == 1'b0) Q = Q - 1; //decrement end assign Q8 = Q[3]; // MSB of counter has weight 8 endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- VHDL Problem 8.13: Traffic Counter library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity TrafficCounter is port(Pulse5Min: in std_logic; -- 5 minute reset pulse RESET: in std_logic; -- Reset counter G1, G2: in std_logic; -- Green lights active S1: in std_logic; -- Sensor 1 pulses Q8: out std_logic); -- 4th count bit (count >= 8) end Problem8_13_TrafficCounter; architecture rtl of Problem8_13_TrafficCounter is signal Q: unsigned(3 downto 0); -- 4-bit counter signal Clear, Clk: std_logic; -- internal reset and clock signal CountUp, CountDown: std_logic; -- count up/down low pulses signal UpDn: std_logic; -- latch up/down condition begin CountUp <= S1 nand G1; -- pulse if sensor 1 pulse during Green 1 CountDown <= S1 nand G2; -- pulse if sensor 1 pulse during Green 2 Clk <= CountUp and CountDown; -- merge active-low pulses Clear <= Pulse5Min or RESET; -- merge reset conditios process (CountUp, CountDown) begin -- latch the direction if (CountUp = '0') then UpDn <= '1'; --latch up direction elsif (CountDown = '0') then UpDn <= '0'; --latch down direction end if; end process; process(Clear, Clk) begin -- counter control if (Clear = '1') then Q <= "0000"; -- clear the counter elsif rising_edge(Clk) then -- pulse on CountUp or CountDown if (UpDn = '1') then Q <= Q + 1; -- increment count else Q <= Q - 1; -- decrement count end if; end if; end process; Q8 <= Q(3); -- Output is MSB of counter (count >= 8) end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.14. Design a Verilog or VHDL realization of the Green-Time Allocator used in the One-Lane Traffic Controller. // Verilog Problem 8.14: Green-Time Allocator module GreenTimeAllocator(Pulse5Min, RESET, TC, T1); input Pulse5Min, RESET, TC; //TC = traffic count MSB output reg [3:0] T1; // T1 counter output wire Inhibit; // inhibit counter to limit min/max T1 time assign Inhibit = (~TC & T1[2] & T1[3]) | (TC & ~T1[2] & ~T1[3]); //max 12, min 4 always @(posedge RESET or negedge Pulse5Min ) begin if (RESET) T1 = 4'h7; //set counter = 7 else if (~Inhibit) begin //clock pulse and not inhibited if (TC == 1'b0) T1 = T1 + 1; //increase T1 time else T1 = T1 - 1; //decrease T1 time end end endmodule -- VHDL Problem 8.14: Green-Time Allocator library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity GreenTimeAllocator is port(Pulse5Min: in std_logic; -- Count every 5 minutes RESET: in std_logic; -- Load T1 with 7 on reset TC: in std_logic; -- Traffic Count >= 8 T1: out std_logic_vector(3 downto 0)); -- T1 time allocation end Problem8_14_GreenTimeAllocator; architecture rtl of Problem8_14_GreenTimeAllocator is signal Q: unsigned(3 downto 0); -- internal 4-bit counter signal Inhibit: std_logic; -- limit count to min=3 and max=12 begin Inhibit <= (not TC and Q(3) and Q(2)) or (TC and not Q(3) and not Q(2)); process(RESET, Pulse5Min) begin if (RESET = ‘1’) then Q <= “0111”; -- initialize T1 time to 7 elsif falling_edge(Pulse5Min) then if (Inhibit = ‘0’) and (TC = ‘0’) then Q <= Q + 1; -- increase T1 time elsif (Inhibit = ‘0’) and (TC = ‘1’) then Q <= Q - 1; -- decrease T1 time end if; end if; end process; T1 <= std_logic_vector(Q); -- drive output with count end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.15. Design a Verilog or VHDL realization of the Control Unit State Machine used in the OneLane Traffic Controller. // Verilog Problem 8.15: Traffic Control Unit State Machine module TrafficStateMachine(T1, T2, AllClear, CLK, RESET, R1, R2, G1, G2, Y1, Y2); input T1, T2, AllClear, CLK, RESET; output R1, R2, G1, G2, Y1, Y2; reg [5:0] Q; //6-bit shift register one-hot state wire Shift; //Shift enable assign Shift = (Q[5] & T1) | Q[4] | (Q[3] & AllClear) | (Q[2] & T2) | Q[1] | (Q[0] & AllClear); always @(posedge RESET or posedge CLK) begin if (RESET) Q = 6'b100000; //Initialize to state A for G1 R2 else if (Shift) Q = {Q[0],Q[5:1]}; //next state if Shift = 1 end assign {G1,Y1,G2,Y2} = {Q[5],Q[4],Q[2],Q[1]}; // drive outputs assign R1 =~(G1 | Y1); assign R2 =~(G2 | Y2); endmodule -- VHDL Problem 8.15: Traffic Control Unit State Machine library ieee; use ieee.std_logic_1164.all; entity TrafficStateMachine is port(T1,T2,AllClear: in std_logic; -- Time and all clear indicators RESET, CLK: in std_logic; -- Reset and time base G1,G2,Y1,Y2,R1,R2: out std_logic); -- Green, Yellow, Red controls end Problem8_15_TrafficStateMachine; architecture rtl of Problem8_15_TrafficStateMachine is signal Q: std_logic_vector(5 downto 0); -- 6-bit shift register for state signal Shift: std_logic; -- Shift enable begin Shift <= (Q(5) and T1) or Q(4) or (Q(3) and AllClear) or (Q(2) and T2) or Q(1) or (Q(0) and AllClear); process(RESET, CLK) begin if (RESET = ‘1’) then Q <= “100000”; -- Initialize to state A (G1, R2) elsif rising_edge(CLK) then if Shift = ‘1’ then Q <= Q(0) & Q(5 downto 1); end if; end if; end process; G1 <= Q(5); Y1 <= Q(4); R1 <= G1 nor Y1; -- drive outputs G2 <= Q(2); Y2 <= Q(1); R2 <= G2 nor Y2; end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.16. Realize an HDL design of the One-Lane Traffic Controller by integrating the unit designs from problems 12, 13, 15, and 15. // Verilog Problem 8.16: Time-Base Generator module TimeBaseGen ( input RESET, output TenSec, output Pulse5Min); reg CLK; // oscillator reg [3:0] Decade1, Decade2; // time base decade counters wire Clear; // clear counters initial CLK = 0; always #5 CLK = ~CLK; // Oscillate at T = 10ns (simulate 10s) assign Pulse5Min = Decade2[1] & Decade2[0]; //Decade2 = 3 assign TenSec = Decade1[3] & Decade1[0]; // Decade1=9 assign Clear = RESET | Pulse5Min; always @(posedge Clear, negedge CLK) begin if (Clear) begin Decade1 = 4'h0; end else begin if (Decade1 == 4'h9) Decade1 = 4'h0; else Decade1 = Decade1 + 1; end end always @(posedge Clear, negedge TenSec) begin if (Clear) begin Decade2 = 4'h0; end else begin if (Decade2 == 4'h9) Decade2 = 4'h0; else Decade2 = Decade2 + 1; end end endmodule // Verilog Problem 8.16: Green Timer module GreenTimer ( input RESET, CLK, G1, G2, // Reset, clock and green lights output reg [3:0] GreenTime, // Green T1+T2 = 16x10sec output T2); // Pulse end of T1+T2 wire GTClock; assign GTClock = CLK & (G1 | G2); // Enable clock during greens always @(posedge RESET, negedge GTClock) begin if (RESET) GreenTime = 4'h0; else GreenTime = GreenTime + 1; end assign T2 = (GreenTime == 4'hF) ? 1'b1 : 1'b0; // Pulse at end of T2 endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition

// Verilog Problem 8.16: One-Lane Traffic Controller module OneLaneTrafficController ( input RESET, S1, S2, // Reset and sensor inputs output G1, Y1, R1, G2, Y2, R2); // Light activators wire T1, T2; // From Green-Time Allocator wire TC; // MSB of traffic counter wire AllClear; // From Cars on Road Detector wire Pulse5Min; // 5m clock from Time-base oscillator wire CLK; // 10s clock from TIme-base oscillator wire [3:0] GreenTime; // Green timer output wire [3:0] GreenTimeAlloc; // Green time allocation for T1 // Instantiate modules to create top-level design TimeBaseGen TBV (.RESET(RESET), .TenSec(CLK), .Pulse5Min (Pulse5Min)); CarsOnRoad COR (.Clear(RESET), .CountUp(S1), .CountDown(S2), .RoadClear(AllClear)); TrafficCounter TCNT (.Pulse5Min(Pulse5Min), .RESET(RESET), .S1(S1), .G1(G1), .G2(G2), .Q8(TC)); GreenTimeAllocator GTA (.Pulse5Min(Pulse5Min), .RESET(RESET), .TC(TC), .T1(GreenTimeAlloc)); GreenTimer GTMR (.RESET(RESET), .CLK(CLK), .G1(G1), .G2(G2), .GreenTime(GreenTime), .T2(T2)); TrafficStateMachine TSM (.T1(T1), .T2(T2), .AllClear(AllClear), .CLK(CLK), .RESET(RESET), .R1(R1), .R2(R2), .G1(G1), .G2(G2), .Y1(Y1), .Y2(Y2)); assign T1 = (GreenTimeAlloc == GreenTime) ? 1'b1 : 1'b0; // compare allocated vs actual green time endmodule

-- Problem 8.16 VHDL: Time-Base Generator library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity TimeBaseGen is port ( RESET: in std_logic; TenSec: out std_logic; -- Clock with 10s period Pulse5Min: out std_logic); -- Pulse at T1+T2 end TimeBaseGen; architecture rtl of TimeBaseGen is signal CLK: std_logic := '0'; -- 10s period oscillator signal Clear: std_logic; -- oscillator, counter reset signal Decade1, Decade2: unsigned(3 downto 0); -- BCD counters begin CLK <= not CLK after 5 ns; --Simulate 1s oscillator period Pulse5Min <= Decade2(1) and Decade2(0); --Decade2 roll over at 3 TenSec <= Decade1(3) and Decade1(0); --Decade1 roll over from 9

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Digital Logic Circuit Analysis and Design, 2nd Edition

end;

Clear <= RESET or Pulse5Min; --Reset counters after 5 min process (Clear, CLK) begin -- Decade1 counter if (Clear = '1') then Decade1 <= "0000"; elsif falling_edge(CLK) then if (Decade1 = "1001") then Decade1 <= "0000"; else Decade1 <= Decade1 + 1; end if; end if; end process; process (Clear, TenSec) begin -- Decade2 counter if (Clear = '1') then Decade2 <= "0000"; elsif falling_edge(TenSec) then if (Decade2 = "1001") then Decade2 <= "0000"; else Decade2 <= Decade2 + 1; end if; end if; end process;

-- Problem 8.16 VHDL: Green Timer library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity GreenTimer is port ( RESET, CLK, G1, G2: in std_logic; -- Count during green lights GreenTime: out std_logic_vector(3 downto 0); -- Green T1+T2 = 16x10sec T2: out std_logic); -- Pulse = end of T1+T2 end GreenTimer; architecture rtl of GreenTimer is signal GTClock: std_logic; -- counter enable signal GT: unsigned(3 downto 0); -- counter state begin GTClock <= CLK and (G1 or G2); -- enable clock during greens process (RESET, GTClock) begin if (RESET = '1') then GT <= "0000"; --reset green timer elsif falling_edge(GTClock) then GT <= GT + 1; --increment green timer end if; end process; GreenTime <= std_logic_vector(GT); -- drive output T2 <= '1' when GT = "1111" else '0'; -- pulse on last count end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- Problem 8.16 VHDL: Package of One-Lane Traffic Controller Component Declarations library ieee; use ieee.std_logic_1164.all; package TrafficComponents is component TimeBaseGen port ( RESET: in std_logic; TenSec: out std_logic; -- Clock with 10s period Pulse5Min: out std_logic); -- Pulse at T1+T2 end component; component GreenTimer port ( RESET, CLK, G1, G2: in std_logic; GreenTime: out std_logic_vector(3 downto 0); -- Green T1+T2 = 16x10sec T2: out std_logic); -- Pulse end of T1+T2 end component; component CarsOnRoad port(Clear: in std_logic; -- Reset the counter CountUp: in std_logic; -- Count up on neg edge CountDown: in std_logic; -- Count down on neg edge RoadClear: out std_logic); -- Road clear if count = 0 end component; component TrafficCounter port(Pulse5Min: in std_logic; -- 5 minute reset pulse RESET: in std_logic; -- Reset counter G1, G2: in std_logic; -- Green lights active S1: in std_logic; -- Sensor 1 pulses Q8: out std_logic); -- 4th count bit (count >= 8) end component; component GreenTimeAllocator port(Pulse5Min: in std_logic; -- Count every 5 minutes RESET: in std_logic; -- Load T1 with 7 on reset TC: in std_logic; -- Traffic Count >= 8 T1: out std_logic_vector(3 downto 0)); -- T1 time allocation end component; component TrafficStateMachine port(T1,T2,AllClear: in std_logic; -- Time and all clear indicators RESET, CLK: in std_logic; -- Reset and time base G1,G2,Y1,Y2,R1,R2: out std_logic); -- Green, Yellow, Red controls end component; end TrafficComponents;

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Digital Logic Circuit Analysis and Design, 2nd Edition

-- Problem 8.16 VHDL: One-Lane Traffic Controller (top level) library ieee; use ieee.std_logic_1164.all; use work.TrafficComponents.all; -- Package of component declarations entity OneLaneTrafficController is port (RESET, S1, S2: in std_logic; -- Reset and sensor inputs G1, Y1, R1, G2, Y2, R2: out std_logic); -- Light activators end OneLaneTrafficController; architecture rtl of OneLaneTrafficController is signal T1, T2: std_logic; -- From Green-Time Allocator signal TC: std_logic; -- MSB of traffic counter signal AllClear: std_logic; -- From Cars on Road Detector signal Pulse5Min: std_logic; -- 5m clock from Time-base oscillator signal CLK: std_logic; -- 10s clock from TIme-base oscillator signal G1T, G2T: std_logic; -- internal G1/G2 signal GreenTime: std_logic_vector(3 downto 0); -- Green timer output signal GreenTimeAlloc: std_logic_vector(3 downto 0); -- Green time allocation for T1 begin IBV: TimeBaseGen port map (RESET=>RESET, TenSec=>CLK, Pulse5Min=>Pulse5Min); COR: CarsOnRoad port map (Clear=>RESET, CountUp=>S1, CountDown=>S2, RoadClear=>AllClear); TCNT: TrafficCounter port map (Pulse5Min=>Pulse5Min, RESET=>RESET, S1=>S1, G1=>G1T, G2=>G2T, Q8=>TC); GTA: GreenTimeAllocator port map (Pulse5Min=>Pulse5Min, RESET=>RESET, TC=>TC, T1=>GreenTimeAlloc); GTMR: GreenTimer port map (RESET=>RESET, CLK=>CLK, G1=>G1T, G2=>G2T, GreenTime=>GreenTime, T2=>T2); TSM: TrafficStateMachine port map (T1=>T1, T2=>T2, AllClear=>AllClear, CLK=>CLK, RESET=>RESET, R1=>R1, R2=>R2, G1=>G1T, G2=>G2T, Y1=>Y1, Y2=>Y2); T1 <= '1' when (GreenTimeAlloc = GreenTime) else '0'; -- compare allocated to actual green time for T1 G1 <= G1T; G2 <= G2T; --drive outputs end;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.17. Design the UART transmitter controller defined in Figure 8.33 using fixed-logic components such as gates and flip-flops. Minimize the number of gates and flip-flops.

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.18. Design a serial parity generator as described in Figure 8.35 using fixed-logic components such as gates and flip-flops. Compare the complexity of the realizations for D and JK flip-flops.

Note that the Reset signal controls an asynchronous reset input on the D flip-flop, and the Enable signal enables Clock to control the flip-flop.

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.19. Design a fixed-logic realization of the UART start-bit detector described in Figure 8.39.

Minimize the number of gates and flip-flops required.

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.20. Design a fixed-logic realization of the UART receiver controller described in Figure 8.40.

Minimize the number of gates and flip-flops required.

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.21. Develop a realization of the two-floor elevator controller using fixed-logic.

State

Next States:

W1 C1 U2 W2 C2 D1

Inputs/Next States Outputs R1 R2 F1 F2 Open Arrive (z2z1z0) C1 U2 C1 U2 C1 C1 000 W1 U2 C1 U2 W1 C1 001 U2 U2 U2 U2 U2 W2 011 D1 C2 D1 C2 C2 C2 100 D1 W2 D1 C2 W2 C2 101 D1 D1 D1 D1 D1 W1 111

From W1: C1 if not (R2 or F2); U2 if (R2 or F2) From C1: W1 if (R1 or Open); U2 if (R2 or F2); C1 otherwise From U2: W2 if Arrive; U2 otherwise From W2: C2 if not (R1 or F1); D1 if (R1 or F1) From C2: W2 if (R2 or Open); D1 if (R1 or F1); C2 otherwise From D1: W1 if Arrive; D1 otherwise Outputs: 𝑧𝑧0 = 𝐶𝐶1 + 𝑈𝑈2 + 𝐶𝐶2 + 𝐷𝐷1 = (𝑊𝑊1 + 𝑊𝑊2) 𝑧𝑧1 = 𝑈𝑈2 + 𝐷𝐷1

𝑧𝑧2 = 𝑊𝑊2 + 𝐶𝐶2 + 𝐷𝐷1

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Digital Logic Circuit Analysis and Design, 2nd Edition

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.22. Develop a realization of the three-floor elevator controller for programmable logic using either Verilog or VHDL as the hardware description language. //Problem 8.22 Verilog - Three Floor Elevator Controller. module ThreeFloor ( input Clock,Reset,R1U,R2U,R2D,R3D,F1,F2,F3,Open,Arrive, //Declare inputs. output reg Z2,Z1,Z0); //Declare outputs. reg [3:0] State,NextState; //Declare state and next state variables. parameter W1=4'b0000,C1=4'b0001,U2=4'b0011, //Make state assignments.

W2=4'b1000,C2=4'b1001,D1=4'b0111, U3=4'b1011, W3=4'b1100,C3=4'b1101,D2=4'b1111; always @ (negedge Clock, negedge Reset) begin //Trigger on Clock or Reset input. if (Reset==0) State <= W1; // State W1 on Reset, otherwise NextState. else State <= NextState; end always @ * //Derive NextState which depends on present State and input. case (State) W1: begin if (R2U||R2D||F2||R3D||F3) NextState=U2; // Up if called else NextState=C1; end //Stay at 1 with door open C1: begin if (R2U||R2D||F2||R3D||F3) NextState=U2; //Up if called else if (R1U||Open) NextState=W1; //Stay at 1 and open door else NextState=C1; end //Stay at 1 with door closed U2: begin if ((Arrive)&&(R2U||R2D||F2)) NextState=W2; //Stop at 2 else if ((Arrive)&&(R3D||F3)) NextState=U3; //Continue to 3 else NextState=U2; end //Move up until 2 reached.

W2: begin if (R1U||F1) NextState=D1; //Start down if called to 1 else if (R3D||F3) NextState=U3; //Start up if called to 3 else NextState=C2; end //Stay at 2 with door open //Start down if called to 1 C2: begin if (R1U||F1) NextState=D1; else if (R3D||F3) NextState=U3; //Start up if called to 3 else if (R2U||R2D||Open) NextState=W2; //Open door on 2 if called else NextState=C2; end //Stay at 2 with door closed D1: begin if (Arrive) NextState=W1; //Stop at 1 and open door else NextState=D1; end //Move down until 1 reached.

U3: begin if (Arrive) NextState=W3; //Stop at 3 and open door else NextState=U3; end //Move up until 3 reached.

W3: begin if (R1U||F1||R2U||R2U||F2) NextState=D2; //Start down to 1 or 2 else NextState=C3; end //Stay at 3 with door open C3: begin if (R1U||F1||R2U||R2U||F2) NextState=D2; //Start down to 1 or 2 else if (R3D||Open) NextState=W3; //Open door if 3 called else NextState=C3; end //Stay at 3 with door closed D2: begin if ((Arrive)&&(R2U||R2D||F2)) NextState=W2; //Stop at 2 else if ((Arrive)&&(R1U||F1)) NextState=D1; //Continue to 1 else NextState=D2; end //Move down until 2 is reached. endcase assign {Z2,Z1,Z0} = State[2:0]; // Outputs are first three state bits endmodule

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Digital Logic Circuit Analysis and Design, 2nd Edition -- Problem 8.22 – Three floor elevator controller library ieee; use ieee.std_logic_1164.all; entity ThreeFloor is port ( R1U,R2U,R2D,R3D: in std_logic; -- Request buttons on floors 1-2-3 F1,F2,F3: in std_logic; -- Floor buttons in elevator car Dopen: in std_logic; -- Door open button in elevator car ARR: in std_logic; -- Arrived at floor sensor CLK: in std_logic; - Clock Direction: out std_logic; -- Up/Down control Motion: out std_logic; -- Motor on/off control Door: out std_logic ); - Door open/close control end ThreeFloor; architecture behavior of ThreeFloor is signal state: std_logic_vector (3 downto 0) := "0000"; -- Controller state constant W1: std_logic_vector (3 downto 0) := "0000"; -- Floor1 door open constant C1: std_logic_vector (3 downto 0) := "0001"; -- Floor1 door closed constant U2: std_logic_vector (3 downto 0) := "0011"; -- Moving up to 2 constant W2: std_logic_vector (3 downto 0) := "1000"; -- Floor2 door open constant C2: std_logic_vector (3 downto 0) := "1001"; -- Floor2 door closed constant D1: std_logic_vector (3 downto 0) := "0111"; -- Moving down to 1 constant U3: std_logic_vector (3 downto 0) := "1011"; -- Moving up to 3 constant W3: std_logic_vector (3 downto 0) := "1100"; -- Floor3 door open constant C3: std_logic_vector (3 downto 0) := "1101"; -- Floor3 door closed constant D2: std_logic_vector (3 downto 0) := "1111"; -- Moving down to 2 constant E1: std_logic_vector (3 downto 0) := "0010"; -- Error state 1 signal F1_L: std_logic := '0'; -- Latched buttons signal F2_L: std_logic := '0'; signal F3_L: std_logic := '0'; signal R1U_L: std_logic := '0'; signal R2D_L: std_logic := '0'; signal R2U_L: std_logic := '0'; signal R3D_L: std_logic := '0'; begin Door <= state(0); -- z0=Door 0=open 1=close Motion <= state(1); -- z1=Motion 0=stop 1=move Direction <= state(2); -- z2=Direction 0=up 1=down process(state,F1,F2,F3,R1U,R2U,R2D,R3D) begin if (state = W1) then F1_L <= '0'; -- Cancel F1 if on floor 1 elsif (state /= C1) then if (F1 = '1') then F1_L <= '1'; end if; -- Set F1 if not in C1 end if;

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Digital Logic Circuit Analysis and Design, 2nd Edition if (state = W1) then R1U_L <= '0'; -- Cancel R1U if door open else if (R1U = '1') then R1U_L <= '1'; end if; --O/W set R1U latch end if; if (state = W2) then F2_L <= '0'; --cancel F2 if on floor 2 elsif (state /= C2) then if (F2 = '1') then F2_L <= '1'; end if; -- Set F2 if not in C2 end if; if (state = W2) then R2U_L <= '0'; --cancel R2U if door already open else if (R2U = '1') then R2U_L <= '1'; end if; -- Set R2U end if; if (state = W2) then R2D_L <= '0'; --cancel R2D if door already open else if (R2D = '1') then R2D_L <= '1'; end if; -- Set R2D end if; if (state = W3) then F3_L <= '0'; -- Cancel F3 if on floor 3 elsif (state /= C3) then if (F3 = '1') then F3_L <= '1'; end if; -- Set F3 if not in C3 end if; if (state = W3) then R3D_L <= '0'; -- Cancel R3D if door already open else if (R3D = '1') then R3D_L <= '1'; end if; -- Set R3D end if; end process; process(CLK) begin if rising_edge(CLK) then case (state) is when W1=> if (((R2U_L or R2D_L or R3D_L) = '0') and ((F2_L or F3_L) = '0')) then state <= C1; elsif ((R2U_L or R2D_L or F2_L or R3D_L or F3_L) = '1') then state <= U2; else state <= W1; end if; when C1=> if ((R2U_L or R2D_L or F2_L or R3D_L or F3_L) = '1') then state <= U2; elsif ((R1U_L or Dopen) = '1') then state <= W1; else state <= C1; end if; when U2=> if ((ARR = '1') and ((R2U_L or R2D_L or F2_L) = '1')) then state <= W2;

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Digital Logic Circuit Analysis and Design, 2nd Edition elsif ((ARR = '1') and ((R3D_L or F3_L) = '1') and ((R2U_L or R2D_L or F2_L) = '0')) then state <= U3; else state <= U2; end if; when W2=> if ((R3D_L or F3_L) = '1') then state <= U3; -- go to floor 1 elsif ((R1U_L or F1_L) = '1') then state <= D1; -- go to floor 3 elsif (((R1U_L or F1_L) = '0') and ((F1_L or F3_L) = '0')) then state <= C2; else state <= W2; end if; when C2=> if ((R1U_L or F1_L) = '1') then state <= D1; -- go to floor 1 elsif ((R3D_L or F3_L) = '1') then state <= U3; -- go to floor 3 elsif ((R2U_L or R2D_L or Dopen) = '1') then state <= W2; -- open door on 2 else state <= C2; end if; when D1=> if (ARR = '1') then state <= W1; -- stop going down when we arrive at floor 1 else state <= D1; end if; when U3=> if (ARR = '1') then state <= W3; -- stpo going up when we arrive at floor 3 else state <= U3; end if; when W3=> if ((R1U_L or F1_L or R2D_L or R2U_L or F2_L) = '1') then state <= D2; elsif (((R1U_L or R2U_L or R2D_L) = '0') and ((F1_L or F2_L) = '0')) then state <= C3; else state <= W3; end if; when C3=> if ((R1U_L or F1_L or R2D_L or R2U_L or F2_L) = '1') then state <= D2; elsif ((R3D_L or Dopen) = '1') then state <= W3; else state <= C3; end if; when D2=> if ((ARR = '1') and ((R1U_L or F1_L) = '1') and ((R2U_L or R2D_L or F2_L) = '0')) then state <= D1; elsif ((ARR = '1') and ((R2D_L or R2U_L or F2_L) = '1')) then state <= W2; else state <= D2; end if; when others => state <= E1; -- Error state end case;

end if; end process; end behavior;

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.23. Develop a block diagram and a state diagram for a four-floor elevator controller.

States (y4y3y2y1y0): Wx = 0xx00, Cx = 0xx01, Ux = xx011, Dx = xx111 Outputs (y4y3y2y1y0): Direction z2 = y2 (0 up, 1 down), Motion z1 = y1 (1 moving, 0 not), Door z0 = y0 (1 closed, 0 open).

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Digital Logic Circuit Analysis and Design, 2nd Edition

8.24. Derive an equation for the number of states needed for an elevator controller for an nstory building. How many flip-flops would be required to realize the controller?

Assume the design approach used in this chapter for elevator controllers. 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 = 𝑛𝑛 + 𝑛𝑛 + (𝑛𝑛 − 1) + (𝑛𝑛 − 1) = 4𝑛𝑛 − 2

This includes one W and one C state for each of the n floors, n-1 D states from higher to lower floor, and n-1 U states from lower to higher floor.

The number of required flip-flops is thus ⌈𝑙𝑙𝑙𝑙𝑙𝑙2 (4𝑛𝑛 − 2)⌉ for a minimal state assignment, or 4n-2 for a one-hot state assignment.

8.25. Design a display for the three-floor elevator that shows the floor location and direction of travel (DOT). The DOT indicators should be blank when the elevator is not in motion.

Assume you have three active-low seven-segment display devices to use in the display.

First digit: 1 in states W1 or C1 or U2 (on floor 1, or left floor 1 and not yet at floor 2.)

2 in states W2 or C2 or U3 or D1 (on floor 2, or left floor 2 and not yet at floor 1 or 3.)

3 in states W3 or C3 or D2 (on floor 3, or left floor 3 and not yet at floor 2.)

Second digit: U in states U2 or U3; otherwise blank Third digit: D in states D1 or D2; otherwise blank Display: Segments: A BC D E F G FLR 1 1 0 0 1 1 1 1 FLR 2 0 0 1 0 0 1 0 FLR 3 0 0 0 0 1 1 0 DOT U 1 0 0 0 0 0 1 DOT D 1 0 0 0 0 0 1 Blank 1 1 1 1 1 1 1

State (y3y2y1y0) (unused states: 0010, 0100, 0101, 0110, 1010, 1110

W1(0000) or C1(0001) or U2(0011) = ∑m(0,1,3)+d(2,4,5,6,10,14) W2(1000) or C2(1001) or U3(1011) or D1(0111) = ∑m(0,1,3)+d(2,4,5,6,10,14) W3(1100) or C3(1101) or D2(1111) = ∑m(12,13,15)+d(2,4,5,6,10,14) U2(0011) or U3(1011) = ∑m(3,11)+d(2,4,5,6,10,14) D1(0111) or D2(1111) = ∑m(7,15)+d(2,4,5,6,10,14) All other conditions

The Floor Digit circuit is created by plotting each segment on a K-map, combining the six don’t cares and the state minterms for which the segment is 1. Note that segment B is 0 for all three floors and segment F is 1 for all three floors.

The DOT digit circuits are likewise created by plotting one K-map for each, to display U for Up and D for Down, and otherwise force the display to blanks (all 1s).

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Digital Logic Circuit Analysis and Design, 2nd Edition

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