EDA Tech Forum Journal

The Technical Journal for the Electronic Design Automation Community

www.edatechforum.com

Volume 6

Issue 5

December 2009

Embedded ESL/SystemC Digital/Analog Implementation Tested Component to System Verified RTL to Gates Design to Silicon

INSIDE: Profit and the electric car Refining R&D productivity MCU prototyping online A third dimension for SiP Automation extends test

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December 2009

contents < COMMENTARY > 5

< TECH FORUM > 22 Embedded

Start Here

The realities of e-design

Even today, it’s not clear how engineers are using the Internet.

6 Analysis

The A word

As the global recession ends, the shape of the recovery is making product shortages inevitable.

Rapid prototyping for MCUs Simon Ford, ARM

30 ESL/SystemC

Overcoming the limitations of data introspection for SystemC

Christian Genz & Rolf Dreschsler, University of Bremen

36 Verified RTL to gates

Power management in OCP-IP 3.0 Christophe Vantinel, Texas Instruments

44 12 Interview

Wright on target

A pioneer in electric vehicle technology is using a different economic model from the automotive giants.

Digital/analog implementation

Interoperable PDKs accelerate analog EDA innovation Jigwen Yuan, Synopsys

48 Design to silicon

Making SiP happen in 3D 16 Design Management

Raising the bar to manage R&D and ROI Ron Collett explains how team leaders can set aggressive yet viable project goals.

Special Report, EDA Tech Forum

56 Tested component to system

Silicon test moves up the food chain Ron Press, Mentor Graphics

EDA Tech Forum Volume 6, Issue 5 December 2009

EDA Tech Forum Journal is a quarterly publication for the Electronic Design Automation community including design engineers, engineering managers, industry executives and academia. The journal provides an ongoing medium in which to discuss, debate and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques and trends.

< www.edatechforum.com/journal > EDA Tech Forum Journal is distributed to a dedicated circulation of 50,000 subscribers.

EDA Tech Forum is a trademark of Mentor Graphics Corporation, and is owned and published by Mentor Graphics. Rights in contributed works remain the copyright of the respective authors. Rights in the compilation are the copyright of Mentor Graphics Corporation. Publication of information about third party products and services does not constitute Mentor Graphics’ approval, opinion, warranty, or endorsement thereof. Authors’ opinions are their own and may not reflect the opinion of Mentor Graphics Corporation.

3

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Untitled-4 1

11/24/09 10:06:49 AM

EDA Tech Forum December 2009

start here

The realities of e-design

One of the livelier public debates at DAC looked at how engineers and vendors are using such media as blogs, social networking and instant messaging for business. There are plenty of good ideas, with companies using new technologies constructively and informatively—but I still have a problem with how this new frontier is presented.

There is an assumption that all branches of engineering use online tools with much the same enthusiasm and intent. However, in talking to the staff actually running sites and services, a different picture emerges suggesting a much broader shading of behavior. Here is a coarse but hopefully still instructive look at that.

On one hand, there are the software designers. They live up to the image of aggressive, frequent users of social networks in a business context.

Here, my informants keep referring me to the importance of open source, not just in providing a framework for creating new services, but also in spreading a culture that promotes their use. Software people are used to collaborating online and sharing discoveries with people they have not met in the flesh. It is all part of feeding something back into the development process. More than that, it is expected.

However, among hardware designers a broader mix of attitudes is apparently on display. Some are as enthusiastic as their software counterparts but they are probably not in the majority. In fact, a senior executive with a tier-one chip company recently told me how its trials of a Twitter identity had yielded extremely modest results.

Here, what you could say is that the hardware business is more systemically secretive. Minor architectural details can still equal significant competitive advantage, and third-party suppliers—whether they offer tools, IP, foundry or other back-end services—also guard the ‘secret sauce’ jealously.

Beyond that, there is also the historic and ongoing importance of the military and security sectors, where secrecy is intrinsically vital. Even engineers who have left these sectors admit to carrying important aspects of the mind-set with them.

Yes, software has historically faced similar issues, but open source does seem to have made a difference. However, it may also be fair to say that there are very few success stories getting a public airing from hardware.

We’ve been quietly running a ‘Design Management’ section in the magazine for a few issues, and now I’d like to specifically reach out to those companies that have already begun to work with new productivity technologies to tell us what they can about getting it right. Please email me at pauld@rtcgroup.com. The one thing that the online world has shown us is that to share is to win.

Paul Dempsey Editor-in-Chief

5

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< COMMENTARY > ANALYSIS

The A word As the semiconductor industry moves out of recession, a new capacity crunch looms. Paul Dempsey reports.

According to the International Monetary Fund’s (IMF) latest World Economic Outlook, the possibility of a ‘double-dip’ recession cannot yet be discounted even if current data show the world economy beginning to recover. The IMF’s main concern is that private demand (including consumer spending) is not showing enough strength to restore consistent global GDP growth by replacing public sector stimulus spending. In this context, it seems almost perverse to raise the prospect of severe product shortages in key technology sectors—nevertheless they now look certain for semiconductors.

Several analysts have been warning of the possibility for some time. One of the most vocal has been Bill McClean, president of IC Insights, and he has since been joined by figures such as Malcolm Penn, chairman and CEO of Future Horizons (who can also point to a background in chip manufacturing).

More to the point, several companies have acknowledged that some (if not all) of their product lines are already being affected. The canary in the coal mine is the historically volatile market for memories, particularly DRAMs and flash. Micron Technology supplies both technologies. Steve Appleton, its chairman and CEO, said this while announcing the company’s Q4 financials: “It appears that industry supply growth and capital spending are at extremely low levels, leaving many products on allocation. We remain optimistic that these trends will continue.”

‘Allocation’, for those unfamiliar with the term, is chipspeak for ‘rationing’. Appleton added that the $750M-$850M that Micron has set aside for capex in the current financial year will be “focused around getting more out of existing facilities.” No new lines and certainly no new fabs will be added as the supply crunch intensifies.

A second-hand rose

One intriguing tale involves Texas Instruments (TI). It recently announced plans to equip a fab shell in Richardson, Texas that was built in 2006 but mothballed. It will manufacture an annual $1B worth of analog semiconductors on 300mm wafers, using second-hand equipment purchased after the bankruptcy earlier this year of memory specialist Qimonda.

Not that long ago, TI announced plans to get out of manufacturing as far as possible and outsource production to

Source: iSuppli

NAND CapEx

DRAM CapEx $35,000

$30,000 10,400 $25,000

$20,000

8,230 9,900

5, 330 $15,000 3,230 21,100

$10,000 15,480 $5,000

13,510

10,775

10,829

2,450 3,850

$0 2004

2005

2006

2007

2008

2009

FIGURE 1 Memory industry capital expenditure ($M) third-party foundries, as has the bulk of the semiconductor industry. But this does look at first glance like a very sweet opportunity. “The time is right for this investment,” said Rich Templeton, TI’s chairman, president and CEO. “Customer demand for analog chips is growing, and there’s tremendous desire to save energy and protect the environment.”

Original capex for Richardson was estimated at $3B, albeit under a plan that would have seen it produce digital rather than analog ICs; the equipment being bought from Qimonda is bang up to date but will cost TI just $172.5M. Even given what TI has spent and will have to spend to install, staff and further prepare the site, it still gets the fab for a fraction of its original price.

Also, as one of the foundries’ biggest clients, it has been given some indication of the capacity crunch looming. Its suppliers are already talking about allocation in private and will soon do so in public. So, the ‘fab-lite’ TI became sufficiently concerned about supply chain bottlenecks that it

EDA Tech Forum December 2009

”Do we expect the foundries to do more for less forever?”

Source: Future Horizons 2,200

0.7 µm & Above < 0.2 µm to 0.16 µm

< 0.7 µm to 0.4 µm < 0.16 µm to 0.12 µm

< 0.4 µm to 0.3 µm < 0.12 µm to 0.08 µm

< 0.3 µm to 0.2 µm < 0.08 µm

200 mm Equ WSpW x 100 C

2,000 1,800 1,600 1,400 1,200 1,000 800 600 400 200 0 <0.08 µm <0.12 µm to 0.08 µm <0.16 µm to 0.12 µm <0.2 µm to 0.16 µm <0.3 µm to 0.2 µm <0.4 µm to 0.3 µm <0.7µm to 0.14 µm 0.7µm & Above

1Q-05 0.0 288.5 285.9 165.6 105.9 187.5 195.9 174.6

2Q-05 3Q-05 4Q-05 1Q-06 2Q-06 3Q-06 4Q-06 1Q-07 2Q-07 3Q-07 4Q-07 1Q-08 2Q-08 3Q-08 4Q-08 1Q-09 2Q-09 0.0 0.0 0.0 35.0 95.0 205.0 285.0 395.0 490.0 616.9 633.4 722.1 894.6 963.1 931.1 884.3 900.9 328.8 379.7 426.2 443.1 447.0 422.6 412.9 409.5 405.5 403.1 404.1 385.8 290.1 258.8 234.7 196.6 181.0 286.0 277.9 284.6 297.8 290.4 288.8 292.9 276.7 270.4 274.0 286.7 272.4 256.6 252.7 232.1 233.5 221.9 172.2 165.2 162.5 163.6 168.4 152.9 149.2 142.5 143.4 147.0 145.3 138.4 133.7 128.4 149.0 136.8 131.4 105.1 101.7 106.6 102.3 106.8 110.4 111.5 95.2 106.7 105.9 104.1 102.6 87.0 86.0 92.3 78.2 80.3 185.4 194.8 194.7 194.3 194.8 189.2 193.2 156.7 152.7 149.5 150.5 146.2 144.9 147.3 156.9 143.8 128.1 187.2 188.2 188.7 189.0 179.0 183.5 183.3 170.0 175.5 173.8 170.9 159.1 163.4 161.2 165.6 144.6 112.7 162.9 175.4 174.9 185.9 179.0 170.9 171.8 148.8 151.2 148.9 149.8 152.2 150.5 147.0 148.7 124.3 106.7

* New Capacity Comes On Stream Very Smoothly (Demand Doesn’t) (But One Year After It’s ‘Planned’ For... No Scope For Fine Tuning) * Q1-09 Was - 8.0%, The Biggest Quarterly Capacity Fall In SC History * Q2-09 Was Not Much Better At A Further - 4.1% * Q2-09 Capacity Is Down 14% On Q3-08’s Peak, Q2/Q4 Lower Still

FIGURE 2 Worldwide MOS wafer fab capacity also speeded up the opening of a test and packaging facility for its chips in the Philippines. Richardson is a very costeffective hedge against the looming problems.

But what are the dynamics behind the existing and incoming shortages, and why do they point to lengthy shortages?

There are principally three closely interlinked elements. First, the shape of this recession. Second, the initial response to it as seen across most industries, not just semiconductors. And third, a longer-term factor concerning the growing power of the foundries in the chip business and their financial needs.

V-shaped… probably

Chip demand has never fallen nor returned so sharply as it has during this recession. For one thing, the last time the

world economy suffered so intense a spasm, semiconductors did not exist. According to IC Insights, Q4 of 2008 saw a 21% slump in demand followed by a 20% fall in Q1 of this year. However, this was followed by 26.1% growth in Q2, and Bill McClean is forecasting 17.6% for Q3.

“What you have here is a classic V-shaped recovery curve, albeit a very extreme one, because there’s no other way of saying it—we dove to the bottom,” he says. “Those dynamics alone make shortages inevitable and the numbers for [manufacturing] capacity utilization bear that out further.

In Q1 it was about 55%, then about 75% in Q2, and it’s going to be around 90% in Q3.”

Continued on next page

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< COMMENTARY > ANALYSIS

Source: Future Horizons

Revenue Per Sq Cm

2003

2004

2005

2006

2007

2008

Chartered

$3.21

$3.29

$3.43

$3.30

$2.79

$2.74

SMIC

$2.45

$3.38

$2.80

$2.88

$2.67

$2.68

TSMC

$5.04

$4.81

$4.66

$4.25

$3.91

$3.79

UMC

$3.54

$4.00

$3.22

$3.13

$2.92

$2.81

Foundry Avg

$4.22

$4.30

$3.92

$3.71

$3.40

$3.33

Industry Avg

$7.50

$8.37

$8.48

$8.09

$7.42

$6.96

FIGURE 3 Foundry wafer prices at rock bottom

Back on track Analysts at iSuppli have called the recovery in semiconductor revenues for the current quarter. Although overall 2009 sales are still set to decline by 16.5%, the company said that Q4 revenues will be up 10.6% against the same period last year.

“The seeds of the current recovery were sown in the second quarter,” said Dale Ford, its senior vice president, market intelligence. “During that period, manufacturers began to report positive book-to-bill ratios, indicating future revenue growth. This was followed by another sequential increase in revenue in the third quarter.

“Meanwhile, semiconductor inventories returned to more normal levels in the third quarter after chip suppliers shed stockpiles. They did this by slashing costs dramatically in order to reduce unsold inventory they’d been carrying since the beginning of 2009.”

While these signs are encouraging, and sequential quarterly increases in revenue will continue into 2010, Ford warned that this growth will not be sufficient to lift semiconductor revenues back to pre-recessionary levels until the 2011-2012 time frame.

Furthermore, there remain some worrisome indicators, such as the climbing U.S. unemployment rate, which reached 9.7% in August and is projected to peak at more than 10%. Persistent difficulties in the credit and banking markets as well as the rising number of foreclosures in the U.S. housing market also still cloud the macroeconomic outlook.

Meanwhile, the pattern of a weak first half of the year followed by a strong second will persist into 2010. The company expects to see revenue that is slightly down compared to the Q4 of 2009—but the second half of the year will deliver a strong performance. This will result in 13.8% growth in global semiconductor revenue in 2010, ending the two-year losing streak. Subsequent years will see a return to single-digit percentage growth in the semiconductor industry as conditions stabilize.

Another important wrinkle is then added by the fact that this pattern does not match what has happened in leading markets for finished products with significant chip content. “If you look at PCs, those have been roughly flat. Cell phones are down 5-6%. Flat panel TVs are flat, maybe down 1-2%. Now, those are broad numbers, but what you can say for sure is that relative to the worst global recession in 63 years, end-use demand has held up really well,” says McClean.

The mismatch between supply and demand even when things were bad is clear and is the most obvious factor making long-term shortages now a certainty rather than simply a high risk. However, the depth and length of those shortages is being exacerbated by the nature of the industry’s initial response.

Too lean, too mean?

“The industry went into this recession in better shape than it has for any other before,” Future Horizon’s Malcolm Penn told this fall’s International Electronics Forum (IEF). “It was lean, it was mean. But then there was also some panic.”

Penn’s data shows that actual output capacity fell by 8% in Q1 of 2009 and then dropped another 4.1% in Q2. “We have never cut back capacity as steeply as this in history,” he continued, going on to also cite the failure of Qimonda. “State-of-theart 300mm fabs have closed down—this is the good stuff, not the older stuff that you expect to go, and it’s not easy to bring that back online. And there are more fab closures to come.”

Capex numbers tell a similar story. Both Penn and McClean judge this at 12% of sales for 2008, but Penn has it slumping to 7%—another all-time low—in 2009. “And what that means is that it’s not just 2010 where you are going to see tight capacity, but 2011’s written off as well. If all the foundries were to double capex right now that would still bring the 2010 number to only 8%, and that simply isn’t enough,” said Penn. Even where money is spent, it takes time to bring capacity online. “We’re in a business where demand ramps sharply late in the year anyway, typically, around Q3 and Q4 running into Christmas, but you can only ever bring new manufacturing into play very gradually,” says McClean.

A case in point here is TI’s plan for Richardson. The 330

EDA Tech Forum December 2009

Source: WSTS/IC Insights

“Racing to Bottom” (Sequential Quarterly Declines)

Sequential IC Unit Volume Decline

0%

-5%

-4% -7%

-10%

-8% -10%

-12% -15%

-20%

-15% 3Q85=75% of 4Q84 Peak 3Q01=70% of 3Q00 Peak

-25% 1Q85

2Q85

3Q85

1Q01

2Q01

-20% -21% 1Q09=64% of 3Q08 Peak

3Q01

4Q08

1Q09

Year

FIGURE 4 History of major IC unit volume adjustments Source: WSTS/IC Insights

30%

Sequential Quarterly Growth

26.1%

20%

17.6%

16.7%

16.0%

15.3%

15.2%

14.2%

13.2%

13.1%

2Q86

3Q05

11.7%

10%

0% 2Q09

3Q09F

2Q03

2Q02

2Q87

1Q84

4Q83

2Q84

Quarter

FIGURE 5 Top 10 quarterly IC unit volume growth rates on record tools it is buying from the Qimonda fire sale, give it all but six of the pieces of equipment it needs. And yet, it began installing the equipment last month, it does not expect chips to come out of the fab until the end of 2010. Even then it will be some time before capacity ramps to the optimum level.

And this, remember, is a ‘jump start’ by the standards of chip manufacturing.

The new supply chain

What further compounds this initial brace of issues is the realization that an extended period of shortages is just what some parts of today’s semiconductor supply chain need.

“We talk about the boom-bust cycle in semiconductors, and for a long time that is exactly what we had, with periods of Continued on next page

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< COMMENTARY > ANALYSIS

over- and under-supply balancing one another out,” says McClean. “But this time, there wasn’t really a boom, in that you didn’t have several years of strong double-digit growth before things went off the cliff.”

In the memory market specifically, volatility was all part of the game. “Companies would enjoy the good years, then the bad ones would come along and almost force them out of business. But then the cycle would start again and save them,” said Penn “Not this time.” Alongside Qimonda, flash supplier Spansion is also currently undergoing a Chapter 11-led restructuring, and only a staggering 60% rise in the average selling price (ASP) of DRAM between January and August may have headed off a complete bloodbath in the sector.

Now, the upward surge in ASPs will allow some manufacturers to catch their breath and restock their war chests.

They also need to face the new reality, as identified by another IEF speaker, former STMicroelectronics CEO Pasquale Pistorio, that there is no easy credit—companies are going to have to get much smarter at building, developing and deploying their internal cash resources, and the chip business is very cash hungry.

Source: TSMC

(sometimes all) of their fabs to get “cheaper” and “more cost-effective” services from third-party manufacturers.

Data from Future Horizons show that all the leading foundries have been getting less revenue per square centimeter of every silicon wafer they produce for at least five years. For the very largest company, Taiwan’s TSMC, a figure that stood at $5.04 in 2003 was $3.79 by 2008 even though the company’s spending on new fab capacity and process R&D was matched by, if anyone, only Intel, the world’s largest chip company.

“Do we expect them [the foundries] to do more for us for less forever? How flawed is this assumption? Aren’t their shareholders going to ask some questions?” Penn offered as a rhetorical flourish during the IEF, because he knows the answer there well enough. “The big winners out of all this will be the foundries, and the biggest winner will be TSMC, because it does have the resources and the others are much smaller,” he said.

McClean shares this view and indeed believes that the process began over a year ago. “It is not as though TSMC has tried to keep its feelings secret—it has made it very clear that the numbers had to improve, and as it has taken a more dominant role in the foundry market, it has acted accordingly. It started to control capex a while ago to make it clear that all the technology it provided, all the IP, all the integration with customers that’s necessary for 32nm and 28nm, all that would have to be paid for.

“They have the market share to push their agenda and it would have been strange if they hadn’t.”

The incoming supply crunch greatly strengthens TSMC’s position. It has significant new capacity coming on stream at Phase 4 of its Fab 12 site in Taiwan. And it therefore has the power to set what it considers a much fairer price. As Penn says, “Get in the queue now guys—you might have a better chance.” The next move in the semiconductor supply chain will only be partly about a recession.

FIGURE 6 TSMC is expanding Fab12 but similar moves may be rare until 2011

Foundries to get tough on price

However, an even longer standing tension is now coming to the fore: that between the foundries and their various customers. It is a tension that has been there ever since the fabless semiconductor business took off and was followed by one-time integrated device manufacturers shedding much

Details on research from Future Horizons and the 2010 International Electronics Forum in Dresden can be found at www.futurehorizons.com. More details about research from IC Insights can be found at www.icinsights.com and from iSuppli at www.isuppli.com.

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< COMMENTARY > INTERVIEW

Wright on target Electric vehicle pioneer Ian Wright is aiming for a different target from Detroit.

We are given plenty of reasons why we ‘should’ all buy electric cars. They will safeguard the environment. They will enhance national security by reducing our dependence on foreign oil. They will create a Detroit 2.0 that can pay back the taxpayer. What we do not hear is a more free-market economic argument.

“And the reason for that is because it fails,” says entrepreneur Ian Wright. “The fundamental problem is that you’re competing with the Toyota Camry, the best-selling midsize car in the U.S. For less than $20,000, it does more than 30mpg. You can buy one and be sure that you’ll get 50,000 miles out of it and it’ll be reliable. The way things are today, an electric car is going to be $50,000—and that still might be subsidized. The number of people willing to pay that kind of premium is vanishingly small.”

Wright is the CEO of Wrightspeed, and what is a bit counterintuitive here is that he is in the electric car business. A veteran of Tesla Motors, Wright’s own venture has already delivered a prototype, the X-1, that has outstripped many traditional ultra-high-performance cars going from 0-60mph in less than three seconds. He is also now talking to some large clients for his electrical vehicle (EV) technology. So, he is not trying to talk down his market here—rather, he thinks that it is being approached in the wrong way.

“How is it that so many companies are trying to build electric family and city cars?” he asks. “My theory is that the execs had a room full of engineers and they tossed out the wrong question. They said, ‘How can we make our vehicles more efficient?’ And the engineers thought, ‘OK, so what’s our most efficient vehicle, and how do we take, say, the [Toyota] Prius from 50mpg to 100?’ And that’s still wrong.

Because what they should have been asking is, ‘How do you save the most fuel?’”

This is not just about conserving resources. Wright makes an argument that does come down to cold, hard cash— economics, but from a different perspective. “If you look at where all the fuel is going, the biggest selling vehicle in the U.S. last year was the Ford F-Series pick-up truck. It’s been that every year for the last 25 years, and in fact, three of the top five cars are the big, full-size pick-ups. Now, if you take one of those trucks getting 10mpg and improve it to just 11.2mpg over 15,000 miles a year, you’re going to save more

fuel than you do by taking a Prius from 50mpg to 100mpg over 15,000 miles. Just go and do the arithmetic, it’s very simple.”

Indeed it is, and the numbers Wright offers represent fairly typical usage. But what matters more is that the transition from family to more heavy-duty vehicles also points the way toward the EV’s holy grail: a three-year payback to the buyer.

Again, taking the example of a mid-size car, the actual window of opportunity for electric drive is very small. Driving such a vehicle in congested traffic for about 10 hours a week—a pretty standard commuter experience—will consume about 150 gallons a year. At today’s $3 per gallon gas price, that means the wiggle room for an EV is about $450 a year, $1,350 over that three-year rule-of-thumb. So even though the Chevy Volt has been pitched at a net price of $32.500 ($40,000 dealer before a federal subsidy), it’s still some way off the $20,000 Camry. “You don’t cross the chasm,” says Wright.

But there is another model available in the shape of the stepvans used by delivery companies. “We’ve found that if we build our powertrain for an electric mid-size car it would cost x dollars and you can see the savings you get.

Now, if we build the powertrain for one of those delivery trucks, it costs more, about 2x, but the fuel savings are 10x because those things are burning three to four thousand gallons a year, and we can save almost all of it,” says Wright.

“You get that three-year payback.”

Wright acknowledges that even these numbers may not be exactly in place just yet, and one of the big obstacles is the batteries. “If you look at the good batteries—and you’ve got to use those for the reliability, for the recharge time, for the cycles—it’s about $1,000 a kWh, albeit with a reasonable projection of $500 in the foreseeable future, and once we get there you can get your payback. And if the price goes above $3 a gallon, then you’re saving a lot of money,” he says. “Here’s another way of looking at it. Say you reach $550 a kWh for the batteries, you have a 20kWh battery pack and a vehicle that uses 600Wh per mile. That’s a good stepvan profile. OK, so the same vehicle used to do 8mpg. If it does 125 miles a day, with a cost of capital at 5% per year, then you get the three-year payback and a really big return at five years.”

EDA Tech Forum December 2009

“Detroit had a room full of engineers and tossed out the wrong question.”

Credit: Scott Beale

FIGURE 1 The Wrightspeed X-1 can go from 0-60mph in less than three seconds Perhaps equally important, there is a potential here not only to build new vehicles but also for retrofits. Many of these vans have new powertrains fitted, so Wrightspeed could get into the market and start generating sales relatively quickly.

This is all a long way from the cool X-1 racer with which Wrightspeed made a splash almost four years ago. Wright himself admits that in commercializing its technology, the company will have to “change pretty much everything.”

However, he has not given up on the high-performance market for the water-carriers.

“One thing to remember about electric drive is that it breaks the 100-year tradition that we have to trade off performance and efficiency,” he says. “If you build in conventional powertrains, then if you want to be efficient, it’s going to be slow. If you want high performance, it’s going to be thirsty. And there really isn’t any way ‘round that. With an electric car that isn’t the case. So, here’s a comparison. If you take the McLaren F1 [supercar], it has similar performance to the X1, but the best you’re going to get out of it is 12mpg. Now, if you drive the X1 on the EPA combined cycle [used in the U.S. to formally rate gas usage] you get

the equivalent of 170mpg.”

The massive efficiencies possible with EVs have long been recognized. In a piston engine vehicle, about 85% of the energy in the gas tank is essentially thrown away as heat. In an EV, 85% of what comes out of the wall socket goes straight to the wheels. However, the real issue that Wright hits on here is the scope for optimization around a core design.

“Any competently engineered EV is going to be similar in efficiency, but you can now optimize across a big scale,” says Wright. “So say we optimize one vehicle for 50hp and another for 1,000hp. We can do that because we have the batteries, we have the motors. It’s not a problem. And now that you’ve done that, take two otherwise identical vehicles, drive them on the combined cycle and see which one uses more energy. Chances are it’s the 50hp one.

“If you think about it, the one that’s engineered for the higher power is going to have lower impedance batteries, it’s gonna have thicker wires, it’s gonna have lower I2R losses in the motors. It might have higher switching losses in the inverter, but on balance it’s probably going to use that Continued on next page

13

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< COMMENTARY > INTERVIEW

little bit less when you drive it to the EPA cycle, where you only need 30hp to 40hp. Yet for that car, you can put your foot down and you’ve got 1,000hp. That’s magic. That really changes things.”

In short, Wright is looking at coming at the market from two directions. “I know a few guys who drive the Bentleys and other big high-performance cars, and they’re a bit embarrassed at what they have and what it’s chugging down. But that market is also very open to new ideas, those drivers are looking for this kind of thing. Indeed, generally if you take our car around, people think it’s cool. There’s not that resistance to the fact that it’s an EV that I think I’d have expected a few years ago. And it’s the same with the guys already driving pick-up trucks. People will look at the options here.

“So this is going to be a surprise. You’re going to see EV coming from the high-performance end, and also from the high fuel consumption end. It’s not going to be the mainstream family cars to start with. In this example, if you’re building a supercar, you can also now approach the engineering by saying, ‘What top speed do I want?’ and then design the motor for a certain rpm; gear it for that top speed and just increase the power until you can do everything you want with just one gear. This is a very different world.”

In fact, the differences are not just in the best markets for the technology. The design approach is also fundamentally different to what has been seen in the automotive world before. If you look at a traditional vehicle, the effort and the intellectual property largely reside in the development, enhancement and refinement of the combustion engine.

“There’s a massive amount of black magic in the mechanical stuff, the shape of the CAM load, the materials used, the lubricants, the gas-flow dynamics,” says Wright. “When the torque feel of these cars doesn’t match what you need at the wheels, you have to dig down to yet another level of mechanical complexity to couple it. Or to put it another way—if you look at a company like Ferrari, what they do with the styling is incredible, but it still comes down to the engines and the transmissions.”

“When you think of all that, what we do is very different.

We’ve got a high-speed, permanent, brushless magnet DC motor. There are two stages of epicyclic gear reduction. You couple that to the wheels, and you’ve got three ball bearings and a couple of gears—and basically, you’re done. There’s no transmission. So where’s the complexity now, where’s that IP?” says Wright. “Well, you’re moving all that from the mechanical stuff into the software and the electronics.”

There are lots of DSPs and general-purpose processors in there. There are complex waveforms to generate for the motors. There are sophisticated sensing systems to provide optimization and even energy harvesting—for example, there’s the potential to recover energy from the 2500hp that a 16,000lb truck can put into braking on a hard stop. And, there is safety to consider. All of this and more means that Wright and his team still have their work to do.

FIGURE 1 Ugly or not, step vans could be crucial for the EV market But there is one other factor that comes into play here.

Because they are largely designing from the ground up, and not so inhibited by a century of prior innovation, Wright and his team can use a true system design approach.

“The existing car companies are really smart companies, and you can say that about Toyota or GM. But if you look at the design, first, yes, it is mechanically led, but second, it is also very incremental and very compartmentalized,” says Wright. “There’ll be one group of engineers working on the engine management systems and there will be another working on the stability control and so on. They’re systems, but they’re also black boxes.

“So, if you look at how a modern European luxury car works, you will hear a lot of talk about systems, but that’s about a set of black boxes inside and the wiring. You add and you add and when you’ve got something solved and in volume production, you don’t want to mess with it. So, rather than integrating things—which is what we look at doing if you take an electronics perspective—you look at hooking them together. It’s a different thing and it’s not as efficient. Though I can’t blame them for doing it like that— like I said, once you’ve got these things rolling off the production line, you get cautious.”

Also, the persistence of this design model may suit Wright well in the longer term. “I’m an optimist,” he says. “Within a decade, you’re gonna have electric motors driving wheels directly on more than 50% of cars. Now, for the family cars, it is going to be a long slog, but there are already some markets to aim for and that’s going to grow. Right now, though, for Detroit to be interested, you’ve got to be making probably more than 100,000 of these EVs a year—anything below isn’t of interest to them. They know what’s happening, but it’s not their business yet. But one day it will be.”

“When that happens, we’ll have the system experience for EVs, and what I’m hoping is that we can go to them and say, ‘Look, save yourselves a few years and few billion dollars’—and we license them the technology.”

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16

< COMMENTARY > DESIGN MANAGEMENT

Raising the bar to manage R&D and ROI Ronald Collett outlines some tested theories for differentiating chip design in the foundry era.

Semiconductor companies are hustling to grow revenues, stay on the razor’s edge of technology and remain one step ahead of their customers’ needs. All this is going on while the industry is undergoing wrenching change.

The end of 2009 finds the chip business at a crossroads. It has been more than 60 years since the invention of the transistor. The business-process innovations we have exploited to become ever more flexible and more profitable have essentially run their course.

The biggest of these processes is the chip manufacturing model. Today, virtually all semiconductor companies are fabless, and therefore the differentiation that they once had by virtue of controlling their own fabs and their entire production strategies, has significantly declined or, in some cases, disappeared completely. This is part and parcel of a profound structural change taking place across the industry.

Meanwhile, competition has been increasing continuously. Too many suppliers are chasing the market, with the result that margins and expenses—especially R&D expenses— have come under enormous pressure.

With chip makers losing a fundamental element of differentiation against a backdrop of unrelenting margin pressure and competition, it is clear that a new set of rules will soon define the business—rules favoring chip companies that can boast superior product-development efficiencies and capabilities.

Running the numbers

Let’s look at just how enormous the pressure is. Let’s say the investment necessary to build a system-on-chip (SoC) is $50M, a common figure these days. Companies generally target at least a 10X return on such an investment, so in this case, that $50M investment needs to yield at least $500M in revenue. Let’s assume that the company captures a third of the market. That means the company needs to target a sector that has $1.5B in total potential revenue to realize its ROI goal. There are not that many markets of this size.

Such financial goals inevitably mean there will be fewer chip startups. Those that are startups require $40M to $100M in funding and six to eight years just to break even.

And for companies that jump that hurdle, the last mile is the most sobering. The M&A price for semiconductor startups

has been steadily declining. In 2007, it was $160M; in 2008, it was $95M; and during the first half of 2009, the average was $65M, according to Lip-Bu Tan, chairman of Walden International, and now CEO of Cadence Design Systems.

A different perspective

A grim future? Not necessarily. The semiconductor industry has done an excellent job of creating specialized sectors with laser-focused competencies—such as foundries—that underpin a highly efficient and optimized design chain.

Companies have looked outward to help themselves differentiate, whether through IP, software, manufacturing or distribution. But with so much specialization available to so many, how do companies differentiate today? By looking inward.

Today, best-in-class companies differentiate not only through their product concepts but also through their product-development processes. They understand that missing a schedule means lost revenue opportunity and disruption across the portfolio of products chugging through the company’s R&D pipeline. In markets where one day’s delay means more than $100,000 in lost potential revenue, productivity is taking on a new and urgent meaning.

These are some of the drivers behind the business at Numetrics and at PRTM, our partner. We understand the keys to newproduct success are management skills, business processes and tools and data that foster fact-based decision making.

PRTM, a leading operational strategy consulting firm for technology companies, has developed PACE (short for ‘Product and Cycle-time Excellence’), a well-established product innovation framework that is already used successfully by a number of semiconductor companies. It has become the backbone for R&D management practices in many of these companies.

In the PACE framework, a portfolio of ‘excellence’ practices is used to manage new product ideas. Out of this portfolio come new projects that require project management best practices. Other fundamental concepts offered within PACE are based on best practices in partner management, functionality excellence and product lifecycle management (PLM).

The PACE methodology has yielded direct business benefits; as companies improve their R&D maturity, the business

EDA Tech Forum December 2009

Staffing levels are not aligned with the level of complexity a design has.

Source:

Portfolio Excellence

Opportunity Exploration Portfolio Governance Market Attack Teams Market and Technology Strategy Portfolio Management Process

New Projects

Project Excellence

Voice of the Customer Project Governance Cross Functional Core Teams Structured Development Process Decision-Makng Process

Technology, Resource, and Partner Management

New Product Ideas

Product Excellence

Idea Management Product Governance Product Line Teams Product Line Planning Lifecycle Management Process

New Products

Functional Excellence

Organization and Skills Functional Procedures, Standards, and Tools Performance Measurement PLM Collaboration Practices PLM Systems and Infrastructure

FIGURE 1 PRTM integrated framework of product development capabilities sees measurable results. While PACE practices are an essential foundation, success requires additional product development capabilities that can be found in five best practices to boost productivity and ensure schedules are met.

1. Optimize your global R&D footprint Coordinating global teams has proven to be a daunting task, but it is a critical requirement for successful semiconductor product development. Leveraging a global R&D resource footprint requires the active management of: • business requirements; • R&D performance; • site data; and • decision-making reviews.

2. Use leading indicators for better decision making Leading indicators such as budget variance, program risk, schedule variance and test coverage identify downstream issues, giving R&D managers timely information to make decisions.

3. Extend the enterprise Establishing deep partnerships not only takes advantage of companies’ specializations, it extends the enterprise and distinguishes R&D leaders. Recognize that there are different kinds of partnerships, two of which are key: external technology insourcing and the external technology database.

• Insourcing is licensing or purchasing technology from Continued on next page

17

< COMMENTARY > DESIGN MANAGEMENT

an external organization, an arm’s-length transaction.

• The external technology database is a collaboration with an external organization—a joint venture or co-development—where technology flows from an established relationship. It is much closer than an arm’s-length transaction. This allows companies to target not only their current market but pursue licensing in the partner’s market and spin off businesses for new markets.

4. Fact-based project planning Part of the reason so many semiconductor projects miss a deadline is that staffing levels are not aligned with the level of complexity that the design team needs to undertake. Factbased planning provides the team with data for decision making—ensuring that projects are staffed properly to meet the demands of the design’s complexity. Estimates of design complexity, project-staffing requirements and development cycleSource: PRTM/Numetrics

60% of IC projects slip by at least one quarter 16% of IC projects slip by more than one year

Desired zone

More

Schedule Slip (Weeks)

100

90

80

70

60

50

40

30

20

10

5

0

-10

-25

% of projects

Solution: Resolve mismatch between staffing levels and design complexity Schedule predictability is a critical for project excellence

FIGURE 2 Schedule slips in the semiconductor industry Source: Numetrics

2k Development Productivity Complexity Units per Person-Week

18

Projects using NMX Planner Projects not using NMX Planner

1.6k Number of IC Projects 129

1.2k

800

400

0 10

18

26

34

42

50

Team Size No. of Full Time Equivalents (FTEs) in Peak Phase Projects Planned using NMX exhibit 38% lower cost due to higher Development Productivity

FIGURE 3 Development cost/productivity: impact of Numetrics

80

page 19 Intel_14

intelligent, connected devices.

Choose your architecture wisely.

15 billion connected devices by 2015.* How many will be yours? intel.com/embedded * Gantz, John. The Embedded Internet: Methodology and Findings, IDC, January 2009.

Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. 2009 Intel Corporation. All rights reserved.

Š

20

< COMMENTARY > STANDARDS

time are generated using empirically calibrated models. This is at the heart of what Numetrics offers. Fact-based planning: • eases the traditional tension between groups within the enterprise that struggle to communicate in different languages by guiding discussions and strategy with facts and data; • enables predictable revenue streams because it yields accurate schedule estimates, therefore there are no surprise shortfalls in revenue or margins; • leads to predictable schedules, is crucial in an era when time-to-market is more important than ever, and companies cannot afford to miss the market upturn; and • does not replace bottom-up detail planning but complements it.

5. See the pipeline clearly; manage it centrally This best practice—and the tool behind it—rolls up all project plans to generate a picture that shows the total resources they consume. With this bird’s-eye view, engineering managers can observe where there are shortfalls and over-subscriptions role-by-role, month-by-month. This becomes an essential tool for managing the pipeline.

Conclusion

Many factors boost productivity in product-development organizations, such as improved tools, flows, methodologies and design technologies. The real name of the game,

EDA Tech Forum December 2009

though, is to leverage the human factor. How do you get the most out of your people?

You leverage the human factor by giving people better tools, but also by motivating them to be extremely efficient.

Engineers will tune out if they think a project schedule is unreasonable or based on false assumptions. But they will be extremely productive if they are given a highly aggressive—but achievable—schedule, one that is based in fact.

In short, it takes a behavioral approach, giving engineers viable project plans.

Distilled to their essence, we think the approaches promoted by Numetrics and PRTM are powerful, productionproven mechanisms for improving productivity. Applying these methods and tools is how ‘also-rans’ become best-inclass in the ever-changing semiconductor industry.

Ronald Collett is a 25-year veteran of the semiconductor industry, where he has held positions in executive management, engineering, marketing and sales. He founded Numetrics in 2000. Find out more at www.numetrics.com.

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< TECH FORUM > EMBEDDED

Rapid prototyping for MCUs Simon Ford, ARM Simon Ford is the mbed Product Manager, and one of the originators of the mbed project. Having started it as a skunk-works project with a colleague, he has led development of mbed through R&D to prototype.

Prior to his work on mbed, He has worked on various ARM R&D projects and was Technical Lead for the ARMv7/NEON architecture.

Microcontrollers (MCUs) are getting smaller, becoming more powerful, consuming less energy, and adding more connectivity, yet the prices keep falling. All this progress potentially opens up huge opportunities in markets where MCUs were not previously seen as an option.

The keys to exploiting those opportunities will be the tools available to help identify new applications and then build from proof-of-concept prototypes through to highly profitable products. This sounds easy enough. But while we have excellent tools for productizing MCU designs where the target is known from the get-go, even experienced engineers often find it too risky or time-consuming to try to prove a concept or define a specification from the ground up.

The result is that new ideas do not get explored and there is little iteration or design space exploration so that the prototype becomes the final design with a specification that is overly cautious. Given that in many cases other observations and insights that would help define and enhance these applications would be coming from engineers in other problem domains, these limitations are amplified.

It is partly in response to this problem that microprocessor specialist ARM and semiconductor group NXP have launched mbed, a rapid prototyping service aimed at allowing engineers to uncover new market opportunities in a timely and cost-effective manner.

Strategy

The underlying goal of mbed is to enable the efficient evaluation of 32-bit MCU capabilities and prototyping for various applications to which they might be applied. Doing this efficiently is achieved via a strategy that works through technologies and trade-offs that can optimize the time to get to a working prototype rather than immediately plunging into the complexity of optimizing the design itself.

For example, the trend in microcontrollers is toward increasing performance and memory capacity for a fixed price. While most tools focus on enabling users to exploit

Source: ARM/NXP

Design Capability Others mbed

Design Challenge

FIGURE 1 The mbed strategy this in the end capability of the applications that can be created, mbed instead focuses on using this performance and capacity to reduce the design challenge (Figure 1). A good example is the use of high-level abstractions to make the functionality accessible at the cost of implementation efficiency and increased code size.

Another key objective is to overcome barriers to entry. As defined by Fred Davis and Richard Bagozzi, the Technology Acceptance Model (Figure 2) provides a clear framework to achieve this, highlighting concepts such as ‘perceived usefulness’ and ‘ease of use’.

Perceived usefulness was defined by Davis as “the degree to which a person believes that using a particular system would enhance his or her job performance.” It is driven by insights into a technology, gained through experimentation and education. In this context, the mbed prototyping approach naturally supports user exploration, while making it easy for both marketing and application engineering professionals to demonstrate and showcase the technology.

Davis defined ease of use as “the degree to which a person believes that using a particular system would be free from effort.” As a result, this concept is very dependent on context: most good tools are easy to use for the task they were intended. But for a different task, the results are unlikely to be the same. By defining clearly the context of rapid prototyping, it becomes much more meaningful to make design trade-offs focused on notions of ease of use.

Remember, any MCU developer in the industry is likely

EDA Tech Forum December 2009

The increasing capability and performance of microcontrollers suggests that they can now reach markets for which they were never previously envisioned, particularly as 32-bit devices move into the mainstream.

to be familiar with an existing proprietary architecture and tool chain, and change can appear daunting. Simply making an engineer feel as though he is about to go from ‘expert’ to ‘learner’ can be enough to make him avoid exploring the benefits of moving to a modern solution. For a new user, the fear, uncertainty and doubt can be equally prohibitive.

This makes the user’s initial experience with the tools critical. They must deliver sound results quickly and with little investment or difficulty.

Source: Davis et al., 89

Perceived Usefulness Behavioral Intention to Use

Actual System Use

Perceived Ease of Use

FIGURE 2 Technology acceptance

Getting started

Consequently, an important objective in mbed’s development was that a new user should be able to run a first program as quickly as possible, thus building confidence and trust in the hardware and software tool chain. The mbed tools have applied some novel technology to achieve this, and the results speak for themselves; you can get started in 60 seconds.

Two innovations fuel this rapid execution time: the presence of a USB drive-based programmer on the hardware, and access to compiler tools as cloud-computing-based applications that run in a Web browser. These solutions have some obvious benefits, but also some that might not be immediately apparent. Let’s consider the first group.

1. There is nothing to set up or install. At the most basic level, this offers instant access without any administrative duties. However, for those using locked-down computer systems (as found in many colleges, universities and offices), this feature could make the difference between being able to test out an MCU and not.

However, prototyping and even researching new application spaces is difficult with existing tools. These are highly optimized for existing uses, but as such very unwieldy when used to explore new ones.

In response, ARM and NXP have developed mbed, an online/USB-based rapid prototyping technology. Its features and use are described in the article, and some illustration of how it can be used to get an initial take on a potential new market is provided.

2. The IDE is simple but functional, and briskly gets on with the job of editing and compiling code. Everything is preconfigured so that it will work out-of-the-box on any platform—PC, Mac or Linux. Users can have confidence that the tools will be there, ready to use whenever they need them or to run a demonstration.

3. The online cloud computing features mean that you can access your workspace from anywhere and on any machine. You no longer need to manage and synchronize multiple installations if, as is increasingly the case, you work from several different computers. So, an engineer or student may resume his work at home picking up from exactly where he was at work or university. An obvious analogy here is how we already taken universal webmail access for granted.

But what about those more subtle advantages?

1. There are the decisions you don’t have to make, because the options and configurations that will give the most appropriate results for the task have been identified already.

2. The tools are so lightweight that you can login from any machine, create a project from scratch and run tests in a matter of minutes, or approach any modifications in the same way. Such flexibility can have a significant impact on working style. Having a simplified setup means everything is easily reproduced.

3. Combined with the single hardware and library model, every other mbed developer works in an identical environment. That makes community support much easier, as people can share problems and questions within a common context.

Continued on next page

23

24

< TECH FORUM > EMBEDDED

Source: ARM/NXP

GND

0v

3.3 v Regulated Out

VOUT

VIN

4.5v - 9.0v In

5.0v USB Out

VU

VB

IF -

nR

IF +

p5 p6 p7

RD -

mosi miso SPI sck

Ethernet

TD -

p8 p9 p10

TD + tx rx

Serial

p11 p12 p13 p14

tx rx

sda scl

I2C

D-

USB

mosi miso SPI sck

CAN I2C

Serial

sda scl

Serial

D+

rd td

p30

tx rx

p28

p15 p16 p17

RD +

PwmOut

AnalogIn

p18

p29 p27 p26 p25 p24 p23

AnalogOut

p19

p22

p20

p21

FIGURE 3 The mbed microcontroller pinout

Rapid prototyping

The mbed MCU hardware packages an NXP LPC1768 device, support components and smart USB interface in a practical 40-pin 0.1” pitch DIP form factor, ideal for experiments involving solderless breadboard, stripboard and through-hole PCBs. To support the exposed interfaces, an mbed C/C++ library provides high-level interfaces to MCU peripherals, enabling a compact, API-driven approach to coding. The combination gives immediate connectivity to peripherals and modules for prototyping and subsequent iterations of MCU-based system designs. Figure 3 shows the basic mbed pinout, including the availability and location of the interface resources.

The interfaces indicated match those found in the mbed Library (Table 1, p.24). This highlights some of the key benefits of their being developed together. The API provides an abstract peripheral interface, rather than one that is implementation specific. The libraries use object orientation that maps well to tangible physical hardware resources.

The hardware, libraries and documentation share the same naming and concepts for interfaces.

The alignment between hardware and software is meant to enable a natural programming style that captures intent, essential for fast experiments and iteration. For example, mbed avoids requiring the multiple levels of indirection

that are usually needed for pinout and resource allocation.

These tend to lose meaning and introduce bugs.

The following example demonstrates how you could set up an SPI master interface: #include “mbed.h” SPI myspi(p5, p6, p7); // mosi, miso, sclk int main() { // Setup 9-bit SPI @ 1MHz myspi.frequency(1000000); myspi.format(9); int response = myspi.write(0x8F); }

First, an SPI object has been created and tied to the desired pins (‘mosi’, ‘miso’, and ‘sclk’) as seen in Figure 3.

Notice that this expression could be equally useful when it comes to physically wiring up the device—the specification has captured the physical connectivity.

Next, the frequency and bit format of the SPI object (myspi) has been configured, before performing a write/read transaction.

The methods on the SPI object are well defined, making the interface intuitive, and the operations are independent of the low-

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< TECH FORUM > EMBEDDED

Source: ARM/NXP

Custom Application Code

mbed Community Peripheral Libraries HTTPClient, USBMouse, GraphicsLCD, Accelerometer, EEPROM, RFID, ...

mbed Library DigitalIn, DigitalOut, InterruptIn AnalogIn, AnalogOut, PwmOut Serial, SPI, 12C, CAN, Ethernet Ticker, Timer, Timeout

Custom CMSIS Peripheral Code

CMSIS

ARM Cortex-M Microcontroller

FIGURE 4 The mbed Library architecture

Source: ARM/NXP

Interface

Function

DigitalIn DigitalOut DigitalInOut InterruptIn

Read the state of a digital input pin Write the state of a digital output pin Read and write a bi-directional digital pin Trigger a function on a pin rising/ falling edge

AnalogIn AnalogOut PwmOut

Read the voltage on an analog input pin Control the voltage on an analog output pin Control a pulse-width modulation output pin

Serial SPI 12C CAN Ethernet

Communicate with serial (UART) devices Communicate with SPI slave devices Communicate with 12C slave devices Communicate on a CAN bus Read and write Ethernet packets

Timer Ticker Timeout

A general purpose timer Call a function at a recurring interval Call a function at a point in the future

TABLE 1 The mbed Library interfaces

level settings or requirements of the underlying hardware. In fact, to change the SPI port being used in this example, only the pin names would need to be changed. This helps separate modification of the physical aspects of a design (the resources used and how they are pinned out) from the control (what they do).

Here is a similar example where we have captured intent: #include â&#x20AC;&#x153;mbed.hâ&#x20AC;?

InterruptIn button(p5); DigitalOut led(LED1); void flip() { led = !led; } int main() { button.rise(&flip); // attach flip to p5 edge while(1); // hang around forever }

In this case, a function is set up to be called every time a rising edge interrupt occurs on a digital input pin. Interrupts are a simple concept, but are notoriously complex to set up and get functioning correctly.

With mbed, the code is conceptually very simple; create a pin that can generate interrupts, and attach a function to the rising edge of that pin. The library is built using these

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< TECH FORUM > EMBEDDED

approaches throughout, allowing developers to concentrate on application logic rather than implementation details.

The mbed Library is built on top of the low-level ARM Cortex Microcontroller Software Interface Standard (CMSIS), a vendor-independent hardware abstraction layer for the Cortex-M processor series (Figure 4).

In contrast to CMSIS, the mbed Library provides a very high-level API, focused on providing abstract interfaces for the basic control of peripherals. This structure provides a natural way for users to benefit from the mbed Library wherever they can, while allowing them to add bespoke code built on CMSIS where they need to support functionality not provided. In particular, this allows the user to concentrate effort on the critical or differentiated aspects of a prototype. In addition to the mbed Library, the mbed Community peripheral libraries provide an expanding base of contributed code for controlling peripherals that can be connected to the MCU (e.g., sensors, actuators, LCDs, etc.). These are usually built on top of the mbed Library, and enable systems to be connected quickly, focusing on the logic and functionality rather than the drivers. Anyone in the mbed community can contribute to these libraries, and will be expanded with middleware from third-party vendors over time.

Application example

To demonstrate how easily a simple experiment can be realized with mbed, the following example shows a hardware device that is controlled by an Internet database. The program implements a system that displays a message on a screen and moves a servo motor based on the result of the HTTP request. #include “mbed.h”

Tools must deliver sound results quickly and with little investment or difficulty.

fundamental concept. The prototype may enable iteration of hardware, early development of the Internet application, exploration of new markets, or provide the case for committing to a project. By enabling an accessible way to test ideas, mbed helps reduce the risk associated with product development, and gets advanced MCUs designed into more applications more often.

Conclusion

Its focus on rapid prototyping gives mbed a broad appeal.

For engineers new to target applications, mbed will enable them to experiment and test product ideas for the first time.

For experienced engineers, mbed provides a way to be more productive in the proof-of-concept stages of development.

And for marketing, distributors and application engineers, mbed provides a consistent platform for the demonstration, evaluation and support of MCUs. As a result, the mbed tools will help a diverse audience exploit the opportunities presented by advanced microcontrollers like the NXP LPC1768.

#include “HTTPClient.h” #include “MobileLCD.h” MobileLCD lcd(p5, p7, p8, p9); // SPI LCD HTTPClient http; // Ethernet client PwmOut servo(p21); // R/C Servo int main() { servo.period(0.020); // 20ms servo period char result[128]; while(1) { http.get(“http://a.com/stat.php”, result); lcd.printf(“The status is %s\n”, result); // position the servo, 1-2ms pulsewidth float percent = atof(result); servo.pulsewidth(0.001 + 0.001 * percent);

}

}

wait(60); // update every minute

The solution is unlikely to be optimal, robust or complete, but what matters is that it is enough to prove the

ARM 110 Fulbourn Road Cambridge CB1 9NJ UK T: (44) 01223 400400 W: www.arm.com

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< TECH FORUM > ESL/SYSTEMC

Overcoming the limitations of data introspection for SystemC Christian Genz & Rolf Drechsler, University of Bremen Source: University of Bremen

Christian Genz is a PhD student at the University of Bremen, where he also received his Diploma in computer science in 2006. His primary research interests are SystemC design analysis and synthesis, and design visualization.

Verification Dr Rolf Drechsler is a full professor of computer architecture at the University of Bremen. He has authored more than 10 books on VLSI CAD and published more than 250 papers. His research interests include verification, test, and synthesis.

Synthesis

Meta Data

Debugging

Visualization

1. Introduction

The system description language, SystemC, is now widely accepted for use during hardware/software (HW/SW) co-design and has been approved as a standard by the IEEE consortium. In complementing hardware description languages (HDLs), it furnishes system architects with concepts and techniques—such as object orientation—that were previously only available in software programming languages. Armed with these qualities, SystemC can help drastically shorten project development time by allowing multiple phases to be parallelized, such as test suite generation, synthesis, application programming and the authoring of driver software.

One way in which SystemC architects achieve major gains in productivity is through the use of features it makes available in C++. Such features include polymorphism to support the clever reuse of existing algorithms and data structures, as well as the insertion of arbitrary software libraries within HW/SW co-design prototypes. In addition, many levels of design abstraction are supported, allowing the description of cycle-accurate hardware structures as well as untimed software algorithms.

The power and the flexibility of the language underpin its greatest benefits, but these attributes can also have a vast impact on the complexity of SystemC design analysis. Figure 1 shows the application of metadata within the context of such applications as synthesis, verification, debug and visualization.

SystemC supports the extraction of metadata by using the kernel interface at run time. Additionally, the Open SystemC Initiative (OSCI) introduced the SystemC Veri-

FIGURE 1 Figure 1. Applications for analysis fication Library (SCV) in December 2002 and this added data introspection to the language’s analysis capabilities.

While data introspection uses run-time information to assemble the metadata for a given model, the metadata itself will suffer from information being lost during the compilation process. We have developed a tool that seeks to overcome such limitations and ensure that key principles are maintained as the metadata is generated. Specifically, we secure the following: • The circuit behavior—that is the operational semantics of the analyzed SystemC program—shall be described in metadata.

• Not only SystemC data types but arbitrary data types like user-defined types will appear in analysis results.

Without a knowledge of inheritance and member types inside classes, any observed design hierarchy will be incomplete.

• All names of declarations (as variables, data types and functions) shall be known after analysis. Otherwise, the names of ports, modules and signals will not be stored in the metadata or may be ambiguously identified using internal SystemC names (‘sc_object’).

Our approach is fully non-intrusive. No modifications occur to either the SystemC library that is needed for elaboration, or the compiler. We do not alter the behavior nor the architecture of the SystemC model. As a result, the proposed methodology is suited to dynamic models whose growth when running may not be foreseeable. This is an important

EDA Tech Forum December 2009 The verification, test and debug of SystemC models can be undertaken at an early stage in the design process. To support these techniques, the SystemC Verification Library uses a concept called data introspection. It lets a library routine extract information from SystemC compound types, or a user-specified composite that is derived from a SystemC type. Unfortunately, data introspection has some limitations, especially when the number of language features applied is on the increase. For example, native C++ data types will not appear in metadata extracted by introspection.

feature since SoC designs tend to contain software partitions that have this characteristic.

2. State extraction

To obtain the kind of complete hierarchy identified as necessary in Section 1, our approach distinguishes between model hierarchies of two different kinds. The first is static and can be derived by parsing. The second is dynamic and has to be examined using run-time information.

To derive the dynamic hierarchy, we extract the start state, a part of each valid SystemC model that can be simu-

This paper describes a non-intrusive analysis technique that aims to overcome the drawbacks with existing data introspection. It is a hybrid technique based on joining a parser that collects static information with a code generator that evaluates run-time information. holds the static architecture of the input program. The parser and an additional scanner have been developed for this application and support special features, such as cross probing. Both tools have been implemented using the Purdue Compiler Compiler Tool Set (PCCTS) [3].

The parse tree is also called an ‘Abstract Syntax Tree’ (AST) and is used for communication within and across different phases. However, since our elaboration only takes SystemC programs as input, we implemented the inverse function of Source: University of Bremen

SystemCModel

AST

Syntactical-Analysis

AST AST Reflection Library Instrumentation

SystemCModel

AST-Synthesis

AST SystemCModel

gcc

Binary

AST

System State

Elaboration

SystemCModel

AST

AST-Synthesis

FIGURE 2 Architecture of the approach lated. The observed system state is defined by a concrete set of values for all variables, declared in the program.

These variables again define the state space of the respective model at the beginning of a simulation when the function sc_start is called.

Architecture As shown in Figure 2, the extraction methodology is partitioned into four phases. First, syntactical analysis derives a given SystemC program and generates a parse tree that

the parser. The AST-synthesis generates a SystemC program from its parse tree to establish communication between the instrumentation and the elaboration.

So that we get the result of a model’s elaboration in the form of an AST, that model must be annotated beforehand. Then, the set of automatically generated functions that have been annotated on the model to implement our elaboration. The generation of those functions is realized by the instrumentation.

Continued on next page

31

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< TECH FORUM > ESL/SYSTEMC

The outcome of the state extraction is to unroll all the generic nodes inside the AST; that is, to derive concrete values from all the expressions. Compared with standard SystemC data introspection, our technique expands the AST that has previously been computed by the parser, instead of only storing values of variables in the structures of the kernel.

AST-Synthesis The AST is represented by an acyclic graph. Consisting of six different node types, it offers a way of expressing any arbitrary combination of control flow operation and data dependency. And because all the declarations that are alSource: University of Bremen

SystemCModel

Static Analysis

Instrumented SystemC-Model

gcc

Analysis of Source-Code

gcc

Dynamic Analysis

Elaborated AST

FIGURE 3 Hybrid analysis lowed in C++ can be represented within the AST too, the state spaces can also be represented in an AST graph.

While the semantic of the program is directly transferred to the AST, each manipulation of the AST will have an influence on the corresponding SystemC document that is a result of the AST-synthesis. Thus, each operation in the program can be captured during run-time by just adding an additional statement to the AST. The synthesis of the AST is much less complex than the syntactical analysis. While the analysis frequently faces difficulties with ambiguities that arise when it is deriving a parse tree, the generation of a program from its AST is unambiguous.

To be able to support the cross probing facilities as described above, tokens forming the AST integrate additional information besides line numbers, such as byte positions.

Using this information, the generated code of the AST-synthesis is written to files that use the same names as the input files of the syntactical analysis.

Instrumentation The instrumentation of the source code is realized via the generation of a set of functions. These functions will be executed in a binary compiled from the output files of the ASTsynthesis. They are called ‘recorder functions’ and each records a state variable after a change in its value. Therefore,

the recorder function stores each modified value in the AST of the corresponding variable during elaboration.

All user-defined data types are compounds of primitive types (e.g., ‘int’) and pointers. Hence, only entities that are declared as native types or pointers are going to be recorded when their values change. To store value changes of variables and avoid any unwanted impacts on the AST, the propagation of the value changes must happen directly after computing the respective expression but before adjacent expressions are elaborated.

In cases where the stack frame changes during elaboration (e.g., when passing function calls, statement blocks or overloaded operators), the stack frame of the corresponding AST has to change. Consequently, more recorder functions have to be generated to enlarge or shrink the respective AST when entering or leaving a statement block.

To be able to expand the AST of a SystemC program during run-time, an inclusion directive is generated inside the AST that includes the source code or our parser. Additionally, the AST is extended by a sequence of instructions that causes the static (syntactical) analysis of the model during elaboration. So before elaboration starts, an exact copy of the AST that was also used as input during the instrumentation phase is handed over to the simulator. A simplified representation of the combination of static and dynamic analysis with the help of instrumentation can be seen in Figure 3.

State elaboration Instead of elaboration by pure interpretation, as has been done in similar research [2], our approach follows a hybrid strategy. After static analysis has finished, a simulated analysis takes place for the purpose of elaboration. This allows you to elaborate expressions, without knowing the respective source code. This is important when system calls are used or when a program is linked to external libraries, both common techniques in system design.

However, the state elaboration—and by extension the state space extraction—is limited to variables and functions that are declared inside the analyzed model. Other declarations (e.g., identifiers that have been declared in an external library exclusively) do not appear in the resulting AST. Only known entities that occur in the AST can be annotated with recorder functions. Finally, only nodes that are attached to recorder functions can be expanded to values.

All the values of the elaborated state variables are written to the AST automatically because the instrumentation code for those variables is compiled automatically too. Hence after elaboration, the AST becomes a tree whose leaves will reflect one of the following: • constant values; • state variables; • undefined functions; or • undefined variables.

Continued on next page

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< TECH FORUM > ESL/SYSTEMC

Source: University of Bremen

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

struct Euclid : public sc_module { sc_in<unsigned int> portA; sc_in<unsigned int> portB; sc_out<unsigned int> portC; unsigned int valA; unsigned int valB; void calc () { valA = portA.read(); valB = portB.read(); while (valA & valB) max (valA, valB) -= min (valA, valB); }

portC.write (valA);

SC_CTOR (Euclid) { SC_METHOD(calc); Sensitive << portA <<portB; } };

FIGURE 4 Euclidean algorithm

Consequently, all control and data operations of the AST are placed between the root and the leaves. Variables that describe the state space can be traversed in depth after elaboration to then be extracted.

been shown, as well as the need for a combination of static and dynamic strategies.

Future work in this area will concentrate on extending this approach with syntactical control mechanisms for the instruction phase. By doing this, we will be able to apply arbitrary modifications to different models in an automatic way that is less error prone and time-consuming than the manual insertion of macros to insert additional operations into SystemC models.

References [1] F. Rogin, C. Genz, R. Drechsler, and S. Rülke, “An Integrated SystemC Debugging Environment,” Embedded Systems Specification and Design Languages: Selected contributions from FDL’07, E. Villar, Ed. Springer-Verlag, 2008, pp. 59–71.

[2] C. Genz, R. Drechsler, G. Angst, and L. Linhard, “Visualization of SystemC Designs,” IEEE International Symposium on Circuits and Systems, 2007, pp. 413–416.

[3] T. Parr, Language Translation using PCCTS and C++: A Reference Guide, 1997, Automata Publishing Company.

Acknowledgments

This work was supported in part by the German Federal Ministry of Education and Research (BMBF) and by Concept Engineering, Freiburg, Germany within Project Herkules.

3. Example

We applied the implementation to various SystemC models.

One specifically computed the Euclidean algorithm within a combinational process (Figure 4).

Only the ports were declared using SystemC types here.

The computation itself was done on two integer variables.

The loop that calculated the greatest common devisor (line 13) was not a SystemC construct. Also, note that the functions min/max were user-defined. Thus, the interface of the module was clear to SCV. But considering the behavior, data introspection could only observe a black box without manual annotations.

After parsing, our approach considered valA and valB as part of the architecture. During elaboration, the attached SystemC applications were not only aware of the changing values of signals, but also had a direct knowledge of the control sequence that caused any of those changes.

4. Summary

This paper has described an analysis strategy for the extension of SystemC models with non-intrusive reflection capabilities. Our approach facilitates the state extraction of SystemC programs without being limited with regard to the abstraction level of the model. Advantages over pure simulative or statical analysis techniques such as [1] & [2] have

The University of Bremen Bibliothekstrasse 1 D-28359 Bremen Germany T: +49 421 218-63932 W: www.uni-bremen.de

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< TECH FORUM > VERIFIED RTL TO GATES

Power management in OCP-IP 3.0 Christophe Vatinel, Texas Instruments Christophe Vatinel is a system-on-chip architect at Texas Instruments France. He has 18 years of experience in the ASIC, embedded processor and system-on-chip fields and joined TI in 2004. He holds MS degrees in computer science and in microelectronics from The Ecole Polytechnique and from Télécom ParisTech, France.

A typical system-on-chip (SoC) can be partitioned into several domains that will be more or less independently managed with respect to power consumption. Several techniques may be used such as lowering the clock frequency, lowering the voltage, gating the clock, entering a retention mode or completely powering down the device. This list is not exhaustive and a full review of power management techniques is not our purpose here. However, one must realize that with some of these techniques, the affected components are not responsive to any input. At most, signals from such components can be forced to a predefined value using a clamp technique, and these enforced states will be referred to as ‘sleep’ states for the rest of this article.

The Open Core Protocol (OCP) defines a point-to-point fully synchronous unidirectional interface protocol that can be used as an internal communication method. The protocol is pipelined, with transfers made up of three phases: request, data and response. It supports multiple transaction types from single access to 2D burst, including Source: Texas Instruments

D1

D2 Master 1

Master 2 OCP Bridge OCP SoC Interconnect

D3

D4

OCP

OCP

OCP

OCP

OCP

Slave 1

Slave 2

Slave 3

Slave 4

Slave 5

D5

FIGURE 1 Simplified SoC architecture

support for threads and tags. Its main attribute is its high configurability, OCP being both modular and scalable. A further important aspect to note is that the protocol does not support retraction: a request phase cannot be aborted.

Figure 1 shows a simple SoC that uses OCP for the interconnect. It includes several domains. D1 and D2 are labeled as master domains as they include at least one master OCP interface at the boundary. D4 and D5 are labeled as slave domains as they include at least one slave OCP interface at the boundary. D3 is both a slave and a master domain according to the previous definitions. An OCP-toOCP bridge is also shown. Its purpose is to adjust different clocking rates or different socket characteristics between a master domain and a slave. The bridge can be fully synchronous or asynchronous, and can include internal FIFOs to temporarily store transactions.

Putting a domain to sleep

Before putting a domain into a sleep state, all OCP transactions that cross the domain boundaries must have been completed. If this is not the case, various problems can arise.

For example, if a domain starts being put into sleep with outstanding transactions at its boundary, the corresponding communicating entities will likely become stuck or corrupted. Such disorders may then propagate via the interconnect throughout the entire SoC. There is no easy way by which to recover from either of these scenarios, if at all.

Intuition suggests that software could be used to guarantee that such a necessary condition is fulfilled before the sleep transition is performed. However, software-based transaction monitoring is extremely difficult—if not impossible—in complex SoCs that have both multiple masters and a complex interconnect. Moreover, some masters operate in such a way as to be, in effect, totally independent of software, an example being a debug master IP.

Bridging

To determine the safe conditions under which to put a domain into sleep where there is a bridge involved, you need to know if that bridge is located in the master domain, the

EDA Tech Forum December 2009 According to Moore’s Law, system-on-chips (SoCs) should continually become more complex and integrate more components, enabled by each reduction in silicon technologies. However, power consumption does not follow the linear path implied here due to increasing leakage in deep sub-micron technologies. Hence, new power management techniques are needed to reduce power dissipation as much as possible.

This paper explores how to address architectural challenges seen in today’s complex SoC designs based on the Open Core Protocol (OCP) by taking advantage of such techniques. The concept of interface disconnection is introduced and the OCP disconnect protocol is described, based on its implementation described in the 3.0 release of OCP-IP. Finally, we consider several implementations in a power management framework. slave domain or split across both. The exact conditions may be hard to define, especially where a bridge is split across two domains. From an architectural point of view, it is more practical to consider the bridge and the two OCP interfaces (master and slave) as a unique OCP socket, and then apply similar conditions across them before performing a sleep transition. By this measure, one domain linked to another through an OCP-to-OCP bridge can only go to sleep if: • OCP transactions are completed on OCP interfaces with both the master and slave domains and none is outstanding; and

• the bridge is empty of transactions (here, the bridge is said to be ‘fully drained’).

Traffic toward a sleeping slave domain

Even after one domain has been properly put to sleep, a still-active master may still try to send transactions toward it. These will probably induce the same kinds of Continued on next page Source: Texas Instruments

Signal MConnect [1:0]

“Connection status”

Driven by the master

SConnect

Value

Description

‘b00 (M-OFF)

This is a disconnect state, requested by the master.

The OCP interface is cleanly stopped.

The alternate behavior is also cleanly stopped.

This is the default reset state.

‘b01 (M_WAIT)

This is a transient state.

The OCP interface is cleanly stopped.

The alternate behavior is also cleanly stopped.

‘b10 (M_DISC)

This is a disconnect state, requested solely by the slave.

The OCP interface is cleanly stopped.

The master alternate behavior is enabled.

‘b11 (M_CON)

This is only connection state.

The OCP interface is up and running. It can send transactions to the slave.

The alternate behavior is cleanly stopped.

‘b0 (S_DISC)

The slave is either requesting a disconnect sequence, or once disconnected, indicating it is unwilling to re-connect.

This is the default reset state.

‘b1 (S_CON)

The slave is indicating a readiness to perform a re-connect sequence, or maintaining a connected state.

‘b0 (S_OK)

Used to indicate to the master that transition to any new state is allowed.

This is the default reset state.

‘b1 (S_WAIT)

Used to indicate to the master that it can only transition to the M_WAIT state. That is, the slave temporarily stalls the transition at the master side.

“Slave’s vote” Driven by the slave SWait “Slave’s stall directive” Driven by the slave

TABLE 1 OCP disconnect protocol signals

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Source: Texas Instruments

Master Controller M Stall

M Vote

Upstream traffic

OCP Master Port

OCPStopReq/Ack

MConnect FSM

OCP traffic initiator

Alternate behavior

ALTStopReg/Ack

OCP

MConnect[1:0]

disorder discussed earlier. Again, you cannot rely upon avoiding this by using software. So what are your options?

The OCP disconnect protocol

Master’s core

SConnect SWait

38

FIGURE 2 Master high-level architecture

The OCP disconnect protocol aims to address these problems. It is an optional add-on in version 3.0 of the OCP-IP standard and is based on the concept of alternative ‘connection’ and ‘disconnection’ states. Connection is a state where both sides are functional and where communication can happen normally. Conversely, disconnection is a state where no communication is possible, and is instituted by a clean termination of the communication interface. Given these definitions, the disconnection state becomes a prerequisite for all OCP interfaces at a domain boundary before they are put into a sleep state. The disconnection protocol is based on the following principles: 1. The transition to connection or disconnection is performed in the master.

2. Both the master and slave ‘vote’ as to whether to enter the connection state or request disconnection.

Continued on next page Source: Texas Instruments

MConnect [1:0] = M_DISC OCPStopReq = 1 ALTStopReq = SConnect or not MVote

MConnect [1:0] = M_CON OCP StopReq = not S Connector not MVote ALTStopReq = 1 OCPStopAck and (not SConnect or not MVote)

ALTStopAck and (SConnect or not MVote) M_DISC

M_CON

MVote and SConnect and not SWait and not MStall

MVote and not SConnect and not SWait and not MStall

M_WAIT

MConnect [1:0] = M_WAIT OCP Stop Req = 1 ALT Stop Req = 1 MWAIT state can be transparent (i.e. no cycle spent) if an exit transition is true when state is entered.

not MVote and not Swait and not MStall

MVote

M_OFF Reset

FIGURE 3 Connection status FSM

MConnect[1:0] = M_OFF OCPStopReq = 1 ALTStopReq = 1

320,000,000 MILES, 380,000 SIMULATIONS AND ZERO TEST FLIGHTS LATER.

THAT’S MODEL-BASED DESIGN.

After simulating the final descent of the Mars Rovers under thousands of atmospheric disturbances, the engineering team developed and verified a fully redundant retro firing system to ensure a safe touchdown. The result—two successful autonomous landings that went exactly as simulated.

To learn more, go to mathworks.com/mbd

©2005 The MathWorks, Inc.

Accelerating the pace of engineering and science

< TECH FORUM > VERIFIED RTL TO GATES

Source: Texas Instruments

Master’s domain Master SleepReq/Ack

POWER CLOCK RESET

Master’s core Controller MStall

MVote

Upstream traffic

OCP Master Port

OCP StopReq/Arch OCP traffic initiator

MConnect FSM

Power manager

Alternate behavior

OCP

SWait

MConnect

ALTStopReq/Ack SConnect

40

Slave SleepReq/Ack Controller

POWER CLOCK RESET

OCP slave port

Slave’s core

Slave’s domain

FIGURE 4 Link with power management 3. Both the master and slave can temporarily stall the transition being performed at the master.

4. The slave’s vote and a stall directive are propagated to the master side.

5. The master generates the actual connection status and propagates it back to the slave, in agreement with both domains’ votes and any stall directives, underlining the need for a clean termination.

6. OCP transactions can be issued only by the master and only when the master is in the connection state.

7. The slave is committed to handling transactions normally while still in the connection state, independent of its own vote.

The voting mechanism allows a connection to be established only where there is mutual agreement. It is better to perform the connection or disconnection at the master side as, where an OCP-to-OCP bridge is present, this allows the emptying/idling operation for that bridge to be part of a

disconnection process. It is assumed here that the bridge understands the OCP disconnect protocol.

The master generates the actual connection status and propagates it to the slave. The slave monitors this connection status to determine when it is safe to perform a domain sleep transition. The connection status permits a disconnection state initiated solely by the slave to be distinguished from a disconnection state initiated by the master. In the case of a disconnection state initiated solely by the slave, the protocol supports an alternate behavior of the master port for new traffic intended for the disconnected slave. This alternate behavior is not in the scope of the specification, but can take various forms depending on other architectural choices (e.g., default error response, default data valid access response, wake-up on-demand). The signals used by the disconnect protocol are shown in Table 1 (p. 37).

Continued on next page

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< TECH FORUM > VERIFIED RTL TO GATES

Connection status FSM

A finite state machine (FSM) is responsible for generating the OCP connection status at the master side (Figure 2, p.

38). It controls both the OCP traffic initiator and the alternate behavior of the OCP master port, based on simple request/acknowledge full handshakes. It also interacts with the master controller that provides the connection vote and the stall directive (‘MVote’ and ‘MStall’). Finally, the FSM is connected to the slave via the interface of the OCP disconnect protocol (Figure 3, p. 38).

Linking the OCP disconnect with power management

As discussed above, the OCP disconnection state is a prerequisite for all OCP interfaces at a domain boundary if a domain sleep transition is to be performed.

Figure 4 (p. 40) shows an implementation where the global power manager has a dedicated power-management protocol with the managed entities, specifically a ‘SleepReq’/’SleepAck’ handshake.

Before transitioning a master domain into a sleep state, the following sequence must be followed.

1. The power manager sends a sleep request to the master.

2. The master controller initiates its internal shut-down sequence.

3. T he master controller votes for an OCP disconnection.

4. The connection status reaches the ‘M_OFF’ state.

5. The

master controller acknowledges the sleep request.

6. The power manager carries out the sleep transition.

Cases where an OCP-to-OCP bridge is present between the master and the slave can also be handled smoothly thanks to the OCP disconnect protocol. The latter can be conveyed through the bridge and the disconnection state can be gated by the bridge emptiness state. Furthermore, coherency properties can be satisfied between both sides of the bridge. The two OCP sockets plus the bridge are then abstracted to a single OCP socket from the power manager’s point of view; the bridge is transparent to it.

Conclusion

There is a clear trend toward the use of more and more power management techniques within SoCs. As part of this process, multiple domain partitioning presents new architectural challenges. The OCP disconnect protocol has been introduced to facilitate power management transitions at the domain level. Gating the domain sleep transition by a prior OCP disconnection state ensures that the system will remain coherent and will not experience any disorder due to the OCP interfaces.

Similarly, before performing a slave’s domain sleep transition, this sequence must be followed.

1. T he power manager sends a sleep request to the slave.

2. T he slave controller votes for an OCP disconnection.

3. The slave controller waits for an OCP disconnection state (‘M_DISC’ or ‘M_OFF’).

4. The slave controller proceeds with other internal shut down operations, if necessary.

5. The slave controller acknowledges the sleep request.

6. The power manager carries out the sleep transition.

In the same way, a sleep sequence can be defined for an interconnect IP that consists essentially of the combination of the two above use-cases because an interconnect IP is both a slave and a master. Upon a sleep request, the internal controller first disconnects all the OCP slave ports, then it drains out all remaining internal transactions. Next it disconnects all the OCP master ports, and finally it acknowledges the request.

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< TECH FORUM > DIGITAL/ANALOG IMPLEMENTATION

Interoperable PDKs accelerate analog EDA innovation Jingwen Yuan, Synopsys Jingwen Yuan is a strategic alliance manager at Synopsys where she is responsible for all marketing activities for the Interoperable Process Design Kit Libraries Alliance (IPL).

Jingwen studied for her MSEE at UC Davis after earning her BSEE from Beijing Normal University.

While digital design automation has progressed with amazing speed over the last 20 years, analog automation has lagged far behind. With RF and consumer devices demanding increased integration, the analog portion is now the gating factor for many, if not all system-on-chip (SoC) designs. This disparity exists because analog is fundamentally harder to automate than digital. During the planning stage of a SoC design, managers use the following rule of thumb for scheduling the analog content: 2% of transistors = 40% of design effort.

Much of the analog portion requires painstaking manual effort that consumes nearly half of the overall design team effort. However, while customers have the economic motivation to automate analog design, limited tools are available. The problem is further compounded by the high effort required to evaluate and then adopt analog automation tools.

This scarcity is not just a technology problem that has resulted from a lack of innovation. Even if engineers could get the tools, they would still lack the infrastructure required to support a viable ecosystem. Such an ecosystem would need several companies working together to fill every niche and competing to provide the best solution. However, before you can have a vibrant eco-system, you need a set of standards that enable interoperability. Process design kit (PDK) standards are one area that can provide substantial benefits to the custom design ecosystem.

A PDK is a comprehensive set of foundry-verified data files including parameterized layout cells (PCells) that are used in an analog and mixed-signal design flow. There has been little to no innovation in PDK technology for the past 20 years. Traditionally, PDKs were written in proprietary languages and operated on proprietary databases. Proprietary SKILL-based PDKs have limited design reuse and prevent designers from adopting best-in-class tools. With the adoption of the OpenAccess (OA) database by many large IDMs and semiconductor companies, more and more EDA vendors have introduced modern automation tools that support the OA standard to address analog design challenges. Nowadays, more designs are moving to advanced process nodes that require complex PCells, complex design flows and IP portability (Figure 1).

Source: Synopsys

Past

Future

Private databases

OpenAccess database

Single vendor centric Main stream processes and basic PCells Basic design flows

Virtuoso + Custom Designer + Laker + Titan + Others Advanced processes and complex PCells Couples design flows and IP reuse

FIGURE 1 PDK trends However, if analog designers are to take full advantage of the newer EDA tools, advanced process technology and design flows, they must have open interoperable and standardized PDKs.

Common standards

In April 2007, four EDA companies—Applied Wave Research (AWR), Ciranova, SpringSoft and Synopsys—started the Interoperable PDK Libraries (IPL) Alliance. It is an industry-wide initiative charged with establishing an interoperable custom design ecosystem. Some 18 EDA vendors and Taiwan Semiconductor Manufacturing Co. (TSMC), the largest foundry, are now members.

The alliance’s current focus is on interoperable PDKs. Members collaborate on the creation and promotion of interoperable PDK standards that work with any OA database tools. Since its inception, the IPL Alliance has released a proof-of-concept interoperable PCell library, demonstrating interoperability among tools from multiple vendors. In October 2007, IPL announced the formation of three technical working groups to advance this work in areas of particularly importance: PCells, Properties and Parameters, and Constraints. These three fields have been identified as having the potential to gain the most benefits when standards are applied. With this announcement, the IPL Alliance expanded its charter to address broader interoperability issues with foundry PDKs and design flows.

TSMC specifically joined the alliance at the 2008 Design Automation Conference (DAC), and began working with key IPL Alliance members on a TSMC 65nm interoperable PDK. At DAC 2009, TSMC announced the availability of the industry’s first in-

EDA Tech Forum December 2009

Process design kit (PDK) standards are one area that could greatly help reduce the disproportionate time and effort required to realize the analog portion of a design. PDKs have existed for two decades and provide access to foundryverified data files for such AMS design elements as parameterized layout cells (PCells). However, most have been constructed using proprietary languages and databases, and this works against easy reuse, multi-vendor tool flows and other potential efficiencies.

teroperable PDK (iPDK). The TSMC 65nm iPDK is supported by all major EDA vendors including Cadence Design Systems, Ciranova, Magma Design Automation, Mentor Graphics, SpringSoft and Synopsys. For the first time in semiconductor industry history, IC designers will be able to use the same PDKs in tools from multiple vendors and tools they have developed in-house.

An interoperable PDK benefits the entire chain of semiconductor companies, foundries and EDA vendors. Semiconductor companies can use one unified interoperable PDK to provide advanced functionality across multiple EDA vendor tools, improve design accuracy, shorten design cycle times, and promote design reuse and IP portability. These benefits improve the return on design investment. Foundries can reduce their PDK development, validation, support and distribution costs while expanding the number of tools they support. EDA vendors will also be able to reduce PDK development costs while supporting a wider range of foundry partners.

As advanced process nodes require access to complex PCells, complex design flows and IP portability, open standardized PDKs are becoming a necessity so that analog designers can take full advantage of the latest technologies. April 2007 saw the establishment of the Interoperable PDK Libraries (IPL) Alliance, an industry-wide initiative charged with establishing an interoperable custom design ecosystem.

Some 18 EDA vendors and Taiwan Semiconductor Manufacturing Co. (TSMC), the largest foundry, are now members of the alliance, and the article describes its work to date, including an already-demonstrated multi-vendor analog design flow that uses the new standards.

Without interoperable PDKs, each foundry has to create multiple tool-specific PDKs for different EDA tools. The numbers are staggering. TSMC alone developed, distributed and maintained 2,500 PDKs and technology files in 2007.

The standardization of PDKs benefits analog and custom IC designers by removing bottlenecks in multiple-vendor flows. Standardization can reduce PDK development cost and schedule, providing designers quicker access to new, advanced process technologies.

Continued on next page Source: Synopsys

Interoperable OA PDK

Cadence OA PDK

- OA Schematic Symbols - Component Description Format (CDF) - SKILL Callbacks

- OA Schematic Symbols - Interoperable Component Description Format (iCDF) - Tcl Callbacks

- SKILL PCells

- PyCells

- Spice Models

- Spice Models

- Tech Files - DRC/LVS/LPE

- Tech Files - DRC/LVS/LPE OpenAccess (SKILL)

OpenAccess, Open-standard languages (Python and Tcl) One iPDK for all EDA vendors

FIGURE 2 Proprietary OA PDK vs. interoperable OA PDK

45

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< TECH FORUM > DESIGN TO SILICON

Source: Synopsys

1 Interoperable PDK 1 OA design database No data translation 1

2 Create schematic & simulate

Schematic Driven Layout

5 PyCell Development Environment

4

3

Fix Layout, Final DRC/LVS/RCX & Simulate

RunDRC

FIGURE 3 Complete multi-vendor front-to-back analog flow

Key PDK features

schematic symbols and saved in the OA database. The schematic was opened in SpringSoft’s Laker to view the same exact circuit. The LNA circuit was then simulated using Synopsys’ HSPICE simulator. A schematic-driven layout of the circuit was created using Laker, saved in OA and re-opened by Synopsys’ Custom Designer, where some PCell parameters were changed to create intentional design rule check (DRC) violations. Mentor Graphics’ Calibre was then used for running DRC to show violations; the Laker layout was used again to fix the DRC violations.

Synopsys’ Hercules physical verification then opened the layout and ran clean DRC and layout vs. schematic (LVS) comparisons.

Synopsys’ Star-RCXT parasitic extraction was used to run extraction and back annotation to demonstrate the post layout flow.

During the complete analog front-to-back multi-vendor flow demonstration, only one TSMC 65nm iPDK was used. The design data was stored in OA and was directly read, modified and written by all tools with no translation at any point. The interoperable PCells were built using Ciranova’s PyCell Studio tool based on the open source language Python. This was a major achievement for the IPL Alliance.

For the first time in analog EDA industry, customers can take advantage of best-in-class tools from their choice of vendors.

Analog design has been characterized as ‘black magic’ because of its comparative difficulty and complexity. Much of the work is still done with less automation compared to digital design. Using iPDK standards as the building block for analog design will enable design reuse, improve design productivity and ultimately promote innovation in analog and full custom EDA.

Multi-vendor flow

Synopsys 700 East Middlefield Rd Building C Mountain View CA 94043

The iPDKs (Figure 2, p. 45) are based on the OA standard and use standard languages such as Tcl and Python to ensure interoperability among all EDA vendor tools. These iPDKs include a comprehensive set of APIs to enable customization, support advanced PDK features and provide an interactive environment for PDK development. PCells written in Python (PyCells) not only have significantly fewer lines of codes, but also provide tremendous performance improvement compared to relative object-based (ROD) SKILL PCells.

PyCells support advanced features such as abutment, stretch handles and DFM rules. PyCell Studio from Ciranova provides an interactive development environment (IDE) for PyCell development and efficient PyCell debugging, therefore improving PCell development productivity and shortening the PDK development cycle.

Development efficiencies result in faster PDK delivery to users and allow more resources to be applied to create more device types and more device features. High-level Python APIs provide process porting capability within PDKs. There is no need to code PyCells for different processes because designers can just swap out tech files. This has great benefits for IP groups. Interoperable PDKs have all the features supported by SKILL-based OA PDKs and more. Analog designers not only get to use a single PDK for all EDA vendors’ tools, but also a better, faster PDK with more features and capabilities. Because interoperable PDKs are based on OpenAccess and only use open-standard languages, no stream-in or stream-out or any form of data translation is needed among the leading physical verification tools. This makes PDK validation easier and more efficient.

The progress of the IPL Alliance’s efforts was showcased at DAC 2009 in a jointly developed TSMC 65nm iPDK prototype used in a multi-vendor flow (Figure 3). This example illustrated how designers can take advantage of iPDKs and choose the best-in-class tools for their design flow.

A low noise amplifier (LNA) circuit was created in Synopsys’ Galaxy Custom Designer environment using standard OA

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< TECH FORUM > DESIGN TO SILICON

Making SiP happen in 3D Special Report, EDA Tech Forum Tom Quan, deputy director of design services marketing at TSMC, spoke to EDA Tech Forum editor Paul Dempsey shortly after this year’s Design Automation Conference, where TSMC released its first flow featuring system-in-package.

At the 2009 Design Automation Conference, TSMC, the largest semiconductor foundry, unveiled its latest approved design flow. For the first time since these were formally launched in 2001, Reference Flow 10 included elements specifically aimed at system-in-package (SiP), such as SiP package design, electrical analysis of package extraction, timing, signal integrity, IR drop, and thermal to physical verification of design rule checks and layout-vs.-schematic.

Multi-chip modules are nothing new. The big difference with this take on SiP, however, is that it implies the use of technologies that promote the overarching technique more clearly as an alternative to highly integrated, single silicon systems-on-chip (SoCs). Foremost among these are 3D stacking and through-silicon vias (TSVs).

Again, these technologies have been discussed and even seen in the lab in many different forms over the last five years, arguably for longer than that. For 3D stacking, the technique is already in use in the memory sector. However, until now there has been some reticence, particularly on the part of foundries, to promote their use in high-volume design. There are some good reasons for this.

TSVs are discussed in more detail below, but suffice it to say here that, as the name suggests, they involve drilling through a wafer, an idea that is enough to make even the least manufacturing-aware designer wince on first confronting it.

Similarly, the interplay between various pieces of such a system may work to compound and worsen the traditional metric that the yield of any package is the multiple of the yield percentages for each IC within it.

Tom Quan, deputy director of design services marketing at TSMC, acknowledges that there is such an emphasis on the manufacturing side of SiPs that his company’s position needs to be sufficiently confident it can deliver chips that yield in commercially viable quantities, “based not just on what we can provide, but on what comes from the entire ecosystem.”

Such is the nature of SiP that even though an error may be introduced outside the manufacturing process—indeed, the scope for this happening is substantial—the foundry could nevertheless see its credibility damaged by errors elsewhere in the chain.

At the same time, there is a SoC bottleneck that is leading some of TSMC’s larger customers to push for the availability of SiP alternatives, and Quan acknowledges that his company also sees this problem.

The SoC bottleneck

“If you are building an SoC today, there are perhaps four main types of issues that the customer faces,” says Quan. “First, there is cycle time. The bigger the design, the longer it takes— now, if you are looking at a 100M gate SoC design, you are likely to need more than a year to complete it with more than 50 engineers on your team.”

“Second, the IP [intellectual property] you need is not always available for the latest technology that you want to put the SoC on.

“Third, not all IP shrinks in the same way—it is not uniform. For example I/Os haven’t changed that much at all.

They’re pretty much the same size in 0.13um, 90, 65 or 45nm.

Analog has changed but still more slowly than the shrinks, much more slowly. And so on.”

“Fourth, all the design challenges are increasing in areas such as power density, signal integrity, design-for-manufacture [DFM] and so on.”

Source: TSMC

SoC

SiP

Single tech node

Multiple tech node

All IPs ported to same technology node

Mix of IPs in diff technology nodes

Horizontal partitioning

Horizontal & vertical partitioning

FIGURE 1 SiP opportunities

EDA Tech Forum December 2009

These are familiar issues and also stretch into concepts such as the crosstalk present when things are crammed in closer than ever before, the increasing number of layout-dependent defects and increasing power in a given area as gate density increases.

“And we see this because SoC targets one node,” says Quan. “SiP can combine things from different nodes. If your IP works well at one node then it doesn’t need to be migrated, for example. Also, you can look at integration in a different way, putting things on the vertical as well as the horizontal axis” (Figure 1).

There are a number of traditional SiP techniques—flipchip, side-by-side, stacking, wirebonding (Figure 2)—that have been in use for some time, but which also have signifiSource: TSMC

FC Side by side WB side by side Stacked WB Hybrid stack PoP stack

System-in-package (SiP) used to be thought of as a ‘poor man’s system-on-chip’ (SoC). Not any more. The complexity involved in implementing various levels of functionality on a single SoC is reaching such levels that it is becoming increasingly difficult to justify the design and manufacturing costs. Similarly, the need to deliver products within equally tight (and sometimes tighter) time budgets means that the reuse of intellectual property and proven blocks, where possible, is highly desirable. Certainly, no one wants to re-invent the wheel.

SiP itself is beginning to offer a number of techniques that provide SoC-like levels of integration and meet demands from performance through to form factor. Such techniques include stacked die and through-silicon vias.

Although talked about for some time, they are only now beginning to become more widely available from semiconductor foundries.

This special article takes the form of an interview with Tom Quan, deputy director of design services marketing at TSMC, the world’s largest foundry. The company included SiP in its Reference Flow 10, launched at this year’s Design Automation Conference. Quan discusses TSMC’s views on SiP’s market position, tools for its realization and the technical challenges, among other issues.

Stacking the die in a 3D configuration essentially gets the different parts to act together as a single IC, and this can be achieved in a number of ways, the two foremost being frontto-back and front-to-front.

Then there are opportunities for a major boost in the I/O. “It doesn’t have to be on the boundary anymore—you can connect directly in the middle of the die. If you look at SoC Continued on next page

Component Source: TSMC

FIGURE 2 Traditional SiP configurations cant limitations particularly in terms of performance (especially over the communication links between the different pieces of silicon) and size (particularly for smaller portable devices aimed at the consumer electronics space).

TSVs are electrical connections, typically copper filled, created by drilling straight through a number of wafers and then stacking these. Not only does this technique reduce the footprint, but it also greatly shortens electrical paths (certainly in comparison with wirebonding to edge-of-chip I/Os) between different parts of the SiP to boost performance (Figure 3 and Figure 4, p.48).

die2

die1

-Potential for benefits beyond traditional SiPs with advantages of SoC. -But new and different design challenges

FIGURE 3 3D stacking with TSVs

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< TECH FORUM > DESIGN TO SILICON

TSV SiP cross section

TSV Cross-section Backside metal layer Si

Top Wafer (Thin)

Through-Si Via Insulator

Bonding layer

Device Layer (top wafer) Interconnect layers (top wafer)

Device Layer (bottom wafer)

Bottom Wafer (Full thickness)

Interconnect layers (bottom wafer)

FIGURE 4 TSV SiP cross section flooplanning today it is I/O limited. Once you get up to 1,000 I/Os, the chip can result in being very big even if the core is very small, and that is about the upper limit. But with SiP, you can get to 1,000 and beyond.”

The RC of the interconnects is also thought to be lower, so that rather than having big I/O device drivers, you can use smaller standard drivers, again helping in terms of size and efficiency.

“There are some big opportunities here,” says Quan. “But there are some significant challenges.”

sign only to discover that it requires a ceramic package that would put the finished component cost beyond viability.

Consequently, silicon/package co-design is highlighted as a specific area that customers need to address within Reference Flow 10.

Then there are also some specific issues. Here are five of the most sensitive that TSMC has also incorporated in the new flow.

Static timing analysis needs inter-die timing strategies that also calculate the effect of the package to reduce margins.

Die that share power domains must take account of IR drop concerns, and the flow must be capable of analyzing dynamic effects using active die models.

Signal integrity and simultaneous switching noise across the entire package need to be simulated in detail, and require the generation of appropriate eye diagrams that again take account of the entire package.

Thermal analysis is also complicated by the fact that whereas one might previously have used the package for a single piece of silicon for heat dissipation, you now have one piece of silicon potentially sitting on top of another, so the power from Die A can raise the temperature of Die B. Finally, you need a sophisticated power-thermal analysis.

Source: TSMC

Stacking Schemes Face2Face or Face2Back Face2Face: Top-metal of two dice connected to each other and has package bump on backside Face2Back: Top-metal of first die connected to backside metal of second die and has package bump on from-side

SiP today

SiP technology has been seen in some quarters as a “SoC made easy,” although a senior executive with a Tier One semiconductor vendor says that he prefers now to see the comparison in terms of “a world of relative pain.” Earlier notions of simply putting different functional and IP elements side by side have been overtaken by the use of new technologies in the drive for performance, cost and market advantages. Quan broadly agrees that the task is not as simple as it might first appear, and highlights a number of illustrative challenges.

“The design flow is affected,” he says. “You need to have some sort of methodology that integrates chip design and package design together. Today, these two teams usually work independently and pass the basic model back and forth, with the die designer assuming some ideal package and the package designer assuming an ideal die. What you don’t have that often is a package-aware design and you really need that for SiP.” A crude example of the potential problem here would be to go through the entire process of achieving the stack de-

Die-to-die connection through top metal Backside metal

Face2Face

Face2Back Die1

Backside metal

Die2 Package substrate

Die-to-die connection through backside metal

Package substrate

FIGURE 5 Emerging SiP configurations Following on from the thermal issues, you also need to look at temperature dependent power and incorporate a statistical leakage calculation. Alternatively, the three can combine in a kind of death loop progressively influencing one another to the point that the design fails.

Continued on next page

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Quan: “SoC targets one node.

SiP can combine things from different nodes.”

that is to be used: face-to-face (F2F) or face-to-back (F2B) (Figure 5, p. 50).

F2F is where the top metal layers of two dice are connected to each other and the packaging bumps are placed on the backside metal of one of the die. F2B is where the top metal of one die is connected to the backside of the second with bumps on the front. “F2F is probably the one that you will see first because it is easier to achieve whereas F2B involves a more complex copper-to-copper bonding,” says Quan. “F2F is an incremental step.”

Making it happen “Essentially, everything that you used to do for a single chip, you have to expand it and do it to include multi-chip and the package,” says Quan. “Then the thermal is very important because that is a big change from even how SiP has been done. With everything sitting side-by-side, you could still use the package to act for heat dissipation, but once you stack them and they are a lot closer on the substrate, they will definitely affect each other. It’s a more complex chip that requires a more integrated package design flow, and an approach to co-design that figures out the die-to-die interactions.”

Having taken all these considerations into account, a designer will also have to look at the kind of 3D configuration

Untitled-15 1

“We’ve been talking about SiP for a few years, and things got very serious about three years ago,” says Quan. “Then the talk was of seeing this happen on a major scale in 2009, but it’s been pushed out and pushed out. It went to 2010, then to 2011, then to 2012. I think now that we’ll see something maybe in late 2010 but really in 2011 for 3D IC.” The issue, he says, has been demand. “It is technologically challenging, but you also need a number of clients who want to work this through.”

The same applies to TSMC’s relationships with EDA vendors and other suppliers into the Reference Flow ecosystem.

“We’re manufacturing the wafer, but we need that collaboration, especially with the EDA guys, where they make sure that design tools are 3D-aware,” says Quan.

6/1/09 3:51:19 PM

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â&#x20AC;&#x153;Right now, weâ&#x20AC;&#x2122;re working with all the major vendors and a lot of the start-ups that are coming into this space because they can see that there are new challenges to address. â&#x20AC;&#x153;Iâ&#x20AC;&#x2122;ll give you an example of the problem. With some tools when you load up the design into the system, you have to point the software to a very specific technology file and that puts you back in the world of single SoC, single chip design.

We need to make it so that you can now visualize a die on top of or underneath that. You need a schematic or a netlist to drive that. And then you can identify the connections between the two dice and perform the analysis.â&#x20AC;?

This is not a trivial task, and so vendors, like TSMC, have wanted to see that there is a market for enhancing their tools to do this. â&#x20AC;&#x153;They want to see, have to see a return on the investment. I think that now we are at the point where there is a significant number of customers who want to do this and have the resources to pay for it.â&#x20AC;?

Hence, SiPâ&#x20AC;&#x2122;s debut in Reference Flow 10. However, Quan does note that things are still at a very early stage. â&#x20AC;&#x153;If you go back to the beginning of what should be the process, somebody at the customer level has to make the high-level decision of whether to go SoC or SiPâ&#x20AC;&#x201D;or even, if they go SiP, whether to go for a newer 3D IC approach or a more traditional side-byside approach,â&#x20AC;? says Quan. â&#x20AC;&#x153;All that means that you need to know, early, the additional or comparative time, the relative cost and complexity, and the

final yields, with and without TSV. And what Iâ&#x20AC;&#x2122;ll say is that we are learning here. We have some preliminary numbers so far, and we have a customer who feels comfortable with taking things forward on this basis within the requirements of their system. And this is where we have to start. Iâ&#x20AC;&#x2122;m confident weâ&#x20AC;&#x2122;ll build from here.â&#x20AC;?

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Silicon test moves up the food chain Ron Press, Mentor Graphics Ron Press is technical marketing manager for the Mentor Graphics Silicon Test Systems Group. He has worked in the test industry for more than a decade and has patents on clock switching and reduced pin count test

The silicon test process continues to become more complicated as both integration and fabrication technologies develop and new defect mechanisms emerge. Not only must it detect subtle flaws in random logic, but it also must extend to all other major areas on the silicon, including various types of memory, clocks and high-speed I/Os. It must also encompass multiple stages in a device’s development cycle such as first silicon debug, burn-in and field test. For complex devices such as mixed-signal system-on-chips (SoCs), having to manually develop test patterns or design and insertion logic to ensure the application of high-quality tests is a daunting, and often unrealizable, task. Effective automation is vital.

Automation to date

Whenever design tasks have become too complex or time-consuming, EDA tools have been developed in response. Obvious examples include the challenges posed by schematic capture, synthesis, and place and route.

Silicon manufacturing test has already encountered many situations where complexity has made automated solutions an absolute necessity. Such instances include boundary scan, internal scan and memory built-in selftest (BIST).

Automated scan test became necessary when gate counts reached levels where it simply became too difficult to manually produce a high-quality pattern set that would detect most defects. The automated insertion of scan logic and corresponding automatic pattern test generation (ATPG) offered in commercial tools have turned scan test into standard practice. The process is now so well automated that very little knowledge of the design is needed to ensure the application of high-quality static tests.

Here are some of the areas where manufacturing test automation is today commonplace.

• Embedded test compression: This technology enables scan test pattern application up to 100 times faster than a

traditional scan pattern set with correspondingly fewer tester cycles. It permits the use of many additional pattern types for small geometries and fewer pins in the test interface without changing the properties of the tester or increasing the test time. Because of automation, the design of embedded compression logic and test pattern generation are transparent.

• Pattern generation automation: This started to require more manual settings as design complexity increased.

As various options and features were added to ATPG tools to handle various design styles, increasing expertise was needed to determine the appropriate settings.

However, almost all the settings can now be reviewed and those that will give the best results implemented as the tool starts pattern generation.

• Logic BIST: This inserts embedded logic for a completely self-contained test. It provides a fully integrated test strategy that can be used at any test step or level of integration via a very simple interface. Processes such as logic insertion, problem logic fixes and test points for high-quality test are fully automated.

• Memory BIST: This inserts and manages self-contained tests for memory arrays. As with logic BIST, the logic insertion and testability fixes are fully automated.

• Memory defect analysis and repair: Memory built-in selfrepair (BISR) automatically inserts logic for repair analysis to determine if a repair is possible and where it should occur.

New frontiers for automation

Today, the requirements and uses for test are expanding beyond random logic and memory test. The amount of clock generation and number of SerDes ports included in today’s devices adds significantly to the test burden. Consequently, BIST options for PLL jitter and SerDes ports have been added to the test automation portfolio.

Coverage analysis If test insertion and pattern generation difficulties can mostly be addressed with automated tools, there remains a need to properly analyze the results and also any missing coverage.

EDA Tech Forum December 2009 Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example.

Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies.

A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip test methodology must address logic, memory, clock generation and I/O access. You need to vary the test types and their application methods used, and also fully analyze early silicon and yield-limiting defects. These various and increasingly complex requirements make automation necessary.

The latter case is particularly challenging given huge levels of integration within a device. You can often be forced to set up multiple experiments to determine the causes of missing coverage or manually analyze a netlist to find logic that is interfering with coverage goals.

In response, automated fault analysis features have been embedded within test generation tools. Analysis and experimentation is embedded in the ATPG process so that the summary report includes specific information about systematic as well as specific locations that are limiting test coverage (Figure 1).

Yield improvement Silicon yield analysis has historically been based on basic test structure analysis and manual steps such as visual inspection. This approach can be very time-consuming, and it is tough to pick out systematic issues within what appear to be random data.

The population of defects caused by features in the silicon has grown with newer and smaller fabrication processes. Using existing scan and memory BIST results provides considerable insight into what is happening inside a failing device.

Thus, automatic yield analysis tools based on failing scan pattern data or memory BIST data are becoming available. Many aspects of the early investigation, identification of outlier issues, and processing of large amounts of production data are automatically performed and reports produced in a very short time.

EDA software contains many test types and options for use when implementing test logic or pattern types. What is still needed is the flexibility to make adjustments after silicon has been produced.

This article discusses the move to automated tools to support the test methods, flexibility and defect analysis necessary in todayâ&#x20AC;&#x2122;s mixed-signal system-on-chip production environment. to be confident that you have implemented all the tests a device really needs.

The most important questions relate to what logic should be inserted so that the production test supports the desired pattern types. No one wants to be forced into considering a design re-spin because tests needed during production were not planned for sufficiently early in the design flow.

One solution is to build in such flexibility that experiments and test adjustments can be performed in software alone. The versatility to perform various tests is provided by automated test logic insertion. Memory BIST automation now includes features that allow new algorithms to be added to account for a defect type that was not originally foreseen.

Logic included in the test structures provides a customdefined threshold that you can use to adjust the amount of scan shift activity as well as capture activity. In this way, you can tune the power impact of your tests on real silicon.

Continued on next page Source: Mentor Graphics

Post-silicon test automation

Uncertainty about production defects and the need to get as much right as early as possible are more sensitive issues than ever due to incoming fabrication processes. There is also concern surrounding the impact of test procedures on power, switching, di/dt and power droop. Project managers want production tests that operate in as much the same way as possible as functional operating power and switching. Even with the automation we have available today, it can be hard

FIGURE 1 Automated fault analysis is embedded within test generation tools

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Source: Mentor Graphics

Source: Mentor Graphics

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BurstMode Clock V DD_idle V DD_func

Power Supply

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BurstMode Clock

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V DD_idle V DD_func

BurstMode Clock

Clock Generator

USB-to-GPIB Interface

Linux Laptop with TessentTM SiliconInsightÂŽ

Performance Board USB-to-JTAG Interface

FIGURE 3 A simple bench-top platform and interface allows you to apply embedded tests and make adjustments through a direct link from USB to boundary scan on the chip 1

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V DD_idle V DD_func

FIGURE 2 A programmable sequence of fast pulses during at-speed test lets you select the number of fast cycles before launch and capture without changing the pattern A recent feature available for test logic inserted for scan control is a programmable sequence of fast pulses for use during at-speed test. This logic keeps the pattern exactly the same but lets you define the number of fast cycles before the at-speed launch and capture. As a result, if you are concerned about power droop because only two fast pulses are together, you can specify that a number of the last few shifts will also have high-speed pulses. The result is a tunable test interface.

A form of automation is also available to simplify the types of experiments mentioned above and to provide a simple platform and interface through which to apply tests and adjustments. A link from a computer USB port directly to the device-under-test (DUT) is possible without the use of a tester. The computer interface is made through the boundary scan test access port (TAP) so that you can directly set up and apply adjustments to test parameters.

You can make adjustments (e.g., which memory BIST algorithms to use, the number of high-speed shifts before at-speed launch and capture) directly to the device and immediately see the results. This interface can also be used for PLL or SerDes characterization, providing a simple platform to test and characterize PLL and SerDes in minutes instead of weeks

Test moves up the chain

Manufacturing test automation now encompasses much more than in the past. Complex requirements have driven more and more automation of the process to the extent that complete suites of tools are available to test all major areas of silicon. You can select the test methods and logic you want to use from a broad set of options. Test logic and generation have become the easy parts. But even the harder parts have been simplified by providing scope to make definable test adjustments on fabricated devices. You can experiment with memory algorithms, clocking, power and more, using a direct interface to the DUT. Production test patterns can be written based directly on these experiments.

With further automation, the expected test impact on a deviceâ&#x20AC;&#x2122;s production schedule will be greatly reduced while providing more options and significant capabilities to adjust for uncertainty in the test needs of fabricated devices.

Mentor Graphics Corporate Office 8005 SW Boeckman Rd Wilsonville OR 97070 USA T: +1 800 547 3000 W: www.mentor.com

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