Solution Manual for Analog Integrated Circuit Design, 2nd Edition, Tony Chan Carusone, David A Johns

Solution Manual for Analog Integrated Circuit Design, 2nd Edition By Tony Chan Carusone, David Johns, Kenneth Martin

Analog Integrated Circuit Design 2 nd Edition

Chapter 1 Solutions Compiled by: Kentaro Yamamoto

Analog Integrated Circuit Design 2 nd Edition

Chapter 2 Solutions Compiled by: Vadim Smolyakov Solutions contributed by: Tony Chan Carusone Yunzhi (Rocky) Dong Vadim Smolyakov Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

2.15)

Analog Integrated Circuit Design 2 nd Edition

Chapter 3 Solutions Compiled by: Vadim Smolyakov Solutions contributed by: Vadim Smolyakov Kentaro Yamamoto

Analog Integrated Circuit Design 2 nd Edition

Chapter 4 Solutions Compiled by: Dustin Dunwell Solutions contributed by: Dustin Dunwell Yunzhi (Rocky) Dong

Analog Integrated Circuit Design 2 nd Edition

Chapter 5 Solutions Compiled by: Dustin Dunwell

Analog Integrated Circuit Design 2 nd Edition

Chapter 6 Solutions Compiled by: Yunzhi (Rocky) Dong

Analog Integrated Circuit Design 2 nd Edition

Chapter 7 Solutions Compiled by: Amer Samarah

Q 7.4) Fig. 7.6, 0.35 um technology, (W/L)10-14 = 4/0.3, (W/L)15 = 16/0.3.   (W / L)13  4 / 0.3  2 1   2 1   (W / L)15  16 / 0.3  1   RB    g m13 g m13 g m13

But W  g m13  nCox   Veff 13  (190 A/V)(4 / 0.3)(0.25V)  633 A/V (*)  L 13  RB 

1  1.6k 633 A/V

Since g m13 is held constant, from (*) above it is clear that Veff13  1/   T 3/2

Hence, going from 25 to 70 degrees C, absolute temperature increases by a factor (343K ) / (298K )  1.15 or 15%. Hence, Veff 13 increases by (1.15)3/2  1.23 or 23 %. The new value of effective gate-source voltage is therefore, Veff13  1.23(0.25V)  0.308V

cont. 1/2

Analog Integrated Circuit Design 2 nd Edition

Chapter 8 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 8.1)

Q 8.2)

(cont.)

(cont.)

(cont.)

(cont.)

(cont.)

(cont.)

(cont.)

(cont.)

Q 8.3) See netlist on test website.

Q 8.4)

Eq. (8.14):

which is Eq. (8.13).

Q 8.5)

Q 8.6)

Q 8.7)

Q 8.8)

Q 8.9)

Q 8.10) Schematic:

Small-signal equivalent:

Zero-value time constants method:

Estimate 3-dB bandwidth from the sum of the zero-value time constants:

3dB 

1

 be   cb   L

Q 8.11)

(cont.)

(cont.)

Q 8.12) Small-signal schematic of the common-base amplifier (neglecting ro for simplicity):

Q 8.13)

Q 8.14) Refer to problems 8.7 and 8.8.

Q 8.15)

(cont.)

(cont.)

Q 8.16)

Q 8.17) Small-signal equivalent schematic using the T-model:

Simplifies to

Assuming Cbe

Ccb and Rc not too large, we have  p1

3dB   p1  ( Rs

 p 2 , hence

1 C 2r )( be  Ccb ) 2

Analog Integrated Circuit Design 2 nd Edition

Chapter 9 Solutions Compiled by: Yunzhi (Rocky) Dong Solutions contributed by: Yunzhi (Rocky) Dong Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 9.9)

Analog Integrated Circuit Design 2 nd Edition

Chapter 10 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Masumi Shibata Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 10.1) To ensure an error rate less than 10-12 requires the input to exceed the offset by at least 7x the input noise rms:

Vin,min = |Vin,offset| + 7Vin,rms = 10 mV + 7(0.2 mV) = 11.4 mV

Q 10.2) The input offset is the input voltage that produces 50% high and 50% low outputs. This occurs at: Vin,offset = -2mV.

The 90% confidence interval occurs at an input voltage 1.28 times the rms value from the offset. This being -0.1mV, the rms input referred noise is given by: Vin,rms = (-0.1mV + 2.0 mV)/1.28 = 1.5mV

Q 10.3)

Q 10.4)

Q 10.5)

Q 10.6)

Q 10.7)

Q 10.8)

Q 10.9)

Q 10.10)

Q 10.11)

Q 10.12)

Q 10.13)

Q 10.14)

Analog Integrated Circuit Design 2 nd Edition

Chapter 11 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 11.1) Thold = 1/(2·fclk) = 1/(2·107) s = 50 ns Droop = (Droop Rate) · Thold = (15 V/s) · 50 ns = 0.75 V

Q 11.2) The output is at the beat frequency: fout = fin – fclk = 21 MHz – 20 MHz = 1 MHz

Q 11.4)

Q 11.5)

(11.3)

Q 11.6)

Q 11.7)

Q 11.8)

Q 11.9)

Q 11.10)

Q 11.11) In hold mode, transistor Q6 is off. The equivalent small-signal half-circuit, assuming signals are fully differential, becomes:

Q 11.12)

Using equation (11.17),

Q 11.13)

Using equation (11.25),

Q 11.14)

Q 11.15)

Analog Integrated Circuit Design 2 nd Edition

Chapter 12 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Yunzhi (Rocky) Dong Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 12.1) The pictured biquad realizes the following transfer function: ( ) For a bandpass transfer function, k0 = k2 = 0 resulting in: ( )

For a center frequency of 34 MHz and Q-factor of 3, in the signal flow graph set MHz and Q=3.

34

Q 12.2)

Q 12.3)

Q 12.4)

Q 12.5) We want a lowpass transfer function k0

H (s)  s2 

0 Q

s  02

with 0  2 ·10MHz , Q  1 , and k0 / 02  5 .

Take all capacitances in the circuit to be a reasonable value; for example C  5pF . We must now find Gm1m 4 : Gm1  Gm2  0C  0.314mA/V

Gm3  0C / Q  0.314mA/V Gm 4  k 0C / 0  5Gm1m3  1.57mA/V

Q 12.6)

Q 12.7) Small-signal model, neglecting rds:

Q 12.8)

Q 12.9)

Q 12.10)

Q 12.11) From equation (12.132),

Q 12.12)

(cont.)

Q 12.13)

Q 12.14)

Q 12.15)

Q 12.16)

Q 12.17)

Q 12.18)

Q 12.19) From the signal flow graph in problem 12.18: Vout ( s) 

1 1/ R1  sC1 Vin (s)  Vout (s) / R2  sC2 

Rearranging yields: Vout ( s) R 1  R1C1s  2 Vin ( s) R1 1  R2C2 s

Q 12.20) The opamp has a frequency response A( s ) 

A0 sA 1 0

ta

Denoting the negative opamp input terminal voltage, Vx , we may write a nodal equation there as follows: Vin  Vx V V  x out R1 1/ sC1 R2 1/ sC2

Substituting in Vout   A(s)Vx  Vx  Vout / A(s) : Vin  Vout / A( s) Vout / A( s)  Vout  R1 1/ sC1 R2 1/ sC2

Using the expression for A(s) above and rearranging yields: Vout ( s) R A0 1  R1C1s 1  2 Vin ( s) R1 1  A0 1  R2C2 s 1  s / ta

Shown below are example magnitude responses for ideal (solid) and nonideal (dashed) opamps where the filter zero is at 103, the pole is at 105, A0  10 , and ta  107 . Notice the small shift in the magnitude response due to the finite A0 and the additional pole at ta .

45 40 35 30 25 20 15 10 5 0 -5 2 10

3

10

4

10

5

10

6

10

7

10

8

10

Q 12.21) We have:

Vout ( s) R 1  R1C1s . For a lowpass filter, $C_1 = 0$ resulting in  2 Vin ( s) R1 1  R2C2 s Vout ( s) R 1 .  2 Vin ( s) R1 1  R2C2 s

Taking (arbitrarily) R1  10k  : DCgain  3 

R2  R2  3R1  30k  R1

For a pole at 15 MHz, 1 1  15·106 Hz  C2   0.35pF 2 R2C2 2 R215·106

Q 12.22) The schematic is shown below, in two parts:

Q 12.23) Refer to Fig. 12.44 for the schematic. Given that we want a second-order lowpass filter with a DC gain of 2, 202

H (s)  s2 

0 Q

s  02

Equating this with equation (12.156), and taking (somewhat arbitrarily) CA  CB  10pF , C1  G2  0 (thus eliminating those components) G5  CB0  10·1012 F·2 ·1MHz  63 A/V

Analog Integrated Circuit Design 2 nd Edition

Chapter 13 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Yunzhi (Rocky) Dong Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 13.1)

Q 13.2)

Q 13.3)

Q 13.4) The signal xc(t) has frequency content at 50kHz and 150kHz. Hence, it is bandlimited to fc = 150kHz and must be sampled at least at its Nyquist rate: fs  2fc = 300 kHz

Q 13.5)

Q 13.6) The continuous-time square pulse is given by x p (t )   (t )   (t  1ms)

where  is the unit step function defined in equation (13.2).

The sampled signal is 10 consecutive samples with all other samples equalling zero. Hence, the spectrum is simply the summation of the corresponding 10 terms in equation (13.15): 9

X ( z)   z k k 0

Q 13.7) Equation (13.17):  = 2·f / fs  f = ·fs / 2 In this case:  = /10 and fs = 10 MHz. Hence, f = (/10)·(10 MHz) / 2 = 0.5 MHz

Q 13.8) Recall that if x(n)  X(z), then x(n-k)  X(z)·z-k. Hence, y(n) = x(n) + 2x(n-3)  Y(z) = X(z) + 2X(z)·z-3

Q 13.9)

Q 13.10)

Q 13.11)

Q 13.12)

Q 13.13)

Q 13.14)

Q 13.15)

Q 13.16)

Q 13.17)

Q 13.18) The transfer function of the block diagram in Fig. 13.12 is given by equation (13.29):

From equation (13.26), the 3-dB frequency of H(z) is:

In this case,  = 2/50 and we must solve for a: cos(2/50) = 2 – a/2 – 1/2a  0.5a2 – 1.008a + 0.5 = 0 This has two solutions: a = 1.134 and 0.882 Only the later results in a stable transfer function. Hence, a = 0.882.

To ensure a dc gain of 2, we require H (1) 

b  2  b  2(1  a)  2(1  0.882)  0.236 .

1 a

Q 13.19)

Q 13.20)

Q 13.21)

Q 13.22)

Q 13.23)

Q 13.24)

Q 13.25) The spectrum of the D/A output is that of the sampled sinusoid, having images at kf s  f  k100MHz  5MHz for all integers k , passed through the S/H sinc response.

H sh ( j )  

sin( / 2)

 / 2

The first image of the sinusoid will have the largest amplitude and will occur at f s  f  95 MHz. Hence, it is required that H sh ( j 2 ( f s  f ))  0.25 H sh ( j 2 f )



sin(2 ( f s  f ) / 2) 2 ( f s  f ) / 2

 0.25

sin(2 f  / 2) 2 f  / 2

sin(2 ( f s  f ) / 2) 2 ( f s  f ) / 2

 0.25 (assuming 

 0.25

Solve numerically for: 

2 ( f s  f ) 2.48  2.48     8.3ns 2  ( fs  f )

1/ f )

Analog Integrated Circuit Design 2 nd Edition

Chapter 14 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Yunzhi (Rocky) Dong Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 14.1)

Q 14.2)

Q 14.3)

Q 14.4)

Q 14.5)

Q 14.6)

Q 14.7)

Q 14.8)

Q 14.9)

Q 14.10)

Q 14.11)

Q 14.12)

(14.37)

Q 14.13) (14.37).

Q 14.14)

Q 14.15)

Q 14.16)

Q 14.17)

Q 14.18)

(14.55) – (14.59)

(14.73) – (14.77)

Q 14.19) Advanced phases are indicated by checkmarks in the solution for Q 14.15.

Q 14.20) Following the method of Example 14.6 and combining equations (14.88-14.90), the output offset is given by:

To minimize charge injections we take L = Lmin = 0.18m. We can then solve for the device width W required to maintain a certain de offset:

Rounding to w=8m, we can find the resulting switch on resistance:

The settling time of C2 is given by 5 RC time constants of:

Q 14.21) For a settling time of 40ns, we require the switch on resistance to satisfy:

The switch effective gate-source voltage is:

To minimize charge injection, take L = Lmin = 0.18m. We can then solve for the device width:

By combining equations (14.88 – 14.90), we can calculate the dc offset:

Q 14.22)

Q 14.23) Reset (

)

⁄ ( ⁄

Valid output (

)

) ⁄ (

)

Q 14.24) Fig. 14.37:

Fig. 14.38:

Q 14.25)

Analog Integrated Circuit Design 2 nd Edition

Chapter 15 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Yunzhi (Rocky) Dong Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 15.1)

Q 15.2)

Q 15.3)

Q 15.4)

Q 15.5)

Q 15.6)

Q 15.7)

Q 15.8)

Q 15.9)

Q 15.10)

Q 15.11)

Q 15.12)

Q 15.13)

Q 15.14)

Q 15.15)

Q 15.16) From equation (15.28):

Q 15.17) The resolutions bandwidth is the frequency range over which the SNDR is within 3-dB of it’s highest value. In this case, the highest value is approximately 63dB at dc. Therefore, the resolution bandwidth extends up to approximately 80 MHz.

Analog Integrated Circuit Design 2 nd Edition

Chapter 16 Solutions Compiled by: Tony Chan Carusone Solutions contributed by: Tony Chan Carusone Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

Q 16.1)

Q 16.2)

Q 16.3)

Q 16.4)

Q 16.5)

Q 16.6) The matching accuracy required for the b2 resistor, b3 resistor, and b4 resistor is 2 times, 4 times, and 8 times the matching accuracy of the b1 resistor, respectively.

Q 16.7)

Q 16.8)

Q 16.9)

Q 16.10)

Q 16.11)

Q 16.12)

Q 16.13)

Q 16.14)

Q 16.15)

Q 16.16)

Q 16.17)

Q 16.18)

Q 16.19) The currents in each branch of the circuit are illustrated below.

The minimum output voltage occurs at Vout when all currents are steered towards the opamp feedback resistor, R/2. In this state, the total current through the feedback resistor is I tot 

Vref 2R



Vref 2R



Vref 2R



Vref 4R



Vref 8R



Vref 16 R



Vref 32 R



63Vref 32 R

When this current passes through R/2, the output voltage becomes 63Vref R R 63 Vout   I tot ·     Vref 2 32 R 2 64

With all switches in the opposite position, the current through R/2 is zero and the output voltage reaches its maximum value equal to the ground potential, 0V. Hence the achievable peak-to-peak output swing is

63 Vref 64

Q 16.20) The switches’ (W/L) ratios must be sized in proportion to the current they carry. Illustrated below are all of the branch currents, along with the relative switch sizes required to handle those branch currents.

Analog Integrated Circuit Design 2 nd Edition

Chapter 17 Solutions Compiled by: Amer Samarah Solutions contributed by: Amer Samarah Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

17.1

17.2

17.3

17.4

17.5

17.6

17.7

17.8

17.9

1/2

17.9

2/2

17.10

17.11

17.12

1/2

17.12

2/2

17.13

1/2

17.13

2/2

17.14

17.23

17.24

17.25

17.26

17.27

1/2

17.27

2/2

17.28

17.29

17.30

17.31

17.32

Analog Integrated Circuit Design 2 nd Edition

Chapter 18 Solutions Compiled by: Kentaro Yamamoto Solutions contributed by: Kentaro Yamamoto Ali Sheikholeslami & Khoman Phang (1st ed. Solutions)

18.4

Analog Integrated Circuit Design 2 nd Edition

Chapter 19 Solutions Compiled by: Amer Samarah