AVR Microcontroller and Embedded Systems Using Assembly and C Muhammad Ali Mazidi Solution Manuals

Online Instructor’s Manual to accompany

The AVR Microcontroller and Embedded Systems: Using Assembly and C 1st Edition Muhammad Ali Mazidi DeVry University

Sarmad Naimi Sepehr Naimi

Contents CHAPTER 0: INTRODUCTION TO COMPUTING..................................................................... 5 SECTION 0.1: NUMBERING AND CODING SYSTEMS................................................... 5 SECTION 0.2: DIGITAL PRIMER ........................................................................................ 6 SECTION 0.3: SEMICONDUCTOR MEMORY .................................................................. 8 SECTION 0.4: CPU AND HARVARD ARCHITECTURE ................................................ 10 CHAPTER 1: THE AVR MICROCONTROLLERS: HISTORY AND FEATURES.................. 11 SECTION 1.1: MICROCONTROLLERS AND EMBEDDED PROCESSORS............... 11 SECTION 1.2: OVERVIEW OF THE AVR FAMILY ....................................................... 11 CHAPTER 2: AVR ARCHITECTURE & ASSEMBLY LANGUAGE PROGRAMMING ....... 13 SECTION 2.1: THE GENERAL PURPOSE REGISTERS IN THE AVR........................ 13 SECTION 2.2: THE AVR DATA MEMORY ...................................................................... 13 SECTION 2.3: USING INSTRUCTIONS WITH THE DATA MEMORY....................... 14 SECTION 2.4: AVR STATUS REGISTER .......................................................................... 15 SECTION 2.5: AVR DATA FORMAT AND DIRECTIVES.............................................. 16 SECTION 2.6: INSTRUCTION TO AVR ASSEMBLY PROGRAMMING AND .......... 17 SECTION 2.7: ASSEMBLING AN AVR PROGRAM........................................................ 17 SECTION 2.8: THE PROGRAM AND PROGRAM ROM SPACE IN THE AVR ......... 18 SECTION 2.9: RISC ARCHITECTURE IN THE AVR ..................................................... 20 CHAPTER 3: BRANCH, CALL AND TIME DELAY LOOP .................................................... 21 SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING........................................... 21 SECTION 3.2: CALL INSTRUCTIONS AND STACK ...................................................... 21 SECTION 3.3: AVR TIME DELAY AND INSTRUCTION PIPELINE ........................... 22 CHAPTER 4: AVR I/O PORT PROGRAMMING ...................................................................... 24 SECTION 4.1: I/O PORT PROGRAMMING IN AVR ...................................................... 24 SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING......................................... 25 CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS.......................... 29 SECTION 5.1: ARITHMETIC INSTRUCTIONS............................................................... 29 SECTION 5.2: SIGNED NUMBER CONCEPTS AND ARITHMETIC OPERATIONS 31 SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS............................................. 31 SECTION 5.4: ROTATE AND SHIFT INSTRUCTIONS AND DATA SERIALIZATION ................................................................................................................................................... 32 SECTION 5.5: BCD AND ASCII CONVERSION............................................................... 33 CHAPTER 6: AVR ADVANCED ASSEMBLY LANGUAGE PROGRAMMING ................... 35 SECTION 6.1: INTRODUCING SOME MORE ASSEMBLER DIRECTIVES .............. 35 SECTION 6.2: REGISTER AND DIRECT ADDRESSING MODES ............................... 35 SECTION 6.3: REGISTER INDIRECT ADDRESSING MODE....................................... 36 SECTION 6.4: LOOK-UP TABLE AND TABLE PROCESSING..................................... 37 SECTION 6.5: BIT-ADDRESSABILITY ............................................................................. 40 SECTION 6.6: ACCESSING EEPROM IN AVR................................................................ 42 SECTION 6.7: CKECKSUM AND ASCII SUBROUTINES .............................................. 45 SECTION 6.8: MACROS ....................................................................................................... 48 CHAPTER 7: AVR PROGRAMMING IN C ............................................................................... 49 SECTION 7.1: DATA TYPES AND TIME DELAYS IN C................................................ 49 SECTION 7.2: I/O PROGRAMMING IN C ........................................................................ 49 SECTION 7.3: LOGIC OPERATIONS IN C....................................................................... 51 SECTION 7.4: DATA CONVERSION PROGRAMS IN C................................................ 52 SECTION 7.6: MEMORY ALLOCATION IN C ................................................................ 53 CHAPTER 8: AVR HARDWARE CONNECTION .................................................................... 55

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3

SECTION 8.1: ATMEGA32 PIN CONNECTION .............................................................. 55 SECTION 8.2: AVR FUSE BITS........................................................................................... 55 SECTION 8.3: EXPLAINING THE INTEL HEX FILE FOR AVR ................................. 55 SECTION 8.4: AVR PROGRAMMIN AND TRAINER BOARD ..................................... 56 CHAPTER 9: AVR TIMER PROGRAMMING IN ASSEMBLY AND C.................................. 57 SECTION 9.1: PROGRAMMING TIMERS 0, 1, AND 2 ................................................... 57 SECTION 9.2: COUNTER PROGRAMMING ................................................................... 59 SECTION 9.3: PROGRAMMING TIMERS IN C .............................................................. 60 Chapter 10: INTERRUPT PROGRAMMING IN ASSEMBLY AND C ..................................... 65 SECTION 10.1: AVR INTERRUPTS ................................................................................... 65 SECTION 10.2: PROGRAMMING TIMER INTERRUPTS ............................................. 65 SECTION 10.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS ........... 68 SECTION 10.4: INTERRUPT PRIORITY IN THE AVR.................................................. 70 CHAPTER 11: AVR SERIAL PORT PROGRAMMING IN ASSEMBLY AND C ................... 71 SECTION 11.1: BASICS OF SERIAL COMMUNICATION ............................................ 71 SECTION 11.2: ATMEGA32 CONNECTION TO RS232 ................................................. 71 SECTION 11.3: AVR SERIAL PORT PROGRAMMING IN ASSEMBLY..................... 72 SECTION 11.4: AVR SERIAL PORT PROGRAMMING IN C........................................ 74 CHAPTER 12: LCD AND KEYBOARD INTERFACING ......................................................... 76 SECTION 12.1: LCD INTERFACING ................................................................................. 76 SECTION 12.2: KEYBOARD INTERFACING .................................................................. 76 CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING .................................................... 77 SECTION 13.1: ADC CHARACTERISTICS ...................................................................... 77 SECTION 13.2: ADC PROGRAMMING IN THE ATMEGA32 ....................................... 77 SECTION 13.3: SENSOR INTERFACING AND SIGNAL CONDITIONING ............... 78 SECTION 13.4: DAC INTERFACING................................................................................. 78 Chapter 14: RELAY, OPTOISOLATOR, AND STEPPER MOTOR INTERFACING WITH AVR .............................................................................................................................................. 80 SECTION 14.1: RELAYS AND OPTOISOLATORS ......................................................... 80 SECTION 14.2: STEPPER MOTOR INTERFACING ....................................................... 80 Chapter 15: INPUT CAPTURE AND WAVE GENERATION IN AVR .................................... 81 SECTION 15.1: WAVE GENERATION USING 8-BIT TIMERS..................................... 81 SECTION 15.2: WAVE GENERATION USING TIMER1 ................................................ 82 SECTION 15.3: INPUT CAPTURE PROGRAMMING..................................................... 84 SECTION 15.4: C PROGRAMMING .................................................................................. 84 Chapter 16: PWM AND DC MOTOR CONTROL ...................................................................... 87 SECTION 16.1: DC MOTOR INTERFACING AND PWM .............................................. 87 SECTION 16.2: PWM MODES IN 8-BIT TIMERS............................................................ 87 SECTION 16.3: PWM MODES IN TIMER1 ....................................................................... 89 Chapter 17: SPI PROTOCOL AND MAX7221 DESPLAY INTERFACING ............................. 92 SECTION 17.1: SPI BUS PROTOCOL ................................................................................ 92 SECTION 17.2: SPI PROGRAMMING IN AVR ................................................................ 92 SECTION 17.3: MAX7221 INTERFACING AND PROGRAMMING ............................. 92 Chapter 18: I2C PROTOCOL AND DS1307 RTC INTERFACING ........................................... 93 SECTION 18.1: I2C BUS PROTOCOL................................................................................ 93 SECTION 18.2: TWI PROGRAMMING IN AVR .............................................................. 93 SECTION 18.3: AVR TWI PROGRAMMING IN ASSEMBLY AN C............................. 93 SECTION 18.4: DS1307 RTC INTERFACING AND PROGRAMMING ........................ 95

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4

CHAPTER 0: INTRODUCTION TO COMPUTING SECTION 0.1: NUMBERING AND CODING SYSTEMS 1.

2.

3.

4.

5.

6.

(a) 1210 = 11002 (b) 12310 = 0111 10112 (c) 6310 = 0011 11112 (d) 12810 = 1000 00002 (e) 100010 = 0011 1110 10002 (a) 1001002 = 3610 (b) 10000012 = 6510 (c) 111012 = 2910 (d) 10102 = 1010 (e) 001000102 = 3410 (a) 1001002 = 2416 (b) 10000012 = 4116 (c) 111012 = 1D16 (d) 10102 = 0A16 (e) 001000102 = 2216 (a) 2B916 = 0010 1011 10012, 69710 (b) F4416 = 1111 0100 01002, 390810 (c) 91216 = 1001 0001 00102, 232210 (d) 2B16 = 0010 10112, 4310 (e) FFFF16 = 1111 1111 1111 11112, 6553510 (a) 1210 = 0C16 (b) 12310 = 7B16 (c) 6310 = 3F16 (d) 12810 = 8016 (e) 100010 = 3E816 (a) 1001010 Î 0011 0110 (b) 111001 Î 0000 0111 (c) 10000010 Î 0111 1110 (d) 111110001 Î 0000 1111

7. (a) 2C+3F = 6B (b) F34+5D6 = 150A (c) 20000+12FF = 212FF (d) FFFF+2222 = 12221 8. (a) 24F-129 = 12616

.

5

9.

(b) FE9-5CC = A1D16 (c) 2FFFF-FFFFF = 3000016 (d) 9FF25-4DD99 = 5218C16 (a) Hex: 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 (b) Binary: 11 0000, 11 0001, 11 0010, 11 0011, 11 0100, 11 0101, 11 0110, 11 0111, 11 1000, 11 1001.

ASCII (hex) 30 31 32 33 34 35 36 37 38 39

0 1 2 3 4 5 6 7 8 9

Binary 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001

10.

000000 22 55 2E 53 2E 41 2E 20 69 73 20 61 20 63 6F 75 000010 6E 74 72 79 22 0D 0A 22 69 6E 20 4E 6F 72 74 68 000020 20 41 6D 65 72 69 63 61 22 0D 0A

"U.S.A. is a cou ntry".."in North America"..

SECTION 0.2: DIGITAL PRIMER 11.

A

1

B

2

3

4 6

C

12.

A 0 0 0 0 1 1 1 1

.

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

5

Y 0 1 1 1 1 1 1 1

6

13. .

A

1

B

2

3

4 6

C

14.

A 0 0 0 0 1 1 1 1

5

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 0 0 0 0 0 0 1

15.

A

1

B

2

3

4 6

C

16.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

5

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 1 1 0 1 0 0 1

Y 1 1 1 1 1 1 1 0

17.

.

7

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 1 0 0 0 0 0 0 0

D X 0 1

Q NC 0 1

18.

LSB

19.

LSB

20.

CLK No Yes Yes

SECTION 0.3: SEMICONDUCTOR MEMORY 21. (a) 4 (b) 4 (c) 4 (d) 1 048 576, 220 (e) 1024K (f) 1 073 741 824, 230 (g) 1 048 576 K (h) 1024M (i) 8388608, 8192K 22. Disk storage capacity / size of a page = (2*230) / (25*80) = 1 million pages

.

8

23. (a) 9FFFFh – 10000h = 8FFFFh = 589 824 bytes (b) 576 kbytes 24. 232 – 1 = 4 294 967 295 25. (a) FFh, 255 (b) FFFFh, 65535 (c) FFFF FFFFh, 4 294 967 295 (d) FFFF FFFF FFFF FFFFh, 18 446 744 073 709 551 615 26. (a) 216 = 64K (b) 224 = 16M (c) 232 = 4096 Mega, 4G (d) 248 = 256 Tera, 262144 Giga, 268435456 Mega 27. Data bus is bidirectional, address bus is unidirectional (exit CPU).

28. The storage of the chip is measured in Megabits while the Computer memory is measured in Megabytes.

29. True, the more address lines the more memory locations.

30. True, the memory location size is fixed.

31. True, the more data lines the more memory locations 32. True 33. access time 34. True 35. electrically erasable 36. True 37. DRAM 38. SRAM 39. DRAM and SRAM 40. (c) 41. (c) 42. (a) 32Kx8, 256K (f) 8Kx1, 8K (b) 8Kx8, 64K (g) 4Kx8, 32K (c) 4Kx8, 32K (h) 2Kx8, 16K (d) 8Kx8, 64K (i) 256Kx4, 1M (e) 4Mx1, 4M (j) 64Kx8, 512K 43. (a) 128K 14 8 (f) 256K 8 4 (b) 256K 15 8 (g) 8M 20 8 (c) 512K 16 8 (h) 16M 11 4 (d) 2M 18 8 (i) 512K 16 8 (e) 512K 16 8 44. 4000h - 7FFFh 45.

A0

A11 A12 A13

.

1 3 1

2

2

~CS

9

46. 8000h - 8FFFh, B000h - BFFFh, E000 – EFFFh 47.

A0

8kx8

A12

U? A13 A14 A15 Vcc

1 2 3 6 4 5

A B C G1 G2AN G2BN

Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N

15 14 13 12 11 10 9 7

~CS

74138

Each controls 8K bytes block 48. 6000h - 7FFFh, C000h - DFFFh, E000h – FFFFh 49.

A0

32kx8

A14

U? A15 A16 A17 Vcc

1 2 3 6 4 5

A B C G1 G2AN G2BN

Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N

15 14 13 12 11 10 9 7

~CS

74138

Each controls 32K bytes block 50. 4000h - 7FFFh, 8000h - BFFFh, C000h – FFFFh SECTION 0.4: CPU AND HARVARD ARCHITECTURE 51. PC ( Program Counter ) 52. ALU is responsible for all arithmetic and logic calculations in the CPU. 53. Address, control and data

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10

CHAPTER 1: THE AVR MICROCONTROLLERS: HISTORY AND FEATURES SECTION 1.1: MICROCONTROLLERS AND EMBEDDED PROCESSORS 1.

2.

3.

4.

5.

6.

7.

8.

9.

False.

True.

True.

True.

CPU, RAM, ROM, EEPROM, I/O, Timer, Serial COM port, ADC. RAM and ROM. Keyboard, mouse, printer.

Computing power and compatibility with millions and millions of PCs. PIC 16x – Microchip Technology, 8051 - Intel, AVR – Atmel, Z8 – Zilog, 68HC11 – Freescale Semiconductor (Motorola).

10. 8051.

11. Power consumption.

12. The ROM area is where the executable code is stored.

13. Very, in case there is a shortage by one supplier.

14. Suppliers other than the manufacturer of the chip.

15. B is absolutely wrong; 16 bit software can not run on an 8 bit system due to special instructions and registers. But A can be true (in the case of software compatibility).

SECTION 1.2: OVERVIEW OF THE AVR FAMILY 16. Flash memory is ideal for fast development because Flash memory can be erased in seconds compared to 20 minutes or more needed for the UV-EPROM. 17. 32 pins 18. 32 Kbytes 19. 256 bytes 20. 8 21. 4K 22. 6 23. 2K 24. ATtiny11, ATtiny12, ATting15L 25. All AVRs have Flash ROM; but a few of them, like ATtiny20, ATtiny28L, and ATtiny4 have no EEPROM 26. AT90USB1286, AT90USB1287, AT90USB162, AT90USB646, AT90USB647, AT90USB82 27. AT90CAN128, AT90CAN32, AT90CAN64 28.

Program ROM Data RAM (a) ATmega32 32 Kbytes 2048 (b) ATtiny44 2 Kbytes 128

.

11

(c) ATtiny84 8 Kbytes (d) 90CAN128 128 Kbytes

512 4K

29.

Program ROM Data RAM ATmega32 32 Kbytes 2048 ATmega16 16 Kbytes 1024 30.

.

EEPROM 1024 512

512

12

CHAPTER 2: AVR ARCHITECTURE & ASSEMBLY LANGUAGE PROGRAMMING SECTION 2.1: THE GENERAL PURPOSE REGISTERS IN THE AVR 1.

2.

3.

4.

5.

6.

7.

8.

8 8 8 0xFF $28 – in R20 (a), (c), (d), (e), (g) (c) This is an illegal instruction since the arguments of ADD should be register. If they instruction was valid 0x44 would be stored in R19 9. This is an illegal instruction since the arguments of ADD should be register. If they instruction was valid 0xFF would be stored in R21 10. True

SECTION 2.2: THE AVR DATA MEMORY 11. internal SRAM 12. True 13. True 14. False 15. False 16. data memory 17. data memory = general purpose register + I/O registers + SRAM. All AVRs have 32 general purpose registers. AVRs with less than 32 I/O pins, which are not a member of special purpose AVR, have 64 I/O registers. The size of SRAM can be found in figures of Chapter 1. (a) 32 + 64 + 2048 = 2144 (b) 32 + 64 + 1024 = 1120 (c) 32 + 64 + 256 = 352 18. EEPROM does not lose its data when power is off, whereas SRAM does. So, the EEPROM is used for storing data that should rarely be changed and should not be lost when the power is off (e.g., options and settings); whereas the SRAM is used for storing data and parameters that are changed frequently.

19. Yes 20. No, each microcontroller should have general purpose registers and I/O registers.

21. From $60 to $FFFF 22. 65,536 bytes

.

13

SECTION 2.3: USING INSTRUCTIONS WITH THE DATA MEMORY 23.

LDI STS LDI STS

R20, $30 $105, R20 R20, $97 $106, R20

LDI STS STS STS STS STS STS STS STS STS

R20, $55 $300, R20 $301, R20 $302, R20 $303, R20 $304, R20 $305, R20 $306, R20 $307, R20 $308, R20

24.

25.

LDI R16, $5F OUT PORTB, R16

26. True 27.

LDI R30, $11 STS $100, R30 STS $101, R30 STS $102, R30 STS $103, R30 STS $104, R30 STS $105, R30 LDS R20, $100 LDS R16, $101 ADD R20, R16 LDS R16, $102 ADD R20, R16 LDS R16, $103 ADD R20, R16 LDS R16, $104 ADD R20, R16 LDS R16, $105 ADD R20, R16

28.

LDI R30, $11 STS $100, R30 STS $101, R30 STS $102, R30 STS $103, R30 STS $104, R30 STS $105, R30

.

14

LDS R20, $100 LDS R16, $101 ADD R20, R16 LDS R16, $102 ADD R20, R16 LDS R16, $103 ADD R20, R16 LDS R16, $104 ADD R20, R16 LDS R16, $105 ADD R20, R16 STS $105, R20

29.

LDI R16, $15 STS $67, R16 LDI R19, 0 LDS R20, $67 ADD R19, R20 ADD R19, R20 ADD R19, R20 ADD R19, R20 ADD R19, R20

30.

LDI R16, $15 STS $67, R16 LDI R19, 0 LDS R20, $67 ADD R19, R20 ADD R19, R20 ADD R19, R20 ADD R19, R20 ADD R19, R20 STS $67, R19

31.

LDُ S R27, $68 ُ COM R27

32.

LDُ S R19, $68 ُ OUT PORTC, R19

SECTION 2.4: AVR STATUS REGISTER 33. 8 34. 0, 5

.

15

35. 3, 2 36. When there is a carry beyond the D7 bit.

37. When there is a carry from the D3 to the D4 bit.

38. C = 1 because there is a carry beyond the D7 bit.

Z = 1 because the R20 (the result) has value 0 in it after the addition.

39. (a) $54 0101 0100 + $C4 1100 0100 $118 10001 1000 R20 = $18 C = 1 because there is a carry beyond the D7 bit. (b) $00 0000 0000 $FF 1111 1111 $FF 1111 1111 C = 0 because there is no carry beyond the D7 bit. +

R23 = $FF

(c) $FF 1111 1111 $05 0000 0101 $FF 10000 0100 C = 1 because there is a carry beyond the D7 bit. +

R30 = $04

40.

LDI R16, $55 LDI R20, $55 ADD R16, R20 ADD R16, R20 ADD R16, R20 ADD R16, R20 ADD R16, R20

SECTION 2.5: AVR DATA FORMAT AND DIRECTIVES 41. .EQU MYDAT_1 = $37 .EQU MYDAT_2 = $62 .EQU MYDAT_3 = $47 .EQU MYDAT_4 = $50 .EQU MYDAT_5 = $C8 .EQU MYDAT_6 = $41 .EQU MYDAT_7 = $AA .EQU MYDAT_8 = $FF .EQU MYDAT_9 = $90 .EQU MYDAT_10 = $7E .EQU MYDAT_11 = $0A .EQU MYDAT_12 = $0F

.

16

42. .EQU DAT_1 = $16 .EQU DAT_2 = $56 .EQU DAT_3 = $99 .EQU DAT_4 = $20 .EQU DAT_5 = $F6 .EQU DAT_6 = $FB

43. .EQU TEMP0 = $60 .EQU TEMP1 = $61 .EQU TEMP2 = $62 .EQU TEMP3 = $63 .EQU TEMP4 = $64 .EQU TEMP5 = $65 LDI R16, $11 STS TEMP0, R16 STS TEMP1, R16 STS TEMP2, R16 STS TEMP3, R16 STS TEMP4, R16 STS TEMP5, R16 LDS R20, TEMP0 LDS R21, TEMP1 ADD R20, R21 LDS R21, TEMP2 ADD R20, R21 LDS R21, TEMP3 ADD R20, R21 LDS R21, TEMP4 ADD R20, R21 LDS R21, TEMP5 ADD R20, R21

SECTION 2.6: INSTRUCTION TO AVR ASSEMBLY PROGRAMMING AND SECTION 2.7: ASSEMBLING AN AVR PROGRAM 44. Low, High 45. Assembly 46. Assembler 47. True 48. False 49. False 50. No 51. Because they do not produce machine instructions. They just give directions to the assembler.

52. True 53. hex 54. hex, eep, lst, map, and obj

.

17

SECTION 2.8: THE PROGRAM AND PROGRAM ROM SPACE IN THE AVR 55. 0 56. It executes whatever is at location 0 which could be garbage in this case.

57. a) 2 bytes b) 2 bytes c) 2 bytes d) 2 bytes e) 2 bytes f) 2 bytes g) 2 bytes h) 4 bytes 58. (a) LDI R20,‘1’ STS 0x100, R20 LDI R20,‘9’ STS 0x101, R20 LDI R20,‘5’ STS 0x102, R20 LDI R20,‘1’ STS 0x103, R20 LDI R20,‘2’ STS 0x104, R20

(b) LDI R19,0 LDS R16, 0x100 ADD R19,R16 LDS R16, 0x101 ADD R19,R16 LDS R16, 0x102 ADD R19,R16 LDS R16, 0x103 ADD R19,R16 LDS R16, 0x104 ADD R19,R16 STS 0x306, R19

(c)

59. In AVR, each location of the program memory holds 2 bytes; therefore: a) Memory locations = 32 K / 2 = 16 K = 16 * 1024 = 16384 Î Last location = 16383 = $3FFF

.

18

b) Memory locations = 8 K / 2 = 4 K = 4 * 1024 = 4096 Î Last location = 4095 = $FFF c) Memory locations = 64 K / 2 = 32 K = 32 * 1024 = 32768 Î Last location = 32767 = $7FFF d) Memory locations = 16 K / 2 = 8 K = 8 * 1024 = 8192 Î Last location = 8191 = $1FFF e) Memory locations = 128 K / 2 = 64 K = 64 * 1024 = 65536 Î Last location = 65535 = $FFFF 60. In ATmega32, the program memory is 32K bytes. Since the 32K is organized as 16K x 2 Bytes, the last location has the address of $3FFF. Therefore the program counter can have values between 0 and $3FFF. 61. $7FFF = 32767 Î the program memory has 32767 + 1 = 32768 locations. Therefore, it has 65536 = 64K bytes.

62. $3FF = 1023 Î the program memory has 1024 locations. Therefore, the size of program memory is 2 Kbytes.

63. (a) $1FFF + 1 = 8,192 words = 16,384 bytes = 16 KB (b) $3FFF + 1 = 16,384 words = 32 KB (c) $7FFF + 1 = 32,768 words = 64 KB (d) $FFFF + 1 = 65,536 words = 128 KB (e) $1FFFF + 1 = 131,072 words = 256 KB (f) $3FFFF + 1 = 262,144 words = 512 KB (g) $FFF + 1 = 4096 words = 8 KB (h) $1FF + 1 = 512 words = 1 KB 64. (a) $3FF + 1 = 1024 words = 2 KB (b) $7FF + 1 = 2048 words = 4 KB (c) $7FFFF + 1 = 524,288 words = 1,048,576 KB (d) $FFFFF + 1 = 1,048,576 words = 2048 KB = 2 MB (e) $1FFFFF + 1 = 2,097,152 words = 4096 KB = 4 MB (f) $3FFFFF + 1 = 4,194,304 words = 8192 KB = 8 MB (g) $5FFF + 1 = 24,576 words = 49152 bytes = 48 KB (h) $BFFFF + 1 = 786,432 words = 1,572,864 bytes = 1536 KB = 1.5 MB 65. 2 bytes 66. 2 bytes 67. As shown in Figure 2-14, 8 bits are set aside for K. Therefore, K can be between 0 and 255.

68. $0C01 = 0000 1100 0000 0001. According to the figures of page 92, it is the machine code for the ADD instruction.

69. It is a 4-byte instruction. 16 bits of it are set aside for K. Therefore, K can be between 0 and 65535. In AVR, the data memory is 64 KB; as a result, STS can address the entire memory space.

70. It is a 4-byte instruction. 16 bits of it are set aside for K. Therefore, K can be between 0 and 65535. In AVR, the data memory is 64 KB; as a result, LDS can address the entire memory space.

71. In the JMP instruction, 22 bits are set aside for K. Therefore K can be between 0 and 4,194,303.

.

19

SECTION 2.9: RISC ARCHITECTURE IN THE AVR 72. RISC is reduced instruction set computer; CISC stands for complex instruction set computer.

73. CISC 74. RISC 75. RISC 76. CISC 77. False

.

20

CHAPTER 3: BRANCH, CALL AND TIME DELAY LOOP SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING 1.

2.

3.

4.

5.

6.

256 The instruction following the jump PC Relative jump, 2 4 RJMP is 2 byte whereas JMP is 4 bytes. Therefore RJMP uses less memory location.

7. False 8. False 9. a, b, and d 10. The RJMP instruction is a 2-byte instruction. Of the 16 bits, the first 4 bits are set aside for the opcode and the other 12 bits are used for the address of the destination (operand). The operand can be between -2048 and 2047.

11. True 12.

LDI BEGIN:LDI HERE: DEC BRNE DEC BRNE

R20, 10 R21, 100

LDI LDI LDI

R20, 10 R21, 100 R22, 100

DEC BRNE DEC BRNE DEC BRNE

R22 L3 R21 L2 R20 L1

R21 HERE R20 BEGIN

13.

L1: L2: L3:

14. 200 * 100 = 20,000 times 15. Negative 16. Positive SECTION 3.2: CALL INSTRUCTIONS AND STACK 17. 4 18. 2

.

21

19. False 20. True 21. In the AVRs whose program counter is not longer than 16 bits, 2 bytes are pushed into the stack. In the AVRs whose program counters are longer than 16 bits, 3 bytes are pushed.

22. In the AVRs whose program counter is not longer than 16 bits, 2 bytes are pushed into the stack. In the AVRs whose program counters are longer than 16 bits, 3 bytes are pushed.

23. 0 24. When the RET instruction at the end of the subroutine is executed, the top location of the stack is copied back to the program counter and the stack pointer is incremented. As a result the CALL is loaded into the PC, and the instruction below the CALL instruction is executed.

25. In AVR, the stack can be as big as the internal RAM. 26. When a subroutine is called, the address of the instruction just below the CALL instruction is pushed onto the stack.

SECTION 3.3: AVR TIME DELAY AND INSTRUCTION PIPELINE 27. crystal frequency = 1 / machine cycle = 1 / 1.25 µs = 0.8 MHz. 28. machine cycle = 1 / 20 MHz = 0.05 µs 29. machine cycle = 1 / 10 MHz = 0.1 µs 30. machine cycle = 1 / 16 MHz = 0.0625 µs 31. False 32.

LDI BACK: LDI HERE: NOP DEC BRNE DEC BRNE

Machine Cycle R16, 200 1 R18, 100 1 1 R18 1 HERE 2/1 R16 1 BACK 2/1

1 + (1 + (1 + 1 + 2) × 100 – 1 + 1 + 2) × 200 – 1 = 1 + (1 + 400 + 2) × 200 = 1 + 403 × 200 – 1 = 80,600 machine cycles 80,600 × 0.125 µs = 10075 µs = 10.075 ms 33.

LDI BACK: LDI HERE: NOP NOP DEC BRNE DEC BRNE

.

Machine Cycle R20, 200 1 R22, 100 1 1 1 R22 1 HERE 2/1 R20 1 BACK 2/1

22

1 + (1 + (1 + 1 + 1 + 2) × 100 – 1 + 1 + 2) × 200 – 1 = 1 + (1 + 500 + 2) × 200 = 1 + 503 × 200 – 1 = 100,600 machine cycles 100,600 × 0.125 µs = 12575 µs = 12.575 ms 34.

LDI BACK: LDI HERE: NOP DEC BRNE DEC BRNE

Machine Cycle R20, 200 1 R21, 250 1 1 R21 1 HERE 2/1 R20 1 BACK 2/1

1 + (1 + (1 + 1 + 2) × 250 – 1 + 1 + 2) × 200 – 1 = (1 + 1000 + 2) × 200 = 1003 × 200 = 200,600 machine cycles Instruction cycle = 1 / 4 MHz = 0.25 µs 200600 × 0.25 µs = 50150 µs = 50.150 ms 35.

LDI BACK: LDI NOP NOP NOP HERE: DEC BRNE DEC BRNE

Machine Cycle R20, 200 1 R25, 100 1 1 1 1 R25 1 HERE 2/1 R20 1 BACK 2/1

1 + (1 + 1 + 1 + 1 + (1 + 2) × 100 – 1 + 1 + 2) × 200 – 1 = 1 + (4 + 300 + 2) × 200 – 1 = 61,200 machine cycles Instruction cycle = 1 / 10 MHz = 0.1 µs 61200 × 0.1 µs = 6120 µs = 6.12 ms

.

23

CHAPTER 4: AVR I/O PORT PROGRAMMING SECTION 4.1: I/O PORT PROGRAMMING IN AVR 1. 40 pins 2. 2 pins are assigned to VCC: VCC and AVCC; and 2 pins are assigned to GND: GND and AGND. 3. 32 pins 4. 8 pins (pins 33-40) 5. 8 pins (pins 1-8) 6. 8 pins (pins 22-29) 7. 8 pins (pins 14-21) 8. input 9. The DDRx register is used for the purpose of making a given port an input or output port. The contents of PORTx registers determine the value of each port when it is output.

10. .INCLUDE "M32DEF.INC" LDI R20, 0x00 OUT DDRC, R20 LDI R20,0xFF OUT DDRB, R20 OUT DDRD, R20 AGAIN: IN R20, PINC OUT PORTB, R20 OUT PORTD, R20 JMP AGAIN

11. .INCLUDE "M32DEF.INC" LDI R20, 0x00 OUT DDRD, R20 LDI R20,0xFF OUT DDRB, R20 OUT DDRC, R20 AGAIN: IN R20, PIND OUT PORTB, R20 OUT PORTC, R20 JMP AGAIN

12. pins 14 and 15 13.

Port DDRA DDRB DDRC

.

Address $3A $37 $34

24

14. (a) .INCLUDE “M32DEF.INC” LDI R16, 0xFF OUT DDRB, R16 OUT DDRC, R16 L1: LDI R16, 0xAA OUT PORTB, R16 OUT PORTC, R16 LDI R16, 0x55 OUT PORTB, R16 OUT PORTC, R16 RJMP L1

(b) .INCLUDE “M32DEF.INC” LDI R16, 0xFF OUT DDRB, R16 OUT DDRC, R16 LDI R16, 0xFF OUT PORTB, R16 OUT PORTC, R16 L1: COM R16 OUT PORTB, R16 OUT PORTC, R16 RJMP L1

SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING 15. In ATmega32, all ports are bit addressable.

16. The advantage of the bit addressing is that it allows each bit to be modified without affecting the other bits.

17. COM PORTB is invalid because AVR ports are not read-modify-write.

18. .INCLUDE “M32DEF.INC” SBI DDRB, 2 SBI DDRB, 5 L1: SBI PORTB, 2 SBI PORTB, 5 CBI PORTB, 2 CBI PORTB, 5 RJMP L1

19. .INCLUDE “M32DEF.INC” SBI DDRD, 3 SBI DDRD, 7 SBI DDRC, 5 L1: SBI PORTD, 3 SBI PORTD, 7 SBI PORTC, 5 CBI PORTD, 3 CBI PORTD, 7 CBI PORTC, 5 RJMP L1

.

25

20. .INCLUDE “M32DEF.INC” LDI R16,0xFF OUT DDRD,R16 CBI DDRC, 3 L1: SBIS PINC, 3 RJMP L1 LDI R16,0x55 OUT PORTD,R16 HERE: RJMP HERE

21. .INCLUDE “M32DEF.INC” LDI R16,0xFF OUT DDRC,R16 CBI DDRB, 7 L1: SBIC PINB, 7 RJMP L1 HERE: LDI R16,0x55 OUT PORTC,R16 LDI R16,0xAA OUT PORTC,R16 RJMP HERE

22. .INCLUDE “M32DEF.INC” LDI R16,0xFF OUT DDRB,R16 CBI DDRA, 0 L1: SBIS PINA, 0 RJMP L2 LDI R16,0x99 OUT PORTB,R16 RJMP L1 L2: LDI R16,0x66 OUT PORTB,R16 RJMP L1

;when PA0 is low the line is executed ;when PA0 is high the line is executed

23. .INCLUDE “M32DEF.INC” CBI DDRB, 5 SBI DDRB, 3 L1: SBIS PINB, 5 RJMP L1 CBI PORTB,3 SBI PORTB,3 CBI PORTB,3 L2: RJMP L2

.

;jump L1 while PB5 is low ;when PB5 is high the line is executed

26

24. .INCLUDE “M32DEF.INC” CBI DDRC, 3 SBI DDRC, 4 L1: SBIS PINC, 3 RJMP L2 SBI PORTC, 4 RJMP L1 L2: CBI PORTC, 4 RJMP L1

;PC3 as input ;PC4 as output ;jump L1 while PC3 is low ;when PC3 is high the line is executed

25.

Make PD6 and PD7 input

CBI CBI

DDRD, 6 DDRD, 7

Make PC0 and PC7 output

SBI SBI

DDRC, 0 DDRC, 7

Yes

Is PD6 one

L1:

SBIS PIND, 6

No

Yes

Jump to PD6_LOW

RJMP PD6_LOW

Set PC0

SBI PORTC, 0 RJMP L2

Clear PC0

PD6_LOW: CBI PORTC, 0

Is PD7 one

L2:

SBIS PIND, 7

No

Jump to PD7_LOW

RJMP PD7_LOW

Set PC7

SBI RJMP

Clear PC7

.

PD7_LOW: CBI RJMP

PORTC, 7 L1 PORTC, 7 L1

27

.INCLUDE “M32DEF.INC” CBI DDRD, 6 CBI DDRD, 7 SBI DDRC, 0 SBI DDRC, 7 L1: SBIS PIND, 6 RJMP PD6_LOW SBI PORTC, 0 RJMP L2 PD6_LOW: CBI PORTC, 0 L2: SBIS PIND, 7 RJMP PD7_LOW SBI PORTC, 7 RJMP L1 PD7_LOW: CBI PORTC, 7 RJMP L1

;PD6 as input ;PD7 as input ;PC0 as output ;PC7 as output ;jump PD6_LOW if PD6 is low ;when PD6 is high the line is executed

;jump L1 while PD7 is low ;when PD7 is high the line is executed

26. .INCLUDE “M32DEF.INC” CBI DDRB, 5 CBI DDRB, 6 LDI R16, 0xFF OUT DDRC, R16 L1: SBIC PINB, 5 RJMP L2 IS_LOW: LDI R16, 0x55 OUT PORTC, R16 RJMP L1 L2: SBIS PINB, 6 RJMP IS_LOW LDI R16, 0xAA OUT PORTC, R16 RJMP L1

;jump L2 if PB5 is high

;jump IS_LOW if PB6 is low

27. .INCLUDE “M32DEF.INC” CBI DDRB, 5 CBI DDRB, 6 LDI R16, 0xFF OUT DDRC, R16 L1: SBIS PINB, 5 RJMP L2 IS_HIGH: LDI R16, 0xAA OUT PORTC, R16 RJMP L1 L2: SBIC PINB, 6 RJMP IS_HIGH BOTH_LOW: LDI R16, 0x55 OUT PORTC, R16 RJMP L1 28. 1001 1011 1011 0011 29. 1001 1010 1101 1010

.

;jump L2 if PB5 is low

;jump IS_HIGH if PB6 is high

28

CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS SECTION 5.1: ARITHMETIC INSTRUCTIONS 1. All the calculations are done in hexadecimal system. (a) 3 F +4 5 8 4 C = 0, Z = 0, H = 1 (b)

(c)

(d)

9 9 +5 8 F 1

C = 0, Z = 0, H = 1

1 +F F +0 0 (1) 0 0

C = 1, Z = 1, H = 1

F F +0 1 (1) 0 0

C = 1, Z = 1, H = 1

2.

LDI LDI ADD

R20,25 R21,10 R20,R21

LDI LDI ADD LDI ADC

R20,0x25 R21,0x19 R20,R21 R21,0x12 R20,R21

LDI LDI ADD LDI ADD LDI ADD

R20,0x25 R21,0x19 R20,R21 R21,0x12 R20,R21 R21,0x3D R20,R21

(a)

Take 2’s complement of 0x12 (0001 0010): Add to 0x23: 0010 0011 + 1110 1110 1 0001 0001 Result = 0001 0001 = 0x11

3.

4.

5.

.

1110 1110

29

(b)

Take 2’s complement of 0x53 (0101 0011): Add to 0x43: 0100 0011 + 1010 1101 0 1111 0000 Result = 1111 0000 = 0xF0

(c)

99 decimal = 0x63 = 0110 0011 Take 2’s complement of 0x63 (0110 0011): Add to 0x63: 0110 0011 + 1001 1101 1 0000 0000 Result = 0000 0000 = 0x00

1010 1101

1001 1101

6. (a) LDI SUBI

R20,0x23 R20,0X12

LDI SUBI

R20,0x43 R20,0X53

LDI SUBI

R20,99 R20,99

(b) (c)

7.

LDI LDI LDI LDI ADD ADC

R23,0x7F R22,0x9A R21,0xBC R20,0x48 R20,R22 R21,R23

LDI LDI LDI LDI SUB SBC

R23,0x7F R22,0x9A R21,0xBC R20,0x48 R20,R22 R21,R23

LDI LDI MUL

R21,77 R20,34 R20,R21

;the result will be in R1:R0

LDI LSR LSR

R21,64 R21 R21

;divide the number by 2. R21 = 64/2 = 32 ;divide the number by 3. R21 = 32/2 = 16

8.

9.

10.

11.

R1:R0

.

30

SECTION 5.2: SIGNED NUMBER CONCEPTS AND ARITHMETIC OPERATIONS 12.

(a) 1110 1001 (e) 1000 0000

(b) 0000 1100 (f) 0111 1111

(c) 1110 0100

(d) 0110 1111

13. unsigned 14. (a) LDI LDI ADD

R21,15 R20,-12 R20,R21

0000 1111 + 1111 0100 = (1)0000 0011 V = 0

LDI LDI ADD

R21,-123 R20,-127 R20,R21

1000 0101 + 1000 0001 = (1)0000 0110 V = 1

LDI LDI ADD

R21,+25 R20,+34 R20,R21

0010 0101 + 0011 0100 = (0)0101 1001 V = 0

LDI LDI ADD

R21,-127 R20,+127 R20,R21

1000 0001 + 0111 1111 = (1)0000 0000 V = 0

(b)

(c)

(d)

15. C flag is raised when there is a carry out of D7 of the result, but V flag is raised when there is a carry from D6 to D7 and no carry out of D7 or when there is no carry from D6 to D7 and there is a carry out of D7 of the result. C flag is used to indicate overflow in unsigned arithmetic operations while V flag is involved in signed operations.

16. When there is a carry from D6 to D7 of result, but there is no carry out of D7 (C=0) OR when there is no carry from D6 to D7 of result, but there is a carry out of D7 (C=1) 17. Status register 18. BRVS and BRVC instructions - BRCS and BRCC instructions SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS 19. (a) 0110 0101 AND 0111 0110 = 0110 0100 = 0x64 (b) 0111 0000 OR 0110 1011 = 0111 1011 = 0x7B (c) 1001 0101 EXOR 1010 1010 = 0011 1111 = 0x3F (d) 0101 1101 AND 0111 0101 = 0101 0101 = 0x55 (e) 1100 0101 OR 0001 0010 = 1101 0111 = 0xD7 (f) 0110 1010 EXOR 0110 1110 = 0000 0100 = 0x04 (g) 0011 0111 OR 0010 0110 = 0011 0111 = 0x37

.

31

20. BRSH is used after the compare instruction. If the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented in Rr, then program execute a jump.

21. Yes. 22. both (a) and (b) 23. 0x85 SECTION 5.4: ROTATE AND SHIFT INSTRUCTIONS AND DATA SERIALIZATION 24. (a) 0 01010110 Æ 0 01100101 Æ C = 0 Æ 1 00110010 Æ 0 10011001 = 99h (b) 0 0011 1001 Æ C = 1 Æ 0 0111 0011 Æ 0 11100110 = E6h (c) C = 0 Æ 0 0100 1101 Æ 0 1101 0100 Æ 1 1010 1000 Æ 0 1101 0100 = D4h (d) 0 0111 1010 Æ 0 0011 1101 = 3Dh 25. (a) LDI MOV ANDI CLC ROL ROL ROL ROL ANDI CLC ROL ROL ROL ROL ROL OR

R20,0xFA R21, R20 R20,0x0F

LDI MOV ANDI CLC ROR ROR ROR ROR ROR ANDI CLC ROR ROR ROR ROR OR

R20,0xFA R21, R20 R20,0x0F

R20 R20 R20 R20 R21,0xF0 R21 R21 R21 R21 R21 R20,R21

(b)

.

R20 R20 R20 R20 R20 R21,0xF0 R21 R21 R21 R21 R20,R21

32

26. .INCLUDE "M32DEF.INC" LDI R20,0b10111001 LDI R21, 8 ;set a counter to 8 LDI R22, 0 ;set number of zeros to 0 AGAIN:ROL R20 ;move MSB to Carry BRCC NEXT ;branch if no carry INC R22 ;increment number of zeros NEXT: DEC R21 ;decrement the counter BRNE AGAIN

27.

LDI LDI AGAIN:ROR BRCS INC CPI BRNE FIN:

R20, 0x68 R21, 0 R20 FIN R21 R21,8 AGAIN

LDI LDI AGAIN:ROL BRCS INC CPI BRNE FIN:

R20, 0x68 R21, 0 R20 FIN R21 R21,8 AGAIN

;set a counter to 0 ;move MSB to Carry ;branch if carry is one ;increment the counter ;Is there any other bit ;Jump AGAIN ;R21 is the position and is ;9 if there is no 1

28. ;set a counter to 0 ;move MSB to Carry ;branch if carry is one ;increment the counter ;is there any other bit ;jump AGAIN ;R21 is the position and is ;9 if there is no 1

SECTION 5.5: BCD AND ASCII CONVERSION 29. (a) LDI MOV ANDI ORI MOV SWAP ANDI ORI

R20,0x76 R21,R20 R21,0x0F R21,0x30 R22,R20 R22 R22,0x0F R22,0x30

;the packed BCD to be converted is 76 ;R21 = R20 = 76H ;mask the upper nibble (R21 = 06H) ;make it ASCII (R21 = 39H) ;R22 = R20 = 76H ;swap nibbles (R22 = 67H) ;mask the upper nibble (R22 = 07) ;make it ASCII (R22 = 37H)

LDI MOV ANDI ORI MOV SWAP ANDI ORI

R20,0x87 R21,R20 R21,0x0F R21,0x30 R22,R20 R22 R22,0x0F R22,0x30

;the packed BCD to be converted is 87 ;R21 = R20 = 87H ;mask the upper nibble (R21 = 07H) ;make it ASCII (R21 = 37H) ;R22 = R20 = 87H ;swap nibbles (R22 = 78H) ;mask the upper nibble (R22 = 08) ;make it ASCII (R22 = 38H)

(b)

.

33

30.

.

LDI LDI ANDI SWAP

R21,'3' R22,'2' R21,0x0F R21

ANDI OR MOV

R22,0x0F R22,R21 R20,R22

;load character 3 (0x33) to R21 ;load character 2 (0x32) to R22 ;mask upper nibble of R21 ;swap nibbles of R21 ;to make upper nibble of packed BCD ;mask upper nibble of R22 ;join R22 and R21 to make packed BCD ;move the result to R20

34

CHAPTER 6: AVR ADVANCED ASSEMBLY LANGUAGE PROGRAMMING SECTION 6.1: INTRODUCING SOME MORE ASSEMBLER DIRECTIVES 1. R20 = (0x20 & 0x6F) | 0x14 = (0x20) | 0x14 = 0x34 R21 = 0x6F – (0x20 + 0x14) = 0x6F – 0x34 = 0x3B

2. R30 = LOW (0x100<<1) = LOW(0x200) = 00 R31 = HIGH (0x100<<1) = HIGH (0x200) = 0x2 R20 = 20

SECTION 6.2: REGISTER AND DIRECT ADDRESSING MODES 3. (b) and (c) 4. (a) I/O direct addressing (c) Direct addressing (e) two-register addressing 5.

Symbol PORTB PORTC DDRC DDRD SPL SPH SREG

(b) Single register (immediate) addressing (d) two-register addressing

I/O address $18 $15 $14 $11 $3D $3E $3F

Data memory address $38 $35 $34 $31 $5D $5E $5F

6.

7.

8.

9.

I/O direct It stores the content of R20 in location 0xF0 of the data memory.

It loads the PORTC register with the contents of R19. $60 to $085F $60 + 2048 – 1 = 2143 = $085F 10. $60 to $045F $60 + 1024 – 1 = 1119 = $45F 11. .INCLUDE “M32DEF.INC” LDI R16, 6 LDI R17, 9 ADD R16, R17 LDI R17, 2 ADD R16, R17 LDI R17, 5 ADD R16, R17 LDI R17, 7 ADD R16, R17 STS $200, R16

.

35

SECTION 6.3: REGISTER INDIRECT ADDRESSING MODE 12. X, Y, and Z LDI XL, LOW(ourAddress) LDI XH, HIGH(ourAddress) LDI YL, LOW(ourAddress) LDI YH, HIGH(ourAddress) LDI ZL, LOW(ourAddress) LDI ZH, HIGH(ourAddress)

13. .INCLUDE "M32DEF.INC" .EQU MEM_ADDR = 0x80 LDI R16, 0xAA LDI R20, 0x20 LDI XH, HIGH(MEM_ADDR) LDI XL, LOW(MEM_ADDR) L1: ST X+, R16 DEC R20 BRNE L1 L2: RJMP L2

14. .INCLUDE "M32DEF.INC" .EQU MEM_ADDR = 0x90 LDI R16, 0 LDI R20, 0xA0 LDI XH, HIGH(MEM_ADDR) LDI XL, LOW(MEM_ADDR) L1: ST X+, R16 DEC R20 BRNE L1 L2: RJMP L2

15. .INCLUDE "M32DEF.INC" .EQU MEM_ADDR1 = 0x80 .EQU MEM_ADDR2 = 0x90 LDI R20, 10 LDI XH, HIGH(MEM_ADDR1) LDI XL, LOW(MEM_ADDR1) LDI YH, HIGH(MEM_ADDR2) LDI YL, LOW(MEM_ADDR2) L1: LD R16,X+ ST Y+, R16 DEC R20 BRNE L1 L2: RJMP L2

.

36

16. .INCLUDE "M32DEF.INC" .EQU MEM_ADDR = 0x80 LDI R20, 0x10 LDI XH, HIGH(MEM_ADDR) LDI XL, LOW(MEM_ADDR) L1: LD R16, X COM R16 ST X+, R16 DEC R20 BRNE L1 L2: RJMP L2

SECTION 6.4: LOOK-UP TABLE AND TABLE PROCESSING 17.

Location 200 201 202 203 204 205 206 207 208 209

High byte $61 $74 $00 $38 $2D $35 $41 $45 $20 $38

Low byte $45 $72 $68 $39 $37 $36 $47 $42 $48 $39

18.

.

37

Location $340 $341 $342

High byte $56 $20 $FB

Low byte $22 $99 $F6

19. Z LDI ZH, HIGH(OUR_DATA<<1) LDI ZL, LOW(OUR_DATA<<1) LPM R20, Z OUR_DATA: .DB “Our Data”

20. 16 bits, it can cover up to 64 kilobytes.

21. .EQU

MEM_ADDR = 0x200 LDI ZH, HIGH(MEM_ADDR<<1) LDI ZL, LOW(MEM_ADDR<<1) LPM R20, Z

.EQU

MEM_ADDR = 0x340 LDI ZH, HIGH((MEM_ADDR<<1)|1) LDI ZL, LOW((MEM_ADDR<<1)|1) LPM R20, Z

22.

23. .INCLUDE "M32DEF.INC" .EQU RAM_ADDR = 0x60 LDI R16, 0 LDI R20, 0xA0 LDI ZH, HIGH(MY_DATA<<1) LDI ZL, LOW(MY_DATA<<1) LDI XH, HIGH(RAM_ADDR) LDI XL, LOW(RAM_ADDR) L1: LPM R16, Z+ ST X+, R16 CPI R16, 0 BRNE L1 L2: RJMP L2 .ORG 0x600 MY_DATA: .DB "1-800-999-9999", 0

24. .INCLUDE "M32DEF.INC" LDI ZH, HIGH(LOOKUP<<1) LDI ZL, LOW(LOOKUP<<1) ADD ZL, R16 LPM R20, Z ;R20 = y = R16^2 + 2*R16 + 5 HERE: RJMP HERE .ORG 0x100 LOOKUP: .DB 5, 8, 13, 20, 29, 40, 53, 68, 85, 104

.

38

25. .INCLUDE "M32DEF.INC" LDI LDI ADD LPM HERE: RJMP

ZH, HIGH(LOOKUP<<1) ZL, LOW(LOOKUP<<1) ZL, R16 R20, Z HERE

.ORG 0x100 LOOKUP: .DB 5, 25, 45, 65, 85, 105, 125, 145, 165, 185

26. .INCLUDE "M32DEF.INC" .EQU RAM_ADDR = 40 LDI R16, 0 LDI R20, 0xA0 LDI ZH, HIGH(MY_DATA<<1) LDI ZL, LOW(MY_DATA<<1) LDI XH, HIGH(RAM_ADDR) LDI XL, LOW(RAM_ADDR) L1: LPM R16, Z+ ST X+, R16 CPI R16, 0 BRNE L1 L2: RJMP L2 .ORG 0x700 MY_DATA: .DB "The earth is but one country", 0

27. True 28. False 29. .INCLUDE "M32DEF.INC" LDI R16, 0xFF OUT DDRC, R16 LDI R16, 0x00 OUT DDRB, R16 LDI ZH,HIGH(LOOKUP<<1) L1: LDI ZL,LOW(LOOKUP<<1) IN R16, PINB ANDI R16,0x0F ADD ZL,R16 LPM R20,Z OUT PORTC, R20 RJMP L1 .ORG 0x100 LOOKUP: .DB '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'

.

39

SECTION 6.5: BIT-ADDRESSABILITY 30. .INCLUDE "M32DEF.INC" LDI R16, HIGH(RAMEND) OUT SPH, R16 LDI R16, LOW(RAMEND) OUT SPL, R16 SBI DDRB, 5 L1: SBI PORTB, 5 CALL DELAY CALL DELAY CALL DELAY CBI PORTB, 5 CALL DELAY RJMP L1

31. .INCLUDE "M32DEF.INC" LDI R16, HIGH(RAMEND) OUT SPH, R16 LDI R16, LOW(RAMEND) OUT SPL, R16 SBI DDRC, 7 L1: SBI PORTC, 7 CALL DELAY CALL DELAY CALL DELAY CALL DELAY CBI PORTC, 7 CALL DELAY RJMP L1

32. .INCLUDE "M32DEF.INC" LDI R16, HIGH(RAMEND) OUT SPH, R16 LDI R16, LOW(RAMEND) OUT SPL, R16 CBI DDRB, 4 SBI DDRB, 7 L1: SBIS PINB, 4 RJMP L1 SBI PORTB, 7 CALL DELAY CBI PORTB, 7 CALL DELAY RJMP L1

.

40

33. .INCLUDE "M32DEF.INC" LDI R16, HIGH(RAMEND) OUT SPH, R16 LDI R16, LOW(RAMEND) OUT SPL, R16 CBI DDRC, 1 LDI R20,0xFF OUT DDRD, R20 L1: SBIC PINC, 1 RJMP L1 LDI R20, 0x55 OUT PORTD, R20 L2: RJMP L2

34. SREG 35. bit 1 36. a. valid, PB1 b. invalid, we should write CBI PORTC,3 instead c. invalid d. valid, bit 0 of R20 e. invalid f. valid, bit 3 of R20 is stored in the T flag g. invalid h. valid, the N flag is cleared 37. valid 38. all of them 39. none of them 40. CLC 41. BRCS 42. BREQ 43. Bits 0, 1, 5, and 3 are assigned to C, Z, H, and V, respectively.

44. False, the lower 32 I/O registers are bit addressable.

45.

IN BST LDS BLD STS

R16, SREG R16, SREG_C R16, 0x60 R16, 4 0x60, R16

;T = C ;R16 = [0x60] ;R16.4 = T ;[0x60] = R16

IN BST LDS BLD STS

R16, SREG R16, SREG_H R16, 0x160 R16, 2 0x160, R16

;T = H ;R16 = [0x160] ;R16.2 = T ;[0x160] = R16

IN BST LDS BLD STS

R16, SREG R16, SREG_Z R16, 0x120 R16, 7 0x120, R16

;T = Z ;R16 = [$120] ;R16.7 = T ;[$120] = R16

46.

47.

.

41

48.

MOV R16, R20 ANDI R16, 0x03 CPI R16, 0 BRNE ARE_NOT_LOW ASR R20 ASR R20 ARE_NOT_LOW: …

49.

LDI OUT BST BRTC LDI OUT NOT_HIGH:

R20, 0xFF DDRD, R20 R25, 7 NOT_HIGH R20, 0xFF PORTD, R20

50. a.

LDI OUT

R20, 0xFF PORTC, R20

SBI SBI SBI SBI SBI SBI SBI SBI

PORTC, 0 PORTC, 1 PORTC, 2 PORTC, 3 PORTC, 4 PORTC, 5 PORTC, 6 PORTC, 7

b.

51.

MOV R20, R24 ANDI R20, 0x07 CPI R20, 0 BRNE NOT_DIVISIBLE DIVISIBLE: …

NOT_DIVISIBLE: …

SECTION 6.6: ACCESSING EEPROM IN AVR 52. .INCLUDE "M32DEF.INC" LDI R20, HIGH(RAMEND) OUT SPH, R20 LDI R20, LOW(RAMEND) OUT SPL, R20

L1:

.

LDI R20, 0 ;loaded into EEPROM LDI R16, $30 ;counter LDI XH, HIGH (EE_MEM) ;X points to location 0 of EEPROM LDI XL, LOW (EE_MEM) RCALL STORE_IN_EEPROM ;store R20 in location X of EEPROM INC XL ;X points to next memory location

42

DEC BRNE HERE: RJMP

R16 L1 HERE

;decrement counter ;if R16 is not zero go to L1

STORE_IN_EEPROM: SBIC EECR, EEWE RJMP STORE_IN_EEPROM OUT EEARH, XH OUT EEARL, XL OUT EEDR, R20 SBI EECR, EEMWE SBI EECR, EEWE RET .ESEG .ORG 0 EE_MEM: .DB 0

53. .INCLUDE "M32DEF.INC" .EQU RAM_ARRAY = 0x80 LDI OUT LDI OUT

R20,HIGH(RAMEND) SPH,R20 R20,LOW(RAMEND) SPL,R20

LDI R16, 10 ;counter LDI ZH, HIGH(RAM_ARRAY) ;Z points to RAM_ARRAY of RAM LDI ZL, LOW(RAM_ARRAY) LDI XH, HIGH(EE_MEM) ;X points to EE_MEM of EEPROM LDI XL, LOW(EE_MEM) L1: LD R20, Z+ RCALL STORE_IN_EEPROM ;store R20 in location X of EEPROM INC XL ;X points to next memory location DEC R16 ;decrement counter BRNE L1 ;if R16 is not zero go to L1 HERE: RJMP HERE STORE_IN_EEPROM: SBIC EECR, EEWE RJMP STORE_IN_EEPROM OUT EEARH, XH OUT EEARL, XL OUT EEDR, R20 SBI EECR, EEMWE SBI EECR, EEWE RET .ESEG .ORG $10 EE_MEM: .DB 0

.

43

54. .INCLUDE "M32DEF.INC" .EQU RAM_ARRAY = 0x80 LDI R20,HIGH(RAMEND) OUT SPH,R20 LDI R20,LOW(RAMEND) OUT SPL,R20 LDI

R16, 10

;counter

LDI LDI

ZH, HIGH(RAM_ARRAY) ZL, LOW(RAM_ARRAY)

;Z points to RAM_ARRAY of RAM

LDI XH, HIGH(EE_MEM) ;X points to EE_MEM of EEPROM LDI XL, LOW(EE_MEM) L1: RCALL LOAD_FROM_EEPROM ;load R20 with contents of location X ST Z+, R20 INC XL ;X points to next memory location DEC R16 ;decrement counter BRNE L1 ;if R16 is not zero go to L1 HERE: RJMP HERE LOAD_FROM_EEPROM: SBIC EECR, EEWE RJMP LOAD_FROM_EEPROM OUT EEARH, XH OUT EEARL, XL SBI EECR, EERE IN R20, EEDR RET .ESEG .ORG $10 EE_MEM: .DB 0

55. .INCLUDE "M32DEF.INC" LDI R20, HIGH (RAMEND) OUT SPH, R20 LDI R20, LOW (RAMEND) OUT SPL, R20 LDI

R16, $10

LDI LDI

R17, 0 R18, 0

;counter

LDI XH, HIGH ($10) ;X points to location $10 of EEPROM LDI XL, LOW ($10) L1: RCALL LOAD_FROM_EEPROM ;load R20 with contents of location X ADD R17, R20 BRCC L2 INC R18 L2: INC XL ;X points to next memory location DEC R16 ;decrement counter BRNE L1 ;if R16 is not zero go to L1 HERE: RJMP HERE

.

44

LOAD_FROM_EEPROM: SBIC EECR, EEWE RJMP LOAD_FROM_EEPROM OUT EEARH, XH OUT EEARL, XL SBI EECR, EERE IN R20, EEDR RET

SECTION 6.7: CKECKSUM AND ASCII SUBROUTINES 56.

Character H Hex 48

e 65

l 6C

L 6C

o 6F

$48 +$65 +$6C +$6C +$6F 1 F4 Î dropping the carry of 1, we have $F4. Its 2’s complement is $0C. Therefore, the checksum byte is $0C. 57. a. $65 + $09 + $95 + $23 = 1 26 Î it is other than 0. Therefore it is corrupted. b. $71 + $69 + $38 + $81 + $6D = 2 00 Î It is 0. Therefore, it is not corrupted.

58. True 59. .include "m32def.inc" .EQU RAM_BUFFER = 0x80 LDI OUT LDI OUT

L1:

.

LDI LDI

R20, HIGH (RAMEND) SPH, R20 R20, LOW (RAMEND) SPL, R20 ;Z points to OUR_DATA of Flash ROM ZH, HIGH(OUR_DATA<<1) ZL, LOW(OUR_DATA<<1)

LDI LDI

XH, HIGH(RAM_BUFFER) XL, LOW(RAM_BUFFER)

LPM ST CPI BRNE

R20, Z+ X+, R20 R20, 0 L1

LDI CALL

R16, 31 CAL_CHKSUM

;X points to RAM_BUFFER of RAM

45

LDI CALL TST BREQ CORRUPTED:

R16, 32 TEST_CHKSUM R20 NOT_CORRUPTED

NOT_CORRUPTED: L2: RJMP

L2

;-------calculating checksum byte CAL_CHKSUM: LDI YL,LOW(RAM_BUFFER) LDI YH,HIGH(RAM_BUFFER) ;Y points to RAM_BUFFER LDI R20,0 ;SUM = 0 CL1: LD R17,Y+ ;load R17 with contents of loc Y ADD R20,R17 ;SUM = SUM + R17 DEC R16 ;Decrement COUNTER BRNE CL1 ;loop while COUNTER is not zero NEG R20 ;two's complement SUM ST Y,R20 ;Store checksum in loc Y of RAM RET ;return ;-------testing checksum byte TEST_CHKSUM: LDI YL,LOW(RAM_BUFFER) LDI YH,HIGH(RAM_BUFFER) ;Y points to RAM_OPTIONS LDI R20,0 ;SUM = 0 TL1: LD R17,Y+ ;load R17 with contents of loc Y ADD R20,R17 ;SUM = SUM + R17 DEC R16 ;Decrement COUNTER BRNE TL1 ;if COUNTER is not zero goto TL1 RET OUR_DATA: .DB "Hello, my fellow world citizens", 0

60. ASCII 61. .INCLUDE "M32DEF.INC" .EQU RAM_BUFFER = 0x140

L1:

.

LDI LDI LDI LDI

ZH, HIGH(MYDATA<<1) ZL, LOW(MYDATA<<1) XH, HIGH(RAM_BUFFER) XL, LOW(RAM_BUFFER)

LDI LPM MOV

R16, 4 R20, Z+ R21, R20

ANDI ORI ST

R20,0x0F R20,0x30 X+,R20

SWAP ANDI ORI

R21 R21,0x0F R21,0x30

46

ST

X+,R21

DEC BRNE RJMP

R16 L1 L2

.ORG MYDATA:

$700 .DB

L2:

$76, $87, $98, $43

62. .INCLUDE "M32DEF.INC" .EQU RAM_BUFFER = 0x60 LDI LDI LDI LDI

ZH, HIGH(MYDATA<<1) ZL, LOW(MYDATA<<1) XH, HIGH(RAM_BUFFER) XL, LOW(RAM_BUFFER)

LDI

R16, 4

LPM LPM

R20, Z+ R21, Z+

ANDI ANDI SWAP OR ST

R20,0x0F R21,0x0F R21 R20, R21 X+,R20

DEC BRNE RJMP

R16 L1 L2

.ORG $300 MYDATA:

.DB

L1:

L2:

"87675649"

63. .INCLUDE "M32DEF.INC" .DEF NUM = R20 .DEF DENOMINATOR = R21 .DEF QUOTIENT = R22 .EQU

.

ASCII_RESULT = 0x60 LDI R20, HIGH (RAMEND) OUT SPH, R20 LDI R20, LOW (RAMEND) OUT SPL, R20 LDI LDI

XH,HIGH(ASCII_RESULT) XL,LOW(ASCII_RESULT)

LDI OUT LDI OUT

R16,0x00 DDRD, R16 R16,0xFF PORTD, R16

47

NOP IN

NUM,PIND

LDI DENOMINATOR, 10 RCALL DIVIDE ORI NUM, 0x30 ST X+,NUM MOV NUM,QUOTIENT RCALL DIVIDE ORI NUM, 0x30 ST X+, NUM ORI QUOTIENT,0x30 ST X+,QUOTIENT L2:

RJMP

DIVIDE: LDI L1: INC SUB BRCC DEC ADD RET

L2 QUOTIENT,0 QUOTIENT NUM, DENOMINATOR L1 QUOTIENT NUM,DENOMINATOR

SECTION 6.8: MACROS 64.

1) The programs using MACROs are more readable.

2) MACROs do not use stacks and are not at the risk of stack overflow in nested form.

65. A MACRO - Because MACROs are replaced with their corresponding instructions in assembling process.

.

48

CHAPTER 7: AVR PROGRAMMING IN C SECTION 7.1: DATA TYPES AND TIME DELAYS IN C 1.

(a) char (d) unsigned char (g) unsigned int

(b) unsigned char (e) unsigned char (h) unsigned char

2.

(a) $0E (d) $07 (g) $FF

3.

(a) Crystal frequency (b) The way the C compiler compiles (depends on the compiler type)

4.

Crystal frequency (also choice over compiler should be taken into consideration)

5.

No, that is an internal factor which is not under programmer’s control. It is determined and designed by the IC designer.

6.

Because in the compilation of the C code into assembly, different compilers use different methods based on their design and optimization which results in different hex file sizes.

(b) $18 (e) $20 (h) $0F

(c) unsigned int (f) unsigned char (i) array of unsigned char

(c) $41 (f) $45

SECTION 7.2: I/O PROGRAMMING IN C 7.

PORTC = 0x00 changes the value of Port C to 0x00 but DDRC = 0x00 changes the direction of Port C to input.

8. #include <avr/io.h> #include <util/delay.h> void main (void) { DDRB = 0xFF; while (1) { PORTB = 0xAA ; _delay_ms(200); PORTB = 0x55; _delay_ms(200); } }

.

49

9. #include <avr/io.h> #include <util/delay.h> void main (void) { DDRB = 0xFF; while (1) { PORTB = PORTB | (1<<1) | (1<<3); _delay_ms(200); PORTB = PORTB & ~ ((1<<1) | (1<<3)); _delay_ms(200); } }

10. void delay100ms(void) { unsigned int j, i; for (i=0 ; i< 450 ; i++) for (j=0 ; j< 100 ; j++); }

11. #include <avr/io.h> #include <util/delay.h> void main (void) { DDRC = 0xFF; while (1) { PORTC = PORTC | (1<<3); _delay_ms(200); PORTC = PORTC & ~ (1<<1); _delay_ms(200); } }

12. #include <avr/io.h> #include <util/delay.h> void main (void) { DDRB = 0xFF; unsigned char i = 0; while (1) { PORTB = i; i ++; if (i > 99) i = 0; } }

.

50

SECTION 7.3: LOGIC OPERATIONS IN C 13. a.

1111 0000 And 0100 0101 0100 0000 = 0x40

b.

1111 0000 And 0101 0110 0101 0000 = 0x50

c.

1111 0000 xor 0111 0110 1000 0110 = 0x86

d.

1111 0000 And 1001 0000 1001 0000 = 0x90

e.

1111 0000 Xor 1001 0000 0110 0000 = 0x60

f.

1111 0000 Or 1001 0000 1111 0000 = 0xF0

g.

1111 0000 And 1111 1111 1111 0000 = 0xF0

h.

1111 0000 Or 1001 1001 1111 1001 = 0xF9

i.

1111 0000 Xor 1110 1110 0001 1110 = 0x1E

j.

1111 0000 Xor 1010 1010 0101 1010 = 0x5A

14. a. 0x65&0x76 0110 0101 And 0111 0110 0110 0100 = 0x64

b. 0x70|0x6B 0111 0000 Or 0110 1011 0111 1011 = 0x=7B

c. 0x95^0xAA 1001 0101 Xor 1010 1010 0011 1111 = 0x3F

d. 0x5D&0x78 0101 1101 And 0111 1000 0101 1000 = 0x58

e. 0xC5|0x12 1100 0101 Or 0001 0010 1101 0111 = 0xD7

f. 0x6A^0x6E 0110 1010 Xor 0110 1110 0000 0100 = 0x04

g. 0x37|0x26 0011 0111 Or 0010 0110 0011 0111 = 0x37

15. a. 0x65>>2 0110 0101 >>2 0001 1001 = 0x19

b. 0x39<<2 0011 1001 <<2 1110 0100 = 0xE4

c. 0xD4>>3 1101 0100 >>3 0001 1010 = 0x1A

d. 0xA7<<2 1010 0111<<2 1001 1100 = 0x9C

16. #include <avr/io.h> unsigned char swap(unsigned char a) { unsigned char t= 0; t = a & 0x0F;

.

51

}

t = t << 4; a = a >> 4; return ( a | t );

void main (void) { unsigned char i; i = swap (0x95); }

17. unsigned char findZero(unsigned char a) { unsigned char i, count = 0; for ( i = 0 ; i <8 ; i++) { if ( (a & 0x01) == 0 ) count ++ ; a = a >> 1; } }

return ( count );

SECTION 7.4: DATA CONVERSION PROGRAMS IN C 18. #include <avr/io.h>

//standard AVR header

int main(void) { unsigned char x, y; unsigned char mybyte = 0x34; DDRB = DDRC = 0xFF; x = mybyte & 0x0F; PORTB = x | 0x30; y = mybyte & 0xF0; y = y >> 4; PORTC = y | 0x30; }

//make port B and C output //mask upper 4 bits //make it ASCII //mask lower 4 bits //shift it to lower 4 bits //make it ASCII

return 0;

19. #include <avr/io.h>

//standard AVR header

int main(void) { unsigned char bcdbyte; unsigned char w = '7'; unsigned char z = '2';

.

52

DDRB = 0xFF; w = w & 0x0F; w = w << 4; z = z & 0x0F; bcdbyte = w | z; PORTB = bcdbyte; }

//make Port B an output //mask 3 //shift left to make upper BCD digit //mask 3 //combine to make packed BCD

return 0;

20. #include <avr/io.h>

//standard AVR header

int main(void) { unsigned char abyte = 0b01001101; unsigned char i = 0 ; unsigned char ones = 0; while (abyte != 0 ) { if ((abyte & 0x01 ) != 0) ones ++ ; abyte = abyte >> 1 ; } }

return 0;

SECTION 7.6: MEMORY ALLOCATION IN C 21.

22.

23.

24.

25.

(a) data SRAM (b) code space (c) code space (d) code space False 1) saving data RAM space (this type of data usually needs a lot of space).

2) They are usually fixed. We use ROM to save fixed data and RAM to store variable data.

1) Much more storage space 2) Not occupying RAM space which may be needed for storing some essential data 1) Data stored in ROM space can not be changed unless with re-programming.

2) The more code space we use for data, the less is left for instructions.

26. #include <avr/io.h>

//Standard AVR header

void eepromWrite (unsigned int pos, unsigned char data ) { while(EECR & (1<<EEWE)); //wait for last write to finish

}

.

EEAR = pos; EEDR = data; EECR |= (1<<EEMWE); EECR |= (1<<EEWE);

//Write low byte to address register //Write data to data register //Write one to EEMWE //Start eeprom write

53

int main(void) { unsigned char str[] = "Sarmad"; unsigned char i = 0; while (str[i] != '\0') { eepromWrite(i,str[i]); i++ ; } }

return 0;

27.

28.

29.

30.

.

(a) data SRAM (b) data SRAM (c) data SRAM (d) data SRAM (e) code space 1) Saving data RAM space (this type of data usually needs a lot of space).

2) They are usually fixed. We use ROM to save fixed data and RAM to store variable data.

Occupying RAM space which may be needed for storing some essential data It is not fixed and can be changed during the execution of the code

54

CHAPTER 8: AVR HARDWARE CONNECTION SECTION 8.1: ATMEGA32 PIN CONNECTION 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

40 pin pins 10 and 30 are assigned to VCC and pins 11 and 31 are assigned to GND 32 12 and 13 False 9 High, Low 2 2 True input 8 (40 – 33) 8 (1 – 8) 8 (22 – 29) 8 (14 – 21) Input

SECTION 8.2: AVR FUSE BITS 17.

18.

19.

20.

21.

22.

23.

24.

25.

5 (External RC Oscillator, External Clock, Crystal Oscillator, Low-Frequency Crystal Resonator, Calibrated RC Oscillator CKSEL3…0 External RC oscillator Internal RC oscillator Crystal oscillator 2 fuse bytes BODLEVEL BODEN It means that the system will reset if the VCC level falls bellow 4V

SECTION 8.3: EXPLAINING THE INTEL HEX FILE FOR AVR 26.

27.

28.

29.

.

True True True After ‘:’ the record starts with 10, which means that the data field contains 10 (16 decimal) bytes of data. The next field is the address field (0010), and it indicates that the first byte of the data field will be placed in address location 16 in the current segment. So the first byte of code will be loaded into location 0 of Flash memory.

The next field is the data field, which contains the code to be loaded into the chip.

The last field of the record is the checksum byte of the record. Notice that the checksum byte at the end of each line represents the checksum byte for everything in that line, and not just for the data portion.

55

30.

31.

10+00+10+00+08+BB+0E+94+0C+00+FB+CF+40+E1+58+EC+6A+EF+00+00+E7 = 800. Dropping the 8 will leave 00. It shows that the information is not corrupted.

Extended Intel Hex files can be used for ROM size of more than 64 kilobytes

SECTION 8.4: AVR PROGRAMMIN AND TRAINER BOARD 32.

33.

34.

35.

.

True True Parallel programming, ISP (in circuit serial programming), Boot loader False

56

CHAPTER 9: AVR TIMER PROGRAMMING IN ASSEMBLY AND C SECTION 9.1: PROGRAMMING TIMERS 0, 1, AND 2 1. three timers 2. 8, TCNT0 3. 16, TCNT1H, TCNT1L 4. 1024 5. 1024 6. 8 7. It is used for control of Timer0.

8. False 9. False 10. TCCR0=00000001=0x01 11. (a) frequency = 8 MHz (b) frequency = 16 MHz (c) frequency = 1 MHz (d) frequency = 10 MHz

period = 1 / (8 MHz) = 0.125 µs period = 1 / (16 MHz) = 0.0625 µs period = 1 / (1 MHz) = 1 µs period = 1 / (10 MHz) = 0.1 µs

12. TIFR 13. (a) $FF to $00 or 255 to 0 (b) $FFFF to $0000 or 65535 to 0 14. (a) When the timer reaches the value $FF and rolls over, the TOV0 flag is raised. (b) When the timer reaches the value $FFFF and rolls over, the TOV1 flag is raised.

15. True 16. True 17. frequency = 8 MHz. Now with no prescaler, we have 8 MHz. The period is = 1 / 8 MHz = 0.125 µs. Now 20 µs/0.125 µs = 160. Therefore TCNT0 = 256 – 160 = 96 18. frequency = 8 MHz. The period is = 1 / 8 MHz = 0.125 µs. Now 5 ms/0.125 µs = 40,000.

The largest possible prescaler is 1024. 40,000 / 1024 = 39.

Therefore TCNT0 = 256 – 39 = 217.

19. frequency = 1 MHz. The period is = 1 / 1 MHz = 1 µs. Now 2.5 ms / 1 µs = 2,500. Therefore TCNT1 = 65,536 – 2,500 = 63,036.

20. frequency = 1 MHz. The period is = 1 / 1 MHz = 1 µs. Now 0.2 ms / 1 µs = 200. Therefore OCR0 = 200 – 1 = 199.

21. frequency = 1 MHz. The period is = 1 / 1 MHz = 1 µs. Now 2 ms / 1 µs = 2000. Therefore OCR1 = 2000 – 1 = 1999.

22. frequency = 8 MHz. Now with prescaler of 1024, we have 8 MHz / 1024 = 7812.5 Hz. The period is = 1 / 7812.5 Hz = 0.128 ms. Now t = 0.128 ms × 65536 = 8.388608. Therefore the lowest frequency = 1 / T = 1/2t = 1/16.777216 = 0.0596 Hz 23. frequency = 8 MHz. Now, with the prescaler of 1, we have 8MHz/1 = 8MHz. The period is 1 / 8 MHz = 0.125 µs. Now, the highest Freq = 1 / (2 x 0.125 µs x 1) = 4 MHz. 24. frequency = 8 MHz. Now with prescaler of 1024, we have 8 MHz / 1024 = 7812.5 Hz. The period is = 1 / 7812.5 Hz = 0.128 ms. Now t = 0.128 ms × 256 = 32.768 ms. Therefore the lowest frequency = 1 / T = 1/2t = 1/ 65.536 = 15.259 Hz

.

57

frequency = 8 MHz. Now, with the prescaler of 1, we have 8MHz/1 = 8MHz. The period is 1 / 8 MHz = 0.125 µs. Now, the highest Freq = 1 / (2 x 0.125 µs x 1) = 4 MHz.

25. $F2, $F3, $F4, $F5, $F6, $F7, $F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF, $00 15 states

26. 1 / 1 kHz = 1 ms. Now 1 ms / 2 = 500 µs.

Scaler Timer Clock Timer Period None 8 MHz 1 / 8 MHz = 0.125 µs 8 8 MHz/8 = 1 MHz 1 / 1 MHz = 1 µs 8 MHz / 64 = 125 kHz 1 / 125 kHz = 8 µs 64 256 8 MHz / 256 = 31.25 kHz 1 / 31.25 kHz = 32 µs 1024 8 MHz / 1024 = 7812.5 Hz 1 / 7812.5 Hz = 128 µs

Timer value 500 µs / 0.125 µs = 4000 500 µs / 1 µs = 500 500 µs / 8 µs = 62.5 500 µs / 32 µs = 15.62 500 µs / 128 µs = 3.9

.INCLUDE "M32DEF.INC"

L1:

LDI OUT LDI OUT

R20, HIGH(RAMEND) SPH, R20 R20, LOW(RAMEND) SPL, R20

SBI SBI CALL CBI CALL RJMP

DDRB, 0 PORTB, 0 DELAY PORTB, 0 DELAY L1

DELAY:LDI OUT LDI OUT LDI OUT DELAY_L1: IN SBRS RJMP

R20, -62 TCNT0, R20 R20, (1<<TOV0) TIFR, R20 R20, 0x03 TCCR0, R20

LDI OUT LDI OUT RET

R20, 0 TCCR0, R20 R20, (1<<TOV0) TIFR, R20

R20,TIFR R20, TOV0 DELAY_L1

27. 1 / 3 kHz = 0.333 ms = 333 µs. Now 333 µs / 2 = 166.5 µs.

Scaler Timer Clock Timer Period None 8 MHz 1 / 8 MHz = 0.125 µs 8 8 MHz/8 = 1 MHz 1 / 1 MHz = 1 µs 64 8 MHz / 64 = 125 kHz 1 / 125 kHz = 8 µs 256 8 MHz / 256 = 31.25 kHz 1 / 31.25 kHz = 32 µs 1024 8 MHz / 1024 = 7812.5 Hz 1 / 7812.5 Hz = 128 µs

.

Timer value 166.5 µs / 0.125 µs = 1332 166.5 µs / 1 µs = 166.5 166.5 µs / 8 µs = 20.8 166.5 µs / 32 µs = 15.62 166.5 µs / 128 µs = 3.9

58

.INCLUDE "M32DEF.INC" LDI R20, HIGH(RAMEND) OUT SPH, R20 LDI R20, LOW(RAMEND) OUT SPL, R20 SBI DDRB, 0 L1: SBI PORTB, 0 CALL DELAY CBI PORTB, 0 CALL DELAY RJMP L1 DELAY: LDI OUT LDI OUT LDI OUT LDI OUT LDI OUT DELAY_L1: IN SBRS RJMP LDI OUT LDI OUT RET

R20, HIGH(-1332) TCNT1H, R20 R20, LOW(-1332) TCNT1L, R20 R20, (1<<TOV1) TIFR, R20 R20, 0x00 TCCR1A, R20 R20, 0x01 TCCR1B, R20 R20,TIFR R20, TOV1 DELAY_L1 R20, 0 TCCR1B, R20 R20, (1<<TOV1) TIFR, R20

28. (a) Timer0 is 8-bit whereas Timer1 is 16-bit. (b) Timer0 has one control register but Timer1 has two control registers (TCCR1A and TCC1B) (c) Timer0 can work in four modes while Timer1 has 16 different modes.

29. (a) – 12 = 0xF4 = 244 (b) – 22 = 0xEA = 234 (c) – 34 = 0xDE = 222 (d) – 92 = 0xA4 = 164 (e) – 120 = 0x88 = 136 (f) – 104 = 0x98 = 152

SECTION 9.2: COUNTER PROGRAMMING 30. CS02–CS00, 110 or 111 31. Yes 32. T0 which is PORTB.0 in ATmega32 33. T1 which is PORTB.1 in ATmega32

.

59

34.

.INCLUDE "M32DEF.INC" LDI R20, HIGH(RAMEND) OUT SPH, R20 LDI R20, LOW(RAMEND) OUT SPL, R20

L1:

35.

CBI SBI

DDRB, 1 PORTB, 1

LDI OUT OUT

R20, 0xFF DDRC, R20 DDRD, R20

LDI OUT LDI OUT

R20, HIGH(20000) TCNT1H, R20 R20, LOW(20000) TCNT1L, R20

LDI OUT LDI OUT IN OUT IN OUT RJMP

R20, 0x00 TCCR1A, R20 R20, 0x07 TCCR1B, R20 R20, TCNT1L PORTD, R20 R20, TCNT1H PORTC, R20 L1

.INCLUDE "M32DEF.INC" LDI R20, HIGH(RAMEND) OUT SPH, R20 LDI R20, LOW(RAMEND) OUT SPL, R20

L1:

CBI SBI LDI OUT

DDRB, 0 PORTB, 0 R20, 0xFF DDRC, R20

LDI OUT LDI OUT IN OUT RJMP

R20, 20 TCNT0, R20 R20, 0x07 TCCR0, R20 R20, TCNT0 PORTC, R20 L1

SECTION 9.3: PROGRAMMING TIMERS IN C 36. 1 / 1 kHz = 1 ms. Now 1 ms / 2 = 500 µs.

.

60

Scaler None 8 64 256 1024

Timer Clock 1 MHz 1 MHz/8 = 125 kHz 1 MHz / 64 = 15.625 kHz 1 MHz / 256 = 3.90 kHz 1 MHz / 1024 = 976.5 Hz

Timer Period 1 / 1 MHz = 1 µs 1 / 125 kHz = 8 µs 1 / 15.625 kHz = 64 µs 1 / 3.9 kHz = 256 µs 1 / 976.5 Hz = 1024 µs

Timer value 500 µs / 1 µs = 500 500 µs / 8 µs = 62.5 500 µs / 64 µs = 7.8125 500 µs / 256 µs = 15.62 500 µs / 1024 µs = 3.9

#include "avr/io.h" void delay_500us ( ); int main () { DDRA = DDRA | 1; while(1) { PORTA = PORTA ^ (1 << PA0); delay_500us (); } }

return 0;

void delay_500us ( ) { TCNT0 = -62; TCCR0 = 0x02; TIFR = (1<<TOV0); while ((TIFR & (1<<TOV0)) == 0);

}

TCCR0 = 0x00; TIFR = (1<<TOV0);

37. 1 / 1 kHz = 1 ms. Now 1 ms / 2 = 500 µs.

Scaler None 8 64 256 1024

Timer Clock 8 MHz 8 MHz/8 = 1 MHz 8 MHz / 64 = 125 kHz 8 MHz / 256 = 31.25 kHz 8 MHz / 1024 = 7812.5 Hz

Timer Period 1 / 8 MHz = 0.125 µs 1 / 1 MHz = 1 µs 1 / 125 kHz = 8 µs 1 / 31.25 kHz = 32 µs 1 / 7812.5 Hz = 128 µs

Timer value 500 µs / 0.125 µs = 4000 500 µs / 1 µs = 500 500 µs / 8 µs = 62.5 500 µs / 32 µs = 15.62 500 µs / 128 µs = 3.9

#include "avr/io.h" void delay_500us ( ); int main () { DDRA = DDRA | 1;

.

61

while(1) { PORTA = PORTA ^ (1 << PA0); delay_500us(); } }

return 0;

void delay_500us ( ) { TCNT1H = (-500)>>8; TCNT1L = (-500)& 0xFF; TCCR1A = 0; TCCR1B = 0x2; TIFR = (1<<TOV1); while ((TIFR & (1<<TOV1)) == 0);

}

TCCR1B = 0x00; TIFR = (1<<TOV1);

38. 1 / 3 kHz = 0.333 ms = 333 µs. Now 333 µs / 2 = 166.5 µs.

Scaler Timer Clock Timer Period None 16 MHz 1 / 16 MHz = 0.0625 µs 8 16 MHz/8 = 2 MHz 1 / 2 MHz = 0.5 µs 64 16 MHz / 64 = 250 kHz 1 / 250 kHz = 4 µs 256 16 MHz / 256 = 62.5 kHz 1 / 62.5 kHz = 16 µs 1024 16 MHz / 1024 = 15625 Hz 1 / 15625 Hz = 64 µs

Timer value 166.5 µs / 0.0625 µs = 2664 166.5 µs / 0.5 µs = 333 166.5 µs / 4 µs = 41.625 166.5 µs / 16 µs = 10.4062 166.5 µs / 64 µs = 2.6015

#include "avr/io.h" void delay_166us ( ); int main () { DDRA = DDRA | 1; while(1) { PORTA = PORTA ^ (1 << PA0); delay_166us(); } }

return 0;

void delay_166us ( ) { TCNT0 = -41; TCCR0 = 0x03; TIFR = (1<<TOV0); while ((TIFR & (1<<TOV0)) == 0);

.

62

}

TCCR0 = 0x00; TIFR = (1<<TOV0);

39. 1 / 3 kHz = 0.333 ms = 333 µs. Now 333 µs / 2 = 166.5 µs.

Scaler None 8 64 256 1024

Timer Clock 10 MHz 10 MHz/8 = 1.25 MHz 10 MHz / 64 = 156.25 kHz 10 MHz / 256 = 39.0625 kHz 10 MHz / 1024 = 9.765 Hz

Timer Period 1 / 10 MHz = 0.1 µs 1 / 1.25 MHz = 0.8 µs 1 / 156.25 kHz = 6.4 µs 1 / 39.0625 kHz = 25.6 µs 1 / 9.765 Hz = 102.4 µs

Timer value 166.5 µs / 0.1 µs = 1665 166.5 µs / 0.8 µs = 208.125 166.5 µs / 6.4 µs = 26.01562 166.5 µs / 25.6 µs = 6.5039 166.5 µs / 102.4 µs = 1.6259

#include "avr/io.h" void delay_166us ( ); int main () { DDRA = DDRA | 1; while(1) { PORTA = PORTA ^ (1 << PA0); delay_166us(); } }

return 0;

void delay_166us ( ) { TCNT1H = (-1665)>>8; TCNT1L = (-1665)& 0xFF; TCCR1A = 0; TCCR1B = 0x1; TIFR = (1<<TOV1); while ((TIFR & (1<<TOV1)) == 0);

}

TCCR1B = 0x00; TIFR = (1<<TOV1);

40. #include "avr/io.h" int main () { DDRC = DDRD = 0xFF; TCNT1 = 20000; TCCR1A = 0;

.

63

TCCR1B = 0x7; while(1) { PORTC = TCNT1L; PORTD = TCNT1H; } }

return 0;

41. #include "avr/io.h" int main () { DDRD = 0xFF; TCNT0 = 20; TCCR0 = 0x7; while(1) { PORTD = TCNT0; } }

.

return 0;

64

Chapter 10: INTERRUPT PROGRAMMING IN ASSEMBLY AND C SECTION 10.1: AVR INTERRUPTS 1. interrupt 2. hardware Reset, timer overflow, timer compare match, hardware external interrupt, USART transmit and receive interrupts, etc 3. $00 to $28 4. True 5. $16 6. $12 7. Yes 8. Yes 9. Status register 10. Because locations $02 to $28 are assigned to interrupt vector.

11. 0, all interrupts are disabled.

12.

LDI OUT SEI

R16, (1<<OCIE0) TIMSK, R16

LDI OUT SEI

R16, (1<<TOIE1) TIMSK, R16

13.

14. TIMSK 15. True 16. CLI 17.

IN ANDI OUT

R16, GICR R16, ~(1<<INT0) GICR, R16

18. False 19. 4 bytes

SECTION 10.2: PROGRAMMING TIMER INTERRUPTS 20. True 21. $0A and $0B 22.

LDI OUT SEI

R16, (1<<TOIE2) TIMSK, R16

LDI OUT SEI

R16, (1<<TOIE0) TIMSK, R16

23. 0

24. The content of TCNT0 increases, at first becoming $E1, then $E2, and so on until the timer reaches $FF and rolls over to zero and the TOV0 flag is set. When TOV0 is set the CPU

.

65

finishes executing the current instruction, pushes the PC register onto the stack, clears the I and the TOV0 flags, and loads PC with $16, since the address of Timer0 overflow interrupt vector is $16. The ISR ends with the RETI instruction causing the CPU to pop the return address from the top of stack.

25. False. The CPU automatically clears the TOV0 flag.

26. The content of TCNT1 increases, at first becoming $100, then $101, and so on until the timer reaches $1F5 and rolls over to zero and the OCF1A flag is set. When OCF1A is set the CPU finishes executing the current instruction, pushes the PC register onto the stack, clears the I and the OCF1A flags, and loads PC with $0E, since the address of Timer1 compare match interrupt vector is $0E. The ISR ends with the RETI instruction causing the CPU to pop the return address from the top of stack.

27. The content of TCNT1 increases, at first becoming $FFE9, then $FFEA, and so on until the timer reaches $FFFF and rolls over to zero and the TOV1 flag is set. When TOV1 is set the CPU finishes executing the current instruction, pushes the PC register onto the stack, clears the I and the TOV1 flags, and loads PC with $12, since the address of Timer1 compare match interrupt vector is $12. The ISR ends with the RETI instruction causing the CPU to pop the return address from the top of stack.

28. To generate a wave with frequency of 1 Hz we need a delay of 0.5 sec.

Scaler Timer Clock Timer Period Timer value None 8 MHz 1 / 8 MHz = 0.125 µs 500 ms / 0.125 µs = 4,000,000 8 8 MHz/8 = 1 MHz 1 / 1 MHz = 1 µs 500 ms / 1 µs = 500,000 64 8 MHz / 64 = 125 kHz 1 / 125 kHz = 8 µs 500 ms / 8 µs = 62,500 256 8 MHz / 256 = 31.25 kHz 1 / 31.25 kHz = 32 µs 500 ms / 32 µs = 15,620 1024 8 MHz / 1024 = 7812.5 Hz 1 / 7812.5 Hz = 128 µs 500 ms / 128 µs = 3900 .INCLUDE "M32DEF.INC" .ORG 0 RJMP MAIN .ORG 0x12 RJMP T1_OVER_ISR MAIN:

.

LDI OUT LDI OUT

R16,HIGH(RAMEND) SPH,R16 R16,LOW(RAMEND) SPL,R16

LDI OUT LDI OUT

R16,HIGH(-62500) TCNT1H,R16 R16,LOW(-62500) TCNT1L,R16

LDI OUT LDI OUT

R16,0x00 TCCR1A,R16 R16,0x02 TCCR1B,R16

LDI OUT SEI

R16, 1<<TOIE1 TIMSK, R16

66

SBI

DDRB, 7

LDI OUT

R16, 0 DDRC, R16

LDI OUT OUT

R16, 0xFF DDRD, R16 PORTC, R16

L1: IN R16, PINC OUT PORTD,R16 RJMP L1 T1_OVER_ISR: LDI R16,HIGH(-62500) OUT TCNT1H,R16 LDI R16,LOW(-62500) OUT TCNT1L,R16 IN LDI EOR OUT RETI

R20, PORTB R21, (1<<PB7) R20, R21 PORTB, R20

29. 1 / 3 kHz = 333 µs. Now 333 µs / 2 = 166 µs.

Scaler Timer Clock Timer Period 1 / 1 MHz = 1 µs None 1 MHz 8 1 MHz/8 = 125 kHz 1 / 125 kHz = 8 µs 64 1 MHz / 64 = 15.625 kHz 1 / 15.625 kHz = 64 µs 256 1 MHz / 256 = 3.90 kHz 1 / 3.9 kHz = 256 µs 1024 1 MHz / 1024 = 976.5 Hz 1 / 976.5 Hz = 1024 µs

Timer value 166 µs / 1 µs = 166 166 µs / 8 µs = 20.75 166 µs / 64 µs = 2.593 166 µs / 256 µs = 0.648 166 µs / 1024 µs = 0.1621

.INCLUDE "M32DEF.INC" .ORG .ORG

0 RJMP 0x14 RJMP

MAIN: LDI OUT LDI OUT

.

MAIN T0_CM_ISR R16,HIGH(RAMEND) SPH,R16 R16,LOW(RAMEND) SPL,R16

LDI OUT

R16,166 OCR0,R16

LDI OUT

R16,0x09 TCCR0,R16

LDI

R16, 1<<OCIE0

67

L1:

OUT SEI

TIMSK, R16

SBI

DDRB, 7

LDI OUT

R16, 0 DDRC, R16

LDI OUT OUT

R16, 0xFF DDRD, R16 PORTC, R16

IN OUT RJMP

R16, PINC PORTD,R16 L1

T0_CM_ISR: IN LDI EOR OUT RETI

R20, PORTB R21, (1<<PB7) R20, R21 PORTB, R20

SECTION 10.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS 30. True 31. $02, $04, and $06 respectively – PD2, PD3, and PB2 respectively.

32. GICR LDI OUT

R16, 1<<INT0 GICR, R16

33. GICR LDI OUT

R16, 1<<INT1 GICR, R16

LDI OUT

R16, (1<<INT0)|(1<<INT1)|(1<<INT2) GICR, R16

34.

35. When the input signal goes from high to low the processor finishes executing the current instruction and jumps to vector address to execute the ISR. 36. False 37. GIFR 38. GIFR 39. The edge interrupt is latched by the AVR and is held by the INTF0 bit of the GIFR register.

This means that when an external interrupt is in an edge-triggered mode, upon triggering an interrupt request, the INTF0 flag will be cleared automatically.

40. Clearing the I-bit makes all the interrupts disabled. Therefore, if the I flag is cleared, interrupts will not be triggered when the interrupt pins are activated.

41. False 42. In falling edge-triggered interrupt, each high-to-low pulse will cause the CPU to execute the ISR. In the level-triggered interrupt a low level pulse will interrupt the CPU causing it to execute the ISR. We must remove the low-level pulse from the interrupt before the execution of the RETI instruction at the end of ISR; otherwise the CPU will be interrupted again.

.

68

43.

LDI OUT

R16, $02 MCUCR, R16

44. True 45. .INCLUDE "M32DEF.INC" .ORG .ORG

0 RJMP 0x02 RJMP

MAIN: LDI OUT LDI OUT

L1:

MAIN INT0_ISR R16,HIGH(RAMEND) SPH,R16 R16,LOW(RAMEND) SPL,R16

LDI OUT LDI OUT CBI SBI

R16, 0xFF DDRC, R16 R16, 0 PORTC, R16 DDRD, 2 PORTD, 2

LDI OUT

R16, 0x02 MCUCR, R16

LDI OUT SEI RJMP

R16, 1<<INT0 GICR, R16

INT0_ISR: IN INC OUT RETI

L1 R20, PORTC R20 PORTC, R20

46. .INCLUDE "M32DEF.INC" .ORG .ORG .ORG

0 RJMP 0x02 RJMP 0x04 RJMP

MAIN: LDI OUT LDI OUT LDI OUT LDI OUT

.

MAIN INT0_ISR INT1_ISR R16,HIGH(RAMEND) SPH,R16 R16,LOW(RAMEND) SPL,R16 R16, 0xFF DDRC, R16 R16, 0 PORTC, R16

69

L1:

CBI SBI CBI SBI SBI LDI OUT

DDRD, 2 PORTD, 2 DDRD, 3 PORTD, 3 DDRD, 7 R16, 0x0A MCUCR, R16

LDI OUT SEI RJMP

R16, (1<<INT0)|(1<<INT1) GICR, R16 L1

INT0_ISR: IN R20, PORTC INC R20 OUT PORTC, R20 RCALL SET_PD7 RETI INT1_ISR: IN R20, PORTC DEC R20 OUT PORTC, R20 RCALL SET_PD7 RETI SET_PD7: CPI R20, 2 BRCS SET_PD7_L1 SBI PORTD,7 RJMP SET_PD7_L2 SET_PD7_L1: CBI PORTD,7 SET_PD7_L2: RET

SECTION 10.4: INTERRUPT PRIORITY IN THE AVR 47. If two interrupts are activated at the same time, the interrupt with the higher priority is served first. The address of external interrupt 1 is $4 while the address of external interrupt 2 is $6; thus, external interrupt 1 has a higher priority, and if both of these interrupts are activated at the same time, external interrupt 1 is served first.

48. The address of Timer1 overflow interrupt is $12 while the address of Timer0 overflow interrupt is $16; thus, Timer1 overflow interrupt has a higher priority, and if both of these interrupts are activated at the same time, Timer1 overflow interrupt is served first.

49. When the AVR begins to execute an ISR, it disables the I bit of the SREG register, causing all the interrupts to be disabled, and no other interrupt occurs while serving the interrupt.

50. True; if we want an interrupt to be served inside an interrupt, we should enable the interrupt manually.

.

70

CHAPTER 11: AVR SERIAL PORT PROGRAMMING IN ASSEMBLY AND C SECTION 11.1: BASICS OF SERIAL COMMUNICATION 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

Parallel False 1010110100 ---> this start bit goes first Mark False. It can be 1 or 2 but we always need stop bit.

7 bit data + 1 stop bit + 1 start bit = 9 bits 2/9 x 100 = 22% False It makes the RS232 standard compatible with TTL logic level.

False 9 pins, since the rest are not involved in data transfer.

False 3: TxD RxD Gnd DTE -to- DTE DCD, RxD, TxD, DTR, Gnd, DSR, RTS, CTS, RI 4,000,000 bits (200 x 80 x 25 x 10) 416.6 seconds

SECTION 11.2: ATMEGA32 CONNECTION TO RS232 17.

18.

19.

20.

21.

22.

23.

24.

25.

.

16 VCC = 16, GND = 15 20 VCC = 7, GND =6 No The MAX233 does not require an external capacitor, but it is more expensive.

2 2

71

26.

27.

28.

It does not need the four capacitors that the MAX232 must have.

Pin 15 – TXD, pin 14 – RXD.

SECTION 11.3: AVR SERIAL PORT PROGRAMMING IN ASSEMBLY 29.

30.

31.

32.

33.

34.

35.

36.

(a), (c), (e), (f) UDR (USART Data Register), UCSRA,UCSRB, UCSRC (USART Control Status Register), and UBRR (USART Baud Rate Register) U2X (Bit1): Double the USART Transmission Speed When you write data to UDR, it will be transferred to the Transmit Data Buffer Register (TXB), and when you read data from UDR, it will return the contents of the Receive Data Buffer Register (RXB).

8 X = (10 MHz/(16(Desired Baud Rate))) – 1 Î X = (625 kHz/(Desired Baud Rate)) – 1. (a) (625 kHz/9600) – 1= 64 = 0x40 (b) (625 kHz/4800) – 1= 129 = 0x81 (c) (625 kHz/1200) – 1= 519 = 0x207 Baud Rate = Fosc/ (16(X + 1)) = 10MHz / (16(15+1)) = 39062 .INCLUDE "M32DEF.INC" LDI R16,(1<<TXEN) ;enable transmitter OUT UCSRB, R16 ; LDI R16,(1<<UCSZ1)|(1<<UCSZ0)|(1<<URSEL) ;8-bit data OUT UCSRC, R16 ;no parity, 1 stop bit LDI R16,64 ;9600 baud rate OUT UBRRL,R16 ;for XTAL = 10 MHz AGAIN: SBIS UCSRA,UDRE ;is UDR empty RJMP AGAIN ;wait more LDI R16,'z' ;send ‘G’ OUT UDR,R16 ;to UDR RJMP AGAIN ;do it again

.

72

37.

This bit is set if parity checking was enabled (UPM1 = 1) and the next character in the receive buffer had a parity error when received.

38.

This flag bit is set when there are new data in the receive buffer that are not read yet. It is cleared when the receive buffer is empty.

39.

This flag is set when the transmit data buffer is empty and you can write new data to it. If this bit is cleared you should not write to UDR because it overrides your last data.

40.

UCSRA.

41.

X = (16 MHz/16(Desired Baud Rate)) – 1 Î X = (1 MHz/(Desired Baud Rate)) – 1. (a) (1 MHz/9600) – 1= 103 (b) (1 MHz/19200) – 1= 51 (c) (1 MHz/38400) – 1= 25 (d) (1 MHz/57600) – 1= 16

42.

X = (16 MHz/8(Desired Baud Rate)) – 1 Î X = (2 MHz/(Desired Baud Rate)) – 1. (a) (2 MHz/9600) – 1= 207 (b) (2 MHz/19200) – 1= 103 (c) (2 MHz/38400) – 1= 51 (d) (2 MHz/57600) – 1= 34

43.

X = (11.0592 MHz/16(Desired Baud Rate)) – 1 Î X = (691200Hz /(Desired Baud Rate)) – 1. (a) (691200Hz/9600) – 1= 71 (b) (691200Hz /19200) – 1= 35 (c) (691200Hz /38400) – 1= 17 (d) (691200Hz /57600) – 1= 11

44.

X = (11.0592MHz/8(Desired Baud Rate)) – 1 Î X = (1382400Hz/(Desired Baud Rate)) – 1. (a) (1382400Hz /9600) – 1= 143 (b) (1382400Hz /19200) – 1= 71 (c) (1382400Hz /38400) – 1= 35 (d) (1382400Hz /57600) – 1= 23

45.

Error = (Calculated value for the UBRR – Integer part) / Integer part (a) (103.166 -103) /103 = 0.16% (b) (51.08 - 51) / 51 = 0.16% (c) (25.04 - 25) / 25 = 0.16% (d) (16.36 - 16) / 16 = 2.2%

46.

Error = (Calculated value for the UBRR – Integer part) / Integer part (a) (207.33 - 207) /207 = 0.16% (b) (103.166 -103) /103 = 0.16% (c) (51.08 - 51) / 51 = 0.16% (d) (33.72 - 33) /33 = 2.1%

.

73

47.

Error = (Calculated value for the UBRR – Integer part) / Integer part (a) (71-71) / 71 = 0% (b) (35-35) / 35 = 0% (c) (17- 17) / 17 = 0% (d) (11 - 11) /11 = 0%

48.

Error = (Calculated value for the UBRR – Integer part) / Integer part (a) (143-143) / 143 = 0% (b) (71-71) / 71 = 0% (c) (35-35) / 35 = 0% (d) (23- 23) / 23 = 0%

SECTION 11.4: AVR SERIAL PORT PROGRAMMING IN C 49. #include <avr/io.h>

//standard AVR header

int main (void) { //initialize USART transmitter for 8 bit data no parity //and one stop bit UCSRB = (1<<TXEN) ; UCSRC = (1<< UCSZ1)|(1<<UCSZ0)|(1<<URSEL); UBRRL = 0x33 ; while (! (UCSRA & (1<<UDRE))); //wait until UDR is empty UDR = 'Z' ; }

return 0 ;

50. #include <avr/io.h>

//standard AVR header

void transmit ( unsigned char data ) { while (! (UCSRA & (1<<UDRE))); //wait until UDR is empty UDR = data; } void serial_putstr( unsigned char str [] ) { unsigned char i = 0; while(str[i] != 0) transmit(str[i++]); } int main (void) { //initialize USART transmitter for 8 bit data no parity //and one stop bit

.

74

UCSRB = (1<<TXEN) ; UCSRC = (1<< UCSZ1)|(1<<UCSZ0)|(1<<URSEL); UBRRL = 0x33 ;

}

.

serial_putstr("The Earth is but One Country."); return 0 ;

75

CHAPTER 12: LCD AND KEYBOARD INTERFACING SECTION 12.1: LCD INTERFACING 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

14 They are the control lines for the LCD. E is for latching information into the LCD, R/W is for reading from or writing information into the LCD , and RS is for making a distinction between the data and command.

Vee controls the contrast of the screen while Vcc provides power to the LCD. command, 01h 0Eh RS = 0, RW = 0, E = H-to-L pulse RS = 1, RW = 0, E = H-to-L pulse (a) H-toL True Sending information to the LCD in the 8-bit mode needs less coding and save the programmer times but it needs 8 pins for data plus the pins needed for control. The 4-bit mode, uses only 4 pins for data and save 4 pins. However, the subroutine for 4-bit data is much harder to write and takes more code.

80h is the starting location ,and 16 locations to the right is 8Fh. C4h. This is 4 locations from C0h since C0 is the first location of line 2.

C0h is the starting location, and 20 locations to the right is 13h which result in C0h + 13h = D3h.

C2h. This is 2 locations from C0h since C0 is the first location of line 2.

If 80h is the address of the first location, then adding 39 (27h) we get 80h + 27h = A7h.

If C0h is the address of the first location, then adding 39 (27h) we get C0h + 27h = E7h.

89h since 80h + 9 = 89h. The 10th is address 9 since it starts at 0.

C0h + 13h = D3h. Notice that the 20th starts at 0 and goes to 13h.

SECTION 12.2: KEYBOARD INTERFACING 19.

20.

21.

22.

23.

24.

.

All 1’s (a) (b) (a) F (b) 0 1) Ground all rows. 2) Read the columns. 3) If all columns are high go to step 1.

1) Ground one row at a time. 2) Read the columns. 3) If all columns are high ground the next row. 4) When a low column is found, we get the key code from the look-up table.

76

CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING SECTION 13.1: ADC CHARACTERISTICS 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

True True True False True True False True False False (d) (d) (a) (5V) / (28) = 19.53 mV (b) (5V) / (210) = 4.88 mV (c) (5V) / (212) = 1.22 mV (d) (5V) / (216) = 76.29 µV The step size is 1.28 / (28) = 5 mV (a) since the step size is 5 mV and all inputs are high, we get 255 x 5 mV = 1.275 V. (b) 10011001 = 153 and 153 x 5 mV = 0.756 V. (c) 1101100= 108 and 108 x 5 mV = 0.540 V. 1.28 V since 256 x 5 mV = 1.28V (a) since the step size is 10 mV and all inputs are high, we get 255 x 10 mV = 2.56 V. (b) 10011001 = 153 and 153 x 10 mV = 1.53 V. (c) 1101100= 108 and 108 x 10 mV = 1.08 V.

SECTION 13.2: ADC PROGRAMMING IN THE ATMEGA32 17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

.

True False. It is 10-bit True True True False False True False True It is kept by the ADCH:ADCL registers. At the end of conversion, the ADIF flag in ADCSRA register is set.

The old data gets lost. (a) 1.024V / 1024 = 1 mV (b) 2.048 / 1024 = 2 mV (c) 2.56 / 1024 = 2.5 mV

77

30.

31.

32.

33.

34.

35.

36.

2 mV x 1024 = 2048mV = 2.048V 3 mV x 1024 = 3.072V 1 mV x 1023 = 1.023V Step Size = 1.024 /1024 = 1 mV (a) 255 x 1 mV = 0.255V (b) 152 x 1 mV = 0.152V (c) 208 x 1 mV = 0.208V 4 mV x 1024 = 4096 mV = 4.096 V Step Size = 2.56/1024 = 2.5 mV (a) 1023 x 2.5 mV = 2.5575V (b) 513 x 2.5mV = 1.2825V (c) 816 x 2.5 mV = 2.04V The crystal frequency is 8MHz (a) Fosc/2 = 8 MHz / 2 = 4 MHz (greater than 200 kHz and not valid) (b) Fosc/4 = 8 MHz / 4 = 2 MHz (greater than 200 kHz and not valid) (c) Fosc/8 = 8 MHz / 8 = 1 MHz (greater than 200 kHz and not valid) (d) Fosc/2 = 8 MHz / 16 = 500 KHz (greater than 200 kHz and not valid) (e) Fosc/2 = 8 MHz / 32 = 250 KHz (greater than 200 kHz and not valid) Note: It is not needed to calculate first conversion time because none of the above frequencies are valid.

37.

The crystal frequency is 4MHz (a) Fosc/8 = 4 MHz / 8 = 500 KHz (greater than 200 kHz and not valid) (b) Fosc/16 = 4 MHz / 16 = 250 KHz (greater than 200 kHz and not valid) (c) Fosc/32 = 4 MHz / 32 = 125.5 KHz => T = 1/ 125.5 KHz = 8 microseconds first conversion takes 25 ADC clock cycles = 25 * 8 microsecond = 200 microseconds (d) Fosc/64 = 4 MHz / 64 = 62.75 KHz => T = 1/ 62.75 KHz = 16 microseconds first conversion takes 25 ADC clock cycles = 25 * 16 microsecond = 400 microseconds

38.

39.

40.

41.

42.

43.

By writing a one to the ADSC bit of ADCSRA. By polling the ADIF bit in the ADCSRA register..

ADPS2:0 (Bit2:0) of ADCSRA MUX4…MUX0 bits of ADMUX register.

ADIF ( bit 4 ) of ADCSRA register. off.

SECTION 13.3: SENSOR INTERFACING AND SIGNAL CONDITIONING 44.

45.

46.

The output corresponds with the input linearly (in a straight line).

10 mV Adjusting the output of a given sensor (device) to meet the input needs of the ADC chip

SECTION 13.4: DAC INTERFACING 47.

48.

49.

50.

.

True. (a) 256 (b) 1024 (c) 4096 2 mA x (255/256) = 1.99 mA (a) 1.195 mA since 10011001B = 153 and (153 x 2 mA)/256 = 1.195 mA (b) 1.594 mA since 11001100B = 204 and (204 x 2 mA)/256= 1.594 mA

78

51.

52.

.

(c) 1.859 mA since 11101110B = 238 and (238 x 2 mA)/256 = 1.859 mA (d) 0.2656 mA (e) 0.0703125 mA (f) 1.063 mA More All high

79

Chapter 14: RELAY, OPTOISOLATOR, AND STEPPER MOTOR INTERFACING WITH AVR SECTION 14.1: RELAYS AND OPTOISOLATORS 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

False True There is no coil, spring or mechanical contact False 5 / 1200 = 4.167 mA Motor control and telecommunications size and speed EM relay True False

SECTION 14.2: STEPPER MOTOR INTERFACING 11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

.

360 / 90 = 4 degrees 48 1001, 1100, 0110 0110, 0011, 1001 0011, 0110, 1100 1100, 1001, 0011 The ULN2003 provides addition current for driving the motor, No b Slows the motor Decrease the time delay between steps

80

Chapter 15: INPUT CAPTURE AND WAVE GENERATION IN AVR SECTION 15.1: WAVE GENERATION USING 8-BIT TIMERS 1.

2.

3.

4.

5.

False False True PD7 TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 80 kHz = 12.5 µs Î Ttoggle = 12.5 / 2 = 6.25 µs 6.25 / 0.125 = 50 Î OCR0 = 49 .INCLUDE "M32DEF.INC" SBI DDRB,3 LDI R20, 49 OUT OCR0, R20 LDI R20, 0x19 OUT TCCR0, R20 L1: RJMP L1

6.

//OCR0 = 49 //N = 1, CTC mode, toggle

TTimer Clock = 1 / 1 MHz = 1 µs TWave = 1/ 5 kHz = 0.2 ms Î Ttoggle = 0.2 / 2 = 0.1 ms = 100 µs 100 / 1 = 100 Î OCR0 = 99 .INCLUDE "M32DEF.INC" SBI DDRB,3 LDI R20, 99 OUT OCR0, R20 LDI R20, 0x19 OUT TCCR0, R20 L1: RJMP L1

7.

//OC0 as output

//OC0 as output //OCR0 = 99 //N = 1, CTC mode, toggle

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 625 Hz = 1.6 ms Î Ttoggle = 1.6 / 2 = 0.8 ms = 800 µs 800 / 0.125 = 6400 Î OCR0 = 99 N 1 8 64 256 1024

Timer clocks 6400 / 1 = 6400 6400 / 8 = 800 6400 / 64 = 100 6400 / 256 = 25 6400 / 1024 = 6.25

OCR0 Too big Too big 99 24 5.25

.INCLUDE "M32DEF.INC"

L1:

.

SBI LDI OUT LDI OUT RJMP

DDRB,3 R20, 99 OCR0, R20 R20, 0x1B TCCR0, R20 L1

//PB3(OC0) as output //OCR0 = 99 //CTC mode, N = 64, toggle

81

8.

TTimer Clock = 1 / 16 MHz = 0.0625 µs TWave = 1/ 3125 Hz = 320 µs Î Ttoggle = 320 / 2 = 160 µs 160 / 0.0625 = 2560 N 1 8 64 256 1024

Timer clocks 2560 / 1 = 2560 2560 / 8 = 320 2560 / 64 = 40 2560 / 256 = 10 2560 / 1024 = 2.5

OCR0 Too big Too big 39 9 1.5

.INCLUDE "M32DEF.INC"

L1:

SBI LDI OUT LDI OUT RJMP

DDRB,3 R20, 39 OCR0, R20 R20, 0x1B TCCR0, R20 L1

//PB3(OC0) as output //OCR0 = 39 //CTC mode, N = 64, toggle

SECTION 15.2: WAVE GENERATION USING TIMER1 9.

10.

11.

True 4 TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 1 kHz = 1 ms Î Ttoggle = 1 ms / 2 = 0.5 ms = 500 µs 500 / 0.125 = 4000 Î OCR1 = 3999 .INCLUDE "M32DEF.INC"

L1:

12.

SBI LDI OUT LDI OUT LDI OUT LDI OUT RJMP

DDRD, 5 R20, HIGH(3999) OCR1AH, R20 R20, LOW(3999) OCR1AL, R20 R20, 0x40 TCCR1A, R20 R20, 0x09 TCCR1B, R20 L1

;OCR1A = 3999 ;Toggle Generator A ;CTC, No prescaler

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 5 kHz = 0.2 ms Î Ttoggle = 0.2 ms / 2 = 0.1 ms = 100 µs 100 / 0.125 = 800 Î OCR1 = 799 .INCLUDE "M32DEF.INC" SBI LDI OUT LDI OUT

.

DDRD, 5 R20, HIGH(799) OCR1AH, R20 R20, LOW(799) OCR1AL, R20

;PD5(OC1A) as output

;OCR1A = 799

82

L1:

13.

LDI OUT LDI OUT RJMP

R20, 0x40 TCCR1A, R20 R20, 0x09 TCCR1B, R20 L1

;Toggle Generator A ;CTC, No prescaler, toggle ;stay here forever

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 50 Hz = 0.02 s Î Ttoggle = 0.02 s / 2 = 0.01 s = 10 ms = 10,000 µs 10,000 / 0.125 = 80,000 N 1 8 64 256 1024

Timer clocks 80,000 / 1 = 80,000 80,000 / 8 = 10,000 80,000 / 64 = 1,250 80,000 / 256 = 312.5 80,000 / 1024 = 78.125

OCR1 Too big 9999 1249 311 77

.INCLUDE "M32DEF.INC"

L1:

14.

SBI LDI OUT LDI OUT LDI OUT LDI OUT RJMP

DDRD, 5 R20, HIGH(1249) OCR1AH, R20 R20, LOW(1249) OCR1AL, R20 R20, 0x40 TCCR1A, R20 R20, 0x0B TCCR1B, R20 L1

;PD5(OC1A) as output

;OCR1A = 1249 ;Toggle Generator A ;CTC mode, N = 64

TTimer Clock = 1 / 16 MHz = 0.0625 µs TWave = 1/ 20 Hz = 0.05 s Î Ttoggle = 0.05 s / 2 = 0.025 s = 25 ms = 25,000 µs 25,000 / 0.0625 = 400,000 N 1 8 64 256 1024

Timer clocks 400,000 / 1 = 400,000 400,000 / 8 = 50,000 400,000 / 64 = 6,250 400,000 / 256 = 1562.5 400,000 / 1024 = 390.625

OCR1 Too big 49999 6249 1561 389

.INCLUDE "M32DEF.INC"

L1:

.

SBI LDI OUT LDI OUT LDI OUT LDI OUT RJMP

DDRD, 5 ;PD5(OC1A) as output R20, HIGH(6249) OCR1AH, R20 R20, LOW(6249) OCR1AL, R20 ;OCR1A = 6249 R20, 0x40 ;Toggle Generator A TCCR1A, R20 R20, 0x0B ;CTC mode, N = 64, toggle TCCR1B, R20 L1

83

SECTION 15.3: INPUT CAPTURE PROGRAMMING 15.

16.

17.

18.

19.

20.

The Input Capture function is widely used for many applications. Among them are (a) recording the arrival time of an event, (b) pulse width measurement, and (c) period measurement.

False False Timer1 0x01 0x41

SECTION 15.4: C PROGRAMMING 21.

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 50 kHz = 0.02 ms Î Ttoggle = 0.02 s / 2 = 0.01 ms = 10 µs 10 / 0.125 = 80 Î OCR0 = 79 #include "avr/io.h" int main () { DDRB = DDRB | (1<<3); //PB3(OC0) as output OCR0 = 79; TCCR0 = 0x19; //CTC mode, no prescaler, toggle }

22.

while(1);

//stay here forever

TTimer Clock = 1 / 1 MHz = 1 µs TWave = 1/ 20 kHz = 0.05 ms Î Ttoggle = 0.05 s / 2 = 0.025 ms = 25 µs 25 / 1 = 25 Î OCR2 = 24 #include "avr/io.h" int main () { DDRD = DDRD | (1<<7); OCR2 = 24; TCCR2 = 0x19; }

23.

while(1);

//PD7(OC2) as output //CTC mode, no prescaler, toggle

//stay here forever

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 100 Hz = 10 ms Î Ttoggle = 10 ms / 2 = 5 ms = 5000 µs 5000 / 0.125 = 40,000 Î 40,000/ 256 = 156.25 Î OCR2 = 155 #include "avr/io.h" int main () {

.

84

DDRD = DDRD | (1<<7); //PD7(OC2) as output OCR2 = 155; TCCR2 = 0x1E; //N = 256 }

24.

while(1);

//stay here forever

TTimer Clock = 1 / 1 MHz = 1 µs TWave = 1/ 95 Hz = 10.52 ms Î Ttoggle = 10.526 ms / 2 = 5.263 ms = 5263 µs 5263 / 1 = 5263 Î 5263/ 64 = 82.23 Î OCR0 = 81 #include "avr/io.h" int main () { DDRB = DDRB | (1<<3); //PB3(OC0) as output OCR0 = 81; TCCR0 = 0x1B; //CTC mode, N = 64, toggle }

25.

while(1);

//stay here forever

TTimer Clock = 1 / 8 MHz = 0.125 µs Î 0.125 µs * 1024 = 128 µs TWave = 1/ 50 Hz = 0.02 s Î Ttoggle = 0.02 s / 2 = 0.01 s =10,000 Î 10000 / 128 = 78.125 Î OCR0 = 77 TWave = 1/ 60 Hz = 0.016 s Î Ttoggle = 0.016 s / 2 = 0.008 s = 8,000 Î 8000 / 128 = 62.5 Î OCR0 = 61 #include "avr/io.h" int main () { PORTB = PORTB | (1<<1); //pull-up register DDRB = DDRB | (1<<3); //PB3(OC0) as output OCR0 = 81; TCCR0 = 0x1D; //CTC mode, toggle, N = 1024

}

26.

while(1) { if(PINB&(1<<1)) OCR0 = 77; else OCR0 = 61; }

//50Hz //60Hz

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 3 kHz = 333 µs Î Ttoggle = 333 µs / 2 = 166.5 s Î 166.5 / 0.125 = 1332 Î OCR1 = 1331 #include "avr/io.h" int main () { DDRD = DDRD | (1<<5);

.

//PD5(OC1A) as output

85

OCR1A = 1331; TCCR1A = 0x40; TCCR1B = 0x09; }

27.

//toggle OC1A on compare match //N = 1, CTC (mode 4)

while(1);

TTimer Clock = 1 / 8 MHz = 0.125 µs TWave = 1/ 44 kHz = 22.727 µs Î Ttoggle = 22.727 µs / 2 = 11.36 µs Î 11.36 / 0.125 = 90.90 Î OCR1 = 90 #include "avr/io.h" int main () { DDRD = DDRD | (1<<5); OCR1A = 90; TCCR1A = 0x40; TCCR1B = 0x09; }

.

//PD5(OC1A) as output //toggle OC1A on compare match //N = 1, CTC (mode 4)

while(1);

86

Chapter 16: PWM AND DC MOTOR CONTROL SECTION 16.1: DC MOTOR INTERFACING AND PWM 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

Stepper motor The higher the load, the higher the current draw False no-load Speed control Positioning and angle control True Pulse width modulation. Higher duty cycle leads to higher speed of the motor Vary the PWM An optoisolator protects the microcontroller pin from EMF

SECTION 16.2: PWM MODES IN 8-BIT TIMERS 11.

62.5 k = 16 M / (256 x N) Î N = 16 M / 62.5 k x 256 = 1 60 = [(OCR0 + 1) / 256] x 100 Î OCR0 + 1 = 60 x 256 / 100 = 153.6 Î OCR0 = 153 .INCLUDE "M32DEF.INC"

L1:

12.

SBI LDI OUT LDI OUT RJMP

DDRB,3 R20, 153 OCR0, R20 R20, 0x69 TCCR0, R20 L1

;PB3(OC0) as output ;OCR0 = 153 ;N = 1, non-inverted fast PWM ;stay here forever

46.875 k = 12 M / (256 x N) Î N = 12 M / 46.875 k x 256 = 1 70 = [(255 – OCR0) / 256] x 100 Î 255 – OCR0 = 70 x 256 / 100 = 179.2 Î OCR0 = 255 – 179 = 76 .INCLUDE "M32DEF.INC"

L1:

13.

SBI LDI OUT LDI OUT RJMP

DDRB,3 R20, 76 OCR0, R20 R20, 0x79 TCCR0, R20 L1

//PB3(OC0) as output //OCR0 = 76 //inverted fast PWM, N = 1 //stay here forever

1953 = 4 M / (256 x N) Î N = 4 M / 256 x 1953 = 8 20 = [(255 – OCR0) / 256] x 100 Î 255 – OCR0 = 20 x 256 / 100 = 51.2 Î OCR0 = 255 – 51.2 = 204 .INCLUDE "M32DEF.INC" SBI LDI OUT

.

DDRB,3 R20, 204 OCR0, R20

//PB3(OC0) as output //OCR0 = 204

87

L1:

14.

LDI OUT RJMP

R20, 0x7A TCCR0, R20 L1

//inverted fast PWM //stay here forever

15.25 = 1 M / (256 x N) Î N = 1 M / 15.25 x 256 = 256 10 = [(OCR0 + 1) / 256] x 100 Î OCR0 + 1 = 10 x 256 / 100 = 25.6 Î OCR0 = 25 .INCLUDE "M32DEF.INC"

L1:

15.

SBI LDI OUT LDI OUT RJMP

DDRB,3 R20, 25 OCR0, R20 R20, 0x6C TCCR0, R20 L1

//PB3(OC0) as output //OCR0 = 25 //non-inverted fast PWM, N = 256 //stay here forever

1960 = 1M /(510xN) Î N = 1M / (1960 x 510) Î N = 1 Duty cycle = 20 = [(255 – OCR0) / 255] x 100 Î255 – OCR0 = 51 Î OCR0 = 204 .INCLUDE "M32DEF.INC"

L1:

16.

SBI LDI OUT LDI OUT RJMP

DDRB,3 R20, 204 OCR0, R20 R20, 0x71 TCCR0, R20 L1

//OCR0 = 204 //inverted phase correct, N = 1 //stay here forever

1960 = 1M /(510xN) Î N = 1M / (1960 x 510) Î N = 1 Duty cycle = 95 = [(255 – OCR0) / 255] x 100 Î255 – OCR0 = 242.25 Î OCR0 = 13 .INCLUDE "M32DEF.INC" SBI DDRB,3 LDI R20, 13 OUT OCR0, R20 LDI R20, 0x71 OUT TCCR0, R20 L1: RJMP L1

17.

//PB3(OC0) as output

//PB3(OC0) as output //OCR0 = 13 //inverted, N = 1 //stay here forever

61.3 = 8M /(510xN) Î N = 8M / (61.3 x 510) Î N = 256 Duty cycle = 19 = [OCR2 / 255] x 100 ÎOCR2 = 48.45 Î OCR2 = 48 .INCLUDE "M32DEF.INC"

L1:

18.

.

SBI LDI OUT LDI OUT RJMP

DDRD,7 R20, 48 OCR2, R20 R20, 0x66 TCCR2, R20 L1

//PD7(OC2) as output //OCR2 = 48 //non-inverted phase correct, N = 256 //stay here forever

245 = 1M /(510xN) Î N = 1M / (245 x 510) Î N = 8 Duty cycle = 82 = [(255 – OCR2) / 255] x 100 Î255 – OCR2 = 209 Î OCR0 = 46

88

.INCLUDE "M32DEF.INC" SBI DDRD,7 LDI R20, 46 OUT OCR2, R20 LDI R20, 0x72 OUT TCCR2, R20 L1: RJMP L1

//PD7(OC2) as output //OCR2 = 46 //inverted phase correct, N = 8 //stay here forever

SECTION 16.3: PWM MODES IN TIMER1 19.

15625 = 8 M / (512 x N) Î N = 8 M / 15625 x 512 = 1 Duty cycle = 40 = 100 x (OCR1x + 1) / 512 Î OCR1x + 1 = 204.8 Î OCR1x = 204 .INCLUDE "M32DEF.INC"

L1:

20.

SBI LDI OUT LDI OUT LDI OUT LDI OUT RJMP

DDRD,5 R20, HIGH(204) OCR1AH, R20 R20, LOW(204) OCR1AL, R20 R20, 0x82 TCCR1A, R20 R20, 0x09 TCCR1B, R20 L1

//PD5(OC1A) as output

//OCR1A = 204 //mode 6, non-inverted Fast PWM //N = 1 //stay here forever

3906 = 4 M / (1024 x N) Î N = 4 M / 3906 x 1024 = 1 45 = 100 x (1023 – OCR1x) / 1024 Î 1023 – OCR1x = 460.8 Î OCR1x = 562 .INCLUDE "M32DEF.INC"

L1:

21.

SBI LDI OUT LDI OUT LDI OUT LDI OUT RJMP

DDRD,5 R20, HIGH(562) OCR1AH, R20 R20, LOW(562) OCR1AL, R20 R20, 0xC3 TCCR1A, R20 R20, 0x09 TCCR1B, R20 L1

//PD5(OC1A) as output

//OCR1A = 562 //mode 7, non-inverted Fast PWM //N = 1 //stay here forever

1953 = 16 M / (1024 x N) Î N = 16 M / 1953 x 1024 = 8 35 = 100 x (1023 – OCR1x) / 1024 Î 1023 – OCR1x = 358.4 Î OCR1x = 665 .INCLUDE "M32DEF.INC" SBI LDI OUT LDI OUT LDI OUT

.

DDRD,5 R20, HIGH(665) OCR1AH, R20 R20, LOW(665) OCR1AL, R20 R20, 0xC3 TCCR1A, R20

//PD5(OC1A) as output

//OCR1A = 665 //mode 7, inverted Fast PWM

89

L1:

22.

LDI OUT RJMP

R20, 0x0A TCCR1B, R20 L1

//N = 8 //stay here forever

1953 = 8 M / (512 x N) Î N = 8 M / 1953 x 512 = 8 50 = 100 x (OCR1x + 1) / 512 Î OCR1x + 1 = 256 Î OCR1x = 255 .INCLUDE "M32DEF.INC"

L1:

23.

SBI LDI OUT LDI OUT LDI OUT LDI OUT RJMP

DDRD,5 R20, HIGH(255) OCR1AH, R20 R20, LOW(255) OCR1AL, R20 R20, 0x82 TCCR1A, R20 R20, 0x0A TCCR1B, R20 L1

//PD5(OC1A) as output

//OCR1A = 255 //mode 6, non-inverted Fast PWM //N = 8 //stay here forever

976 = 4 M / (510 x N) Î N = 4 M / 976 x 510 = 8 35 = 100 x (255 – OCR1x) / 255 Î 255 – OCR1x = 89.25 Î OCR1x = 165.75 ≈ 166 .INCLUDE "M32DEF.INC"

PWM L1:

24.

SBI LDI OUT LDI OUT LDI OUT

DDRD,5 R20, HIGH(166) OCR1AH, R20 R20, LOW(166) OCR1AL, R20 R20, 0xC1 TCCR1A, R20

//PD5(OC1A) as output

//mode 1, inverted phase correct

LDI OUT RJMP

R20, 0x02 TCCR1B, R20 L1

//N = 8 //stay here forever

//OCR1A = 166

30.5 = 8 M / (1022 x N) Î N = 8 M / 1022 x 30.5 = 256 25 = 100 x OCR1x / 511 Î OCR1x = 127.75 ≈ 128 .INCLUDE "M32DEF.INC" SBI DDRD,5 LDI R20, HIGH(128) OUT OCR1AH, R20 LDI R20, LOW(128) OUT OCR1AL, R20 LDI R20, 0x82 OUT TCCR1A, R20 correct PWM LDI R20, 0x04 OUT TCCR1B, R20 L1: RJMP L1

.

//PD5(OC1A) as output

//OCR1A = 128 //mode 2, non-inverted phase //N = 256 //stay here

90

25.

245 = 8 M / (510 x N) Î N = 8 M / 245 x 510 = 64 19 = 100 x OCR1x / 255 Î OCR1x = 48.45 Î OCR1x = 48 .INCLUDE "M32DEF.INC" SBI LDI OUT LDI OUT

DDRD,5 R20, HIGH(48) OCR1AH, R20 R20, LOW(48) OCR1AL, R20

LDI R20, 0x81 OUT TCCR1A, R20 correct PWM LDI R20, 0x03 OUT TCCR1B, R20 L1:

26.

RJMP

L1

//PD5(OC1A) as output

//OCR1A = 48 //mode 1, non-inverted phase //N = 64 //stay here forever

978 = 8 M / (1022 x N) Î N = 8 M / 978 x 1022 = 8 20 = 100 x OCR1x / 511 Î OCR1x = 102.2 Î OCR1x = 102 85 = 100 x OCR1x / 511 Î OCR1x = 434.35 Î OCR1x = 434 .INCLUDE "M32DEF.INC" SBI PORTB,0 SBI DDRD,5 LDI R20, 0x82 OUT TCCR1A, R20 correct PWM LDI R20, 0x02 OUT TCCR1B, R20 L1:

L2:

.

SBIS PINB,0 RJMP L2 LDI R20, HIGH(434) OUT OCR1AH, R20 LDI R20, LOW(434) OUT OCR1AL, R20 RJMP L1 LDI OUT LDI OUT RJMP

R20, HIGH(102) OCR1AH, R20 R20, LOW(102) OCR1AL, R20 L1

//pull-up resistor //PD5(OC1A) as output //mode 2, non-inverted phase //N = 8 //if PINB.0 is 0 then jump L2 //duty cycle = 85%

//when key is closed //duty cycle = 20%

91

Chapter 17: SPI PROTOCOL AND MAX7221 DESPLAY INTERFACING SECTION 17.1: SPI BUS PROTOCOL 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

False True True False True True True False In a 3-wire interface bus, we have SCLK and CE, and only a single pin for data transfer but in SPI, we have SCLK and CE, and 2 pins for data transfer; MISO and MOSI. To distinguish between the read and write operations, the D7 bit of the address byte is always 1 for write, while for the read, the D7 bit is LOW.

SECTION 17.2: SPI PROGRAMMING IN AVR 11.

12.

13.

14.

15.

False SPSR, SPCR and SPDR SPI mode 2 means Read on falling edge and changed on a rising edge. According to Table 17-1, CPOL = 1 and CPHA = 0. CPOL and CPHA are bits 3 and 2 of SPCR register.

True True

SECTION 17.3: MAX7221 INTERFACING AND PROGRAMMING 16.

17.

18.

19.

20.

21.

22.

23.

24.

.

24 Pin 19 300 mA True 10 kilohm 8 The first byte (MSBs) of each packet contains the command control bits The second byte is the data to be displayed False

92

Chapter 18: I2C PROTOCOL AND DS1307 RTC INTERFACING SECTION 18.1: I2C BUS PROTOCOL 1.

2.

3.

4.

5.

6.

7.

8.

9.

True False True True True False True True In SPI, we have SCLK and CE, and 2 pins for data transfer that are called MISO and MOSI. But is I2C, we have SCK for clock and a single data pin that is called SDA. 10. The eighth bit in the packet is the READ/WRITE control bit. If this bit is set, the master will read the next frame (Data) from the slave, otherwise, the master will write the next frame to the slave.

SECTION 18.2: TWI PROGRAMMING IN AVR 11. True 12. Bit rate generation unit, bus interface unit, address match unit, and control unit.SPI mode.

13. bus interface unit 14. True 15. Bit0 and bit1 16. TWIE 17. By clearing the TWEA bit to zero.

SECTION 18.3: AVR TWI PROGRAMMING IN ASSEMBLY AN C 18. #include <avr/io.h> void i2c_init(void) { TWSR=0x00; // set prescaler bits to zero TWBR=0x47; // SCL Frequency is 50K for XTAL=8M TWCR=0x04; // Enable the TWI module } //********************************************************** void i2c_start(void) { TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN); while ((TWCR & (1 << TWINT)) == 0); }

.

93

//********************************************************** void i2c_write(unsigned char data) { TWDR = data ; TWCR = (1<< TWINT)|(1<<TWEN); while ((TWCR & (1 <<TWINT)) == 0); } //********************************************************** unsigned char i2c_read(unsigned char isLast) { if (isLast == 0) //if want to read more than 1 bytes TWCR = (1<< TWINT)|(1<<TWEN)|(1<<TWEA); else //if want to read only one byte TWCR = (1<< TWINT)|(1<<TWEN); while ((TWCR & (1 <<TWINT)) == 0); return TWDR ; } //********************************************************** void i2c_stop() { TWCR = (1<< TWINT)|(1<<TWEN)|(1<<TWSTO); } //********************************************************** int main (void) { unsigned char i = 0 ; i2c_init(); //initialize TWI for master mode i2c_start(); //transmit START condition i2c_write(0b01101001); //transmit SLA + R(1) i=i2c_read(1); //read only one byte of data i2c_stop(); //transmit STOP condition i2c_start(); //transmit START condition i2c_write(0b01101010);//transmit SLA + W(0) i2c_write(i); //write the byte of data i2c_stop(); //transmit STOP condition while(1); //stay here forever return 0 ; }

19. #include <avr/io.h>

// Standard AVR header

void i2c_initSlave(unsigned char slaveAddress) { TWCR = 0x04; //enable TWI module TWAR = slaveAddress; //set the Slave Address TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWEA);//init TWI module } //********************************************************* void i2c_send(unsigned char data) { TWDR = data; //copy Data to TWDR TWCR = (1<< TWINT)|(1<<TWEN); //start transmission while ((TWCR & (1 <<TWINT))==0); //wait to complete }

.

94

//********************************************************* void i2c_listen() { while ((TWCR & (1 <<TWINT))==0); //wait to be addressed } //********************************************************* int main (void) { i2c_initSlave(0b01101000);//init TWI module as //slave with address //0b0110100 and do not //accept general call i2c_listen(); //listen to be addressed i2c_send('Y'); //transmit ‘Y’ letter while(1); //stay here forever return 0 ; }

SECTION 18.4: DS1307 RTC INTERFACING AND PROGRAMMING 20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

30.

31.

32.

8 pin 4 pin 8 True True True 2099 It provides one of 1 kHz, 4 kHz, 8 kHz, or 32 kHz frequency if enabled. input RS1, RS0 and SQWE 64 When Vcc falls below the Vbat level Address location 0x00 is assigned to seconds, address location 0x01 is assigned to minute and address location 02 is assigned to hours and AM/PM 33.

Address location 0x03 is assigned to day(of week), address location 0x04 is assigned to day of month (date), address location 0x05 is assigned to month and address location 0x06 is assigned to year 34.

By setting D6 of hour location (location 0x02) to high, we switch to AM/PM mode 35.

By clearing D6 of hour location (location 0x02) we switch to 24 hours mode 36.

0x06 37.

0x3F 38.

True 39.

Here only the changed lines of program 18-11 are mentioned and other lines are the same. i2c_start(); i2c_write(0b11010000); i2c_write(0);

.

//transmit START condition //address DS1307 for write //set register pointer to 0

95

i2c_write(0x05); i2c_write(0x15); i2c_write(0b01101001); i2c_stop();

40.

Here only the changed line of program 18-12 is mentioned and other lines are the same. i2c_start(); i2c_write(0b11010000); i2c_write(0x04); i2c_write(0x14); i2c_write(0x05); i2c_write(0x09); i2c_stop();

41.

//transmit START condition //address DS1307 for write //set register pointer to 4 //set day to 0x14 = 14 BCD //set month to 0x05 = 05 BCD //set year to 0x09 = 09 BCD //transmit STOP condition

Here only the changed lines of program 18-13 are mentioned and other lines are the same.

DDRB = DDRC = 0xFF; i2c_start(); i2c_write(0xD1); i2c_read(1); PORTB = i2c_read(1); to PORTB PORTC = i2c_read(0); to PORTC i2c_stop();

.

//set seconds to 0x05 = 05 BCD //set minutes to 0x15 = 15 BCD //set hour=09 in 12 hours mode //transmit STOP condition

//Ports B and C are output //transmit START condition //address DS1307 for read //read second, return ACK //read minute, return ACK, Send BCD value //read hour, return NACK, Send BCD value //transmit STOP condition

96