Operating Systems Foundations
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Course Introduction
Operating Systems Foundations introduces students to the fundamental concepts and principles that underpin modern operating systems. The course covers essential topics such as process management, memory management, file systems, input/output systems, and security. Students explore how operating systems manage hardware resources, enable multitasking, enforce protection mechanisms, and facilitate user interactions. Through lectures, hands-on labs, and projects, learners gain practical experience with concepts like scheduling, synchronization, inter-process communication, and virtualization, preparing them for advanced studies or careers in software development and systems administration.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Page 2
Chapter 1: Basic Concepts and Computer Evolution
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Q1) When data are received from or delivered to a device that is directly connected to the computer,the process is known as __________.
Answer: input / output (I / O)
Q2) A particular architecture may span many years and encompass a number of different computer models,its organization changing with changing technology. A)True
B)False Answer: True
Q3) A __________ system is a set of interrelated subsystems. A)secondary
B)hierarchical
C)complex
D)functional Answer: B
Q4) The _________ controls the operation of the CPU and hence the computer. Answer: control unit
Q5) The major structural components of the CPU are: control unit,register,CPU interconnection,and __________.
Answer: arithmetic and logic unit (ALU)
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Chapter 2: Performance Issues
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Q1) With __________ the processor looks ahead in the instruction code fetched from memory and predicts which branches,or groups of instructions,are likely to be processed next.
Answer: branch prediction
Q2) Traditionally found on a plug-in graphics card,a _________ is used to encode and render 2D and 3D graphics as well as process video.
Answer: GPU (graphics processing units)
Q3) One increment,or pulse,of a clock is referred to as a __________ .
A)clock cycle
B)clock rate
C)clock speed
D)cycle time
Answer: A
Q4) A straight comparison of clock speeds on different processors tells the whole story about performance.
A)True
B)False
Answer: False
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) The method of using the same lines for multiple purposes is known as time multiplexing.
A)True
B)False
Answer: True
Q2) Timing refers to the way in which events are coordinated on the bus.
A)True
B)False
Answer: True
Q3) The most common classes of interrupts are: program,timer,I / O and ________.
Answer: hardware failure
Q4) With _________ transmission signals are transmitted as a current that travels down one conductor and returns on the other.
Answer: balanced
Q5) The collection of paths connecting the various modules is called the _________ structure.
Answer: interconnection
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Q6) A __________ is a communication pathway connecting two or more devices. Answer: bus
Chapter 4: Cache Memory
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Q1) A line includes a _________ that identifies which particular block is currently being stored.
A)cache
B)hit
C)tag
D)locality
Q2) The ________ consists of the access time plus any additional time required before a second access can commence.
A)latency
B)memory cycle time
C)direct access
D)transfer rate
Q3) The three key characteristics of memory are capacity,access time,and _______.
Q4) A logical cache stores data using __________.
A)physical addresses
B)virtual addresses
C)random addresses
D)none of the above
Q5) One byte equals __________ bits.
Q6) External,nonvolatile memory is referred to as ___________ or auxiliary memory.
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Chapter 5: Internal Memory
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Q1) The simplest of the error-correcting codes is the _________ code.
Q2) Which of the following memory types are nonvolatile?
A)erasable PROM
B)programmable ROM
C)flash memory
D)all of the above
Q3) An error-correcting code enhances the reliability of the memory at the cost of added complexity.
A)True
B)False
Q4) A __________ failure is a permanent physical defect so that the memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1.
Q5) Flash memory is only used for internal memory applications.
A)True
B)False
Q6) A static RAM will hold its data as long as power is supplied to it.
A)True
B)False
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Q7) The two distinctive types of flash memory are designated as NOR and ______ .
Chapter 6: External Memory
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Q1) Because data are striped in very small strips,RAID 3 cannot achieve very high data transfer rates.
A)True
B)False
Q2) RAID levels 2 and 3 make use of a _________ access technique in which all member disks participate in the execution of every I / O request.
Q3) A __________ disk is permanently mounted in the disk drive,such as the hard disk in a personal computer.
A)nonremovable
B)movable-head
C)double sided
D)removable
Q4) Flash memory becomes unusable after a certain number of writes.
A)True
B)False
Q5) RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance.
A)True
B)False
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Chapter 7: Input Output
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Q1) ________ is when the DMA module must force the processor to suspend operation temporarily.
A)Interrupt
B)Thunderbolt
C)Cycle stealing
D)Lock down
Q2) It is the responsibility of the processor to periodically check the status of the I / O module until it finds that the operation is complete.
A)True
B)False
Q3) The most common means of computer / user interaction is a __________.
A)keyboard / monitor
B)mouse / printer
C)modem / printer
D)monitor / printer
Q4) The categories for the major functions or requirements for an I / O module are: control and timing,device communication,data buffering,error detection,and
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Chapter 8: Operating System Support
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Q1) When the processor executes a process it automatically converts from logical to physical address by adding the current starting location of the process,called its __________,to each logical address.
Q2) The _________ defines the repertoire of machine language instructions that a computer can follow.
A)ABI
B)API
C)HLL
D)ISA
Q3) In an _________ system the user / programmer interacts directly with the computer,usually through a keyboard / display terminal to request the execution of a job or to perform a transaction.
Q4) The portion of the monitor that must always be in main memory and available for execution is referred to as the __________.
Q5) A _________ system works only one program at a time.
A)batch
B)uniprogramming
C)kernel
D)privileged instruction
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Chapter 9: Number Systems
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Q1) A nibble is a grouping of four decimal digits.
A)True
B)False
Q2) In a __________ number system,each number is represented by a string of digits in which each digit position i has an associated weight ri,where r is the radix of the number system.
Q3) In the number 472.156 the 2 is the _________.
A)most significant digit
B)radix point
C)least significant digit
D)none of the above
Q4) In any number,the rightmost digit is referred to as the most significant digit.
A)True
B)False
Q5) The decimal system has a radix of _________.
Q6) Binary 0101 is hexadecimal _________.
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Chapter 10: Computer Arithmetic
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Q1) The register contains additional bits,called __________,which are used to pad out the right end of the significand with 0s.
Q2) __________ representation is almost universally used as the processor representation for integers.
A)Biased
B)Twos compliment
C)Sign-magnitude
D)Decimal
Q3) Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________.
A)sign extension
B)range extension
C)bit extension
D)partial extension
Q4) The most important floating-point representation is defined in IEEE Standard _________,adopted in 1985 and revised in 2008.
Q5) The _________ is that part of the computer that actually performs arithmetic and logical operations on data.
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Chapter 11: Digital Logic
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Q1) Logical functions are implemented by the interconnection of decoders.
A)True
B)False
Q2) Counters can be designated as _________.
A)asynchronous
B)synchronous
C)both asynchronous and synchronous
D)neither asynchronous or synchronous
Q3) A register is a digital circuit used within the CPU to store one or more bits of data.
A)True
B)False
Q4) A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.
A)SPLD
B)FPGA
C)PAL
D)PLA
Q5) The basic logical operations of Boolean algebra are AND,OR,and ________.
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Chapter 12: Characteristics and Functions
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Q1) It has become common practice to use a symbolic representation of machine instructions.
A)True
B)False
Q2) The collection of different instructions that the processor can execute is referred to as the processor's _________.
Q3) Which data type is defined in MMX?
A)packed byte
B)packed word
C)packed doubleword
D)all of the above
Q4) Addresses are a form of data.
A)True
B)False
Q5) Intel's ________ technology is a set of highly optimized instructions for multimedia tasks.
Q6) Today the most commonly used character code is the IRA,referred to in the United States as _____________.
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Chapter 13: Addressing Modes and Formats
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Q1) A(n)__________ defines the layout of the bits of an instruction in terms of its constituent fields,must include an opcode and,implicitly or explicitly,zero or more operands.
Q2) For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.
A)True
B)False
Q3) The simplest form of addressing is __________ addressing.
Q4) _________ is a principle by which two variables are independent of each other.
A)Opcode
B)Orthogonality
C)Completeness
D)Autoindexing
Q5) The principal advantage of ___________ addressing is that it is a very simple form of addressing.
A)displacement
B)register
C)stack
D)direct
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Chapter 14: Processor Structure and Function
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Q1) The _________ contains a word of data to be written to memory or the word most recently read.
A)MAR
B)PC
C)MBR
D)IR
Q2) The ________ flag allows the programmer to disable debug exceptions so that the instruction can be restarted after a debug exception without immediately causing another debug exception.
Q3) A processor must: fetch instruction,interpret instruction,process data,write data,and
Q4) The _________ stage includes ALU operations,cache access,and register update.
A)decode
B)execute
C)fetch
D)write back
Q5) The processor needs to store instructions and data temporarily while an instruction is being executed.
A)True
B)False
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Chapter 15: Reduced Instruction Set Computers
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Q1) Blocks of memory,recently used global variables,memory addressing,and one operand addressed and accessed per cycle are characteristics of _________ organizations.
Q2) _________ determines the control and pipeline organization.
A)Calculation
B)Execution sequencing
C)Operations performed
D)Operands used
Q3) With simple,one cycle instructions,there is little or no need for microcode.
A)True
B)False
Q4) A _________ architecture is one that makes use of more,and more fine-grained pipeline stages.
A)parallel
B)superpipelined
C)superscalar
D)hybrid
Q5) The acronym RISC stands for __________.
Q6) The acronym CISC stands for _________.
Q7) The acronym SPARC stands for __________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) _________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.
A)Machine parallelism
B)Instruction-level parallelism
C)Output dependency
D)Procedural dependency
Q2) In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.
Q3) In the scalar organization there are multiple functional units,each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.
A)True
B)False
Q4) The superscalar approach depends on the ability to execute multiple instructions in parallel.
A)True
B)False
Q5) An alternative to _________ is a scoreboarding.
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Chapter 17: Parallel Processing
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Q1) The four deployment models defined by NIST are: public cloud,private cloud,community cloud,and __________ cloud.
Q2) Uniprocessors fall into the _______ category of computer systems.
A)MIMD
B)SIMD
C)SISD
D)MISD
Q3) ________ provides service to customers in the form of software,specifically application software,running on and accessible in the cloud.
A)PaaS
B)CaaS
C)SaaS
D)IaaS
Q4) An approach that allows for a high degree of instruction-level parallelism without increasing circuit complexity or power consumption is called ________.
Q5) Two key characteristics of a process are: scheduling / execution and ________.
Q6) A ________ is a group of interconnected,whole computers working together as a unified computing resource that can create the illusion of being one machine.
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Chapter 18: Multicore Computers
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Q1) ________ threading involves the selective use of fine-grain threading for some systems and single threading for other systems.
Q2) The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.
Q3) An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.
A)True
B)False
Q4) _______ law assumes a program in which a fraction (1- f )of the execution time involves code that is inherently serial and a fraction f that involves code that is infinitely parallelizable with no scheduling overhead.
Q5) _________ states that performance increase is roughly proportional to square root of increase in complexity.
Q6) With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.
A)True
B)False
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) The parallel code in the form of a function to be run on GPU is the ________ .
A)grid
B)thread
C)kernel
D)none of the above
Q2) To enhance performance,a technique known as __________ is used for the shared L3 data cache.
A)cache banking
B)thread blocking
C)streaming
D)warping
Q3) GPUs can be found in almost all of today's workstations,laptops, tablets,and smartphones.
A)True
B)False
Q4) A group of threads assigned to a particular SM is a __________ .
A)block
B)grid
C)unit
D)kernel
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Chapter 20: Control Unit Operation
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Q1) The "read word from memory" and "increment PC" actions cannot be used simultaneously because they will interfere with each other.
A)True
B)False
Q2) The execution of a program consists of the sequential execution of instructions.
A)True
B)False
Q3) If the instruction specifies an indirect address,then a(n)________ cycle must precede the execute cycle.
Q4) The execute cycle is simple and predictable.
A)True
B)False
Q5) The __________ register contains the value to be stored in memory or the last value read from memory.
Q6) The __________ module handles multiple levels of interrupt signals.
A)interrupt control
B)incrementer address latch
C)serial I / O control
D)decrementer address latch
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Chapter 21: Microprogrammed Control
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Q1) The __________ generated by a microinstruction are used to cause register transfers and ALU operations.
Q2) The LSI-11 is a good example of a __________ microinstruction approach.
Q3) Microprogramming is the dominant technique for implementing control units in pure _________ architectures due to its ease of implementation.
Q4) _________ processors,with their simpler instruction format,typically use hardwired control units.
Q5) The two basic tasks performed by a microprogrammed control unit are microinstruction sequencing and microinstruction __________.
Q6) When a microinstruction is read from the control memory it is transferred to a
A)control buffer register
B)control memory
C)control address register
D)control unit
Q7) A microprogram is midway between hardware and software.
A)True
B)False
Q8) A sequence of instructions is known as a ___________,or firmware.
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