Microprocessor Systems
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Course Introduction
This course introduces students to the fundamental concepts of microprocessor architecture and operation, emphasizing the design and implementation of microprocessor-based systems. Topics include instruction sets, assembly language programming, interfacing techniques, memory organization, input/output devices, and bus structures. Students will gain practical experience through programming exercises and laboratory projects focused on the integration of hardware and software components in embedded applications. By the end of the course, students will have a comprehensive understanding of how microprocessors control and interact with other system elements to perform real-world tasks.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Page 2
Chapter 1: Basic Concepts and Computer Evolution
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Q1) Often referred to as processor the ________ controls the operation of the computer and performs its data processing functions.
Answer: central processing unit (CPU)
Q2) Control signals,interfaces between the computer and peripherals,and the memory technology used are all examples of _________ attributes.
Answer: organizational
Q3) The basic functions that a computer can perform are: data processing,data movement,control,and _________.
Answer: data storage
Q4) The _________ stores data.
A)system bus
B)I / O
C)main memory
D)control unit
Answer: C
Q5) When data are received from or delivered to a device that is directly connected to the computer,the process is known as __________.
Answer: input / output (I / O)
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Chapter 2: Performance Issues
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Q1) Cloud service providers use massive high-performance banks of servers to satisfy high-volume,high-transaction-rate applications for a broad spectrum of clients.
A)True
B)False
Answer: True
Q2) With respect to changes in values,the __________ Mean gives equal weight to all of the values in the data set.
A)Harmonic
B)Arithmetic
C)Composite
D)Geometric
Answer: D
Q3) Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors.
A)True
B)False
Answer: False
Q4) __________ Law applies to a queuing system.
Answer: Little's
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) A key characteristic of a bus is that it is not a shared transmission medium.
A)True
B)False
Answer: False
Q2) The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.
A)True
B)False
Answer: False
Q3) A(n)_________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.
Answer: timer
Q4) The TL supports which of the following address spaces?
A)memory
B)I / O
C)message
D)all of the above
Answer: D
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Chapter 4: Cache Memory
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Q1) All of the Pentium processors include two on-chip L1 caches,one for data and one for instructions.
A)True
B)False
Q2) The most commonly used physical types of memory are: semiconductor memory,__________ memory (used for disk and tape),and optical and magneto-optical.
Q3) The cache consists of blocks called __________.
Q4) Cache is not a form of internal memory.
A)True
B)False
Q5) __________ computing deals with super computers and their software.
Q6) The Pentium 4 processor core consists of four major components: fetch / decode unit,out-of-order execution logic,memory subsystem,and __________.
Q7) Internal memory capacity is typically expressed in terms of _________.
A)hertz
B)nanos
C)bytes
D)LOR
Q8) One byte equals __________ bits.
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Chapter 5: Internal Memory
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Q1) A __________ RAM is a digital device that uses the same logic elements used in the processor.
Q2) A __________ contains a permanent pattern of data that cannot be changed,is nonvolatile,and cannot have new data written into it.
A)RAM
B)SRAM
C)ROM
D)flash memory
Q3) A __________ error is a random,nondestructive event that alters the contents of one or more memory cells without damaging the memory.
Q4) ___________ is a new type of Magnetic RAM,which features non-volatility,fast writing / reading speed,and high programming endurance and zero standby power.
Q5) Theoretically,a DDR module can transfer data at a clock rate in the range of __________ Mbps.
A)200 to 400
B)400 to 1066
C)600 to 1400
D)800 to 1600
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Chapter 6: External Memory
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Q1) The sum of the seek time and the rotational delay equals the _________,which is the time it takes to get into position to read or write.
A)access time
B)gap time
C)transfer time
D)constant angular velocity
Q2) A _________ drive is a memory device made with solid-state components that can be used as a replacement to a hard disk drive.
Q3) The areas between pits are called _________.
A)lands
B)sectors
C)cylinders
D)strips
Q4) RAID levels 4 through 6 make use of an __________ access technique that allows separate I / O requests to be satisfied in parallel.
Q5) In a __________ disk there is only one read-write head mounted on an arm that can be extended or retracted to be able to be positioned above any track.
Q6) Data is organized on the platter in a concentric set of rings called ________.
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Chapter 7: Input Output
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Q1) A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device.
A)True
B)False
Q2) An I / O module that takes on most of the detailed processing burden,presenting a high-level interface to the processor,is usually referred to as an _________.
A)I / O channel
B)I / O command
C)I / O controller
D)device controller
Q3) There are four types of I / O commands that an I / O module may receive when it is addressed by a processor: control,test,write,and _________.
Q4) An I / O channel has the ability to execute I / O instructions,which gives it complete control over I / O operations.
A)True
B)False
Q5) An external device connected to an I / O module is often referred to as a __________ device.
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Chapter 8: Operating System Support
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Q1) The portion of the monitor that must always be in main memory and available for execution is referred to as the __________.
Q2) Three key interfaces in a typical computer system are: instruction set architecture,application programming interface,and ___________.
Q3) Virtual memory schemes make use of a special cache called a ________ for page table entries.
A)TLB
B)HLL
C)VMC
D)SPB
Q4) The five defined states for a process are: new,ready,waiting,halted,and ________.
Q5) The technique where memory is expanded to hold three,four,or more programs and switch among all of them is __________,(or multitasking).
Q6) ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer.
A)True
B)False
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Chapter 9: Number Systems
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Q1) In the number 3109,the 3 is referred to as the _________.
A)most significant digit
B)least significant digit
C)radix
D)base
Q2) A number cannot be converted from binary notation to decimal notation.
A)True
B)False
Q3) Another term for "base" is __________.
A)radix
B)integer
C)position
D)digit
Q4) (2 x 10-1)+ (5 x 10-2)+ (6 x 10-3)represents the number _________.
Q5) The binary string 110111100001 is equivalent to __________.
A)DE1<sub>16</sub>
B)C78<sub>16</sub>
C)FF64<sub>16</sub>
D)B8F<sub>16</sub>
Q6) The decimal system has a radix of _________.
Page 11
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Chapter 10: Computer Arithmetic
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Q1) It is not necessary for the ALU to signal when overflow occurs.
A)True
B)False
Q2) The use of subnormal numbers is referred to as _________ underflow.
Q3) _________ representation is when the radix point is fixed and assumed to be to the right of the rightmost digit.
Q4) Compared with addition and subtraction,multiplication is a complex operation,whether performed in hardware of software.
A)True
B)False
Q5) Although considered obsolete,the term _________ is sometimes used instead of significand.
A)minuend
B)mantissa
C)base
D)subtrahend
Q6) The most important floating-point representation is defined in IEEE Standard _________,adopted in 1985 and revised in 2008.
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Chapter 11: Digital Logic
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Q1) The digital circuitry in digital computers and other digital systems is designed,and its behavior is analyzed,with the use of a mathematical discipline known as __________.
Q2) The delay by the propagation time of signals through the gate is known as the gate delay.
A)True
B)False
Q3) "Don't care" conditions are when certain combinations of values of variables never occur,and therefore the corresponding output never occurs.
A)True
B)False
Q4) The unary operation _________ inverts the value of its operand.
A)OR
B)NOT
C)NAND
D)XOR
Q5) An asynchronous counter is also referred to as a ________ because the change that occurs to increment the counter starts at one end and "ripples" through to the other end.
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Chapter 12: Characteristics and Functions
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Q1) The _________ instruction includes an implied address.
A)skip
B)rotate
C)stack
D)push
Q2) Which data type is defined in MMX?
A)packed byte
B)packed word
C)packed doubleword
D)all of the above
Q3) Addresses are a form of data.
A)True
B)False
Q4) Most machines provide the basic arithmetic operations of add, subtract,multiply,and divide.
A)True
B)False
Q5) A self-contained computer program that is incorporated into a larger program is a __________.
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Chapter 13: Addressing Modes and Formats
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Q1) The value of the mode field determines which addressing mode is to be used.
A)True
B)False
Q2) A very powerful mode of addressing,__________ combines the capabilities of direct addressing and register indirect addressing,requiring that the instruction have two address fields,at least one of which is explicit.
Q3) _________ is a principle by which two variables are independent of each other.
A)Opcode
B)Orthogonality
C)Completeness
D)Autoindexing
Q4) Sometimes referred to as a pushdown list or last-in-first-out queue,a __________ is a linear array of locations.
Q5) Typically an instruction set will include both preindexing and postindexing.
A)True
B)False
Q6) Just as register addressing is analogous to direct addressing,________ addressing is analogous to indirect addressing.
Q7) The simplest form of addressing is __________ addressing.
Page 15
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Chapter 14: Processor Structure and Function
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Q1) The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.
A)dynamic branch
B)loop table
C)branch history table
D)flag
Q2) A processor must: fetch instruction,interpret instruction,process data,write data,and
Q3) The exception modes have full access to system resources and can change modes freely.
A)True
B)False
Q4) Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.
A)True
B)False
Q5) Two classes of events cause the x86 to suspend execution of the current instruction stream and respond to the event: interrupts and ________.
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Chapter 15: Reduced Instruction Set Computers
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Q1) __________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.
Q2) Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.
A)True
B)False
Q3) A tactic similar to the delayed branch is the _________,which can be used on LOAD instructions.
A)delayed load
B)delayed program
C)delayed slot
D)delayed register
Q4) Introduced by IBM with its System / 360,the _________ is a set of computers offered with different price and performance characteristics that presents the same architecture to the user.
Q5) The work that has been done on assessing merits of the RISC approach can be grouped into two categories: quantitative and _________.
Q6) The acronym CISC stands for _________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) A ________ implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.
Q2) The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.
A)True
B)False
Q3) Register renaming eliminates antidependencies and output dependencies.
A)True
B)False
Q4) ________ refers to the process of initiating instruction execution in the processor's functional units.
A)Instruction issue
B)In-order issue
C)Out-of-order issue
D)Procedural issue
Q5) In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.
Q6) An alternative to _________ is a scoreboarding.
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Chapter 17: Parallel Processing
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Q1) A ________ is a group of interconnected,whole computers working together as a unified computing resource that can create the illusion of being one machine.
Q2) A cloud broker is useful when cloud services are too complex for a cloud consumer to easily manage.
A)True
B)False
Q3) Hardware-based solutions are generally referred to as cache coherence _______.
A)clusters
B)streams
C)protocols
D)vectors
Q4) SMPs,clusters,and NUMA systems fit into the ________ category of computer systems.
A)SISD
B)MIMD
C)SIMD
D)MISD
Q5) The four deployment models defined by NIST are: public cloud,private cloud,community cloud,and __________ cloud.
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Chapter 18: Multicore Computers
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Q1) The ________ feature enables moving dirty data from one CPU to another without writing to L2 and reading the data back in from external memory.
A)migratory lines
B)DDI
C)VFP unit
D)IPIs
Q2) Database management systems and database applications are one area in which multicore systems can be used effectively.
A)True
B)False
Q3) From the point of view of an A15 core,an interrupt can be active,inactive,or
Q4) The principal building block of the IBM zEnterprise EC12 mainframe is the
Q5) The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.
Q6) Individual modules called systems are assigned to individual processors with ________ threading.
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) The GPU has found its way into massively parallel programming environments for a wide range of applications,which is where the term __________ is derived from.
Q2) An instance of the kernel on the GPU is a ___________ .
A)thread
B)warp
C)grid
D)block
Q3) The __________ is designed specifically to be optimized for fast three-dimensional (3D)graphics rendering and video processing.
A)CPU
B)GPU
C)CU
D)ALU
Q4) In the CPU the control logic and __________ make up the majority of the CPU's real estate.
Q5) The _________ GPU has a total of 16 SMs x 32 CUDA cores / SM,or 512 CUDA cores.
Q6) GPGPU is a computing platform and programming model created by NVIDIA.
A)True
B)False
21
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Chapter 20: Control Unit Operation
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Q1) A cycle is made up of a sequence of micro-operations.
A)True
B)False
Q2) The __________ module handles multiple levels of interrupt signals.
A)interrupt control
B)incrementer address latch
C)serial I / O control
D)decrementer address latch
Q3) The "read word from memory" and "increment PC" actions cannot be used simultaneously because they will interfere with each other.
A)True
B)False
Q4) The control unit controls the internal flow of data.
A)True
B)False
Q5) The __________ register contains the value to be stored in memory or the last value read from memory.
Q6) Control unit implementation techniques fall into two categories: microprogrammed implementation and ___________ implementation.
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Chapter 21: Microprogrammed Control
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Q1) It is easier to design in hardware than in firmware.
A)True
B)False
Q2) _________ processors,with their simpler instruction format,typically use hardwired control units.
Q3) The principal disadvantage of a microprogrammed unit is that it will be somewhat slower than a hardwired unit of comparable technology.
A)True
B)False
Q4) Two approaches can be taken to organizing the encoded microinstruction into fields: functional and __________.
Q5) In executing a microprogram the address of the next microinstruction to be executed is in which of the following categories?
A)determined by instruction register
B)branch
C)next sequential address
D)all of the above
Q6) The LSI-11 is a good example of a __________ microinstruction approach.
Q7) A sequence of instructions is known as a ___________,or firmware.
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