Introduction to Computer Systems
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Course Introduction
Introduction to Computer Systems provides students with a foundational understanding of how computers work from the ground up. This course covers the key concepts of computer organization, including hardware components, data representation, assembly language programming, memory management, and input/output mechanisms. Students will explore the interaction between software and hardware, gain insight into system-level programming, and examine fundamental operating system concepts. By the end of the course, students will develop an appreciation for the complexities of computer systems and be able to analyze and troubleshoot common computer architecture and system-level issues.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Chapter 1: Basic Concepts and Computer Evolution
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Q1) Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures.
A)True
B)False
Answer: True
Q2) The __________ architecture is the architecture of IBM's mainframe product line.
Answer: System / 370
Q3) When data are moved over longer distances,to or from a remote device,the process is known as __________.
A)data communications
B)registering
C)structuring
D)data transport
Answer: A
Q4) Computer organization refers to attributes of a system visible to the programmer.
A)True
B)False
Answer: False
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Chapter 2: Performance Issues
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Q1) The cache holds recently accessed data.
A)True
B)False
Answer: True
Q2) Traditionally found on a plug-in graphics card,a _________ is used to encode and render 2D and 3D graphics as well as process video.
Answer: GPU (graphics processing units)
Q3) Raw speed is far more important than how a processor performs when executing a given application.
A)True
B)False
Answer: False
Q4) The raw speed of the microprocessor will not achieve its potential unless it is fed a constant stream of work to do in the form of computer instructions.
A)True
B)False
Answer: True
Q5) __________ Law applies to a queuing system. Answer: Little's
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) A __________ register specifies the address in memory for the next read or write. Answer: memory address (MAR)
Q2) The von Neumann architecture is based on which concept?
A)data and instructions are stored in a single read-write memory
B)the contents of this memory are addressable by location
C)execution occurs in a sequential fashion
D)all of the above
Answer: D
Q3) The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.
A)link
B)protocol
C)routing
D)physical
Answer: C
Q4) There are three important groups of DLLPs used in managing a link: flow control packets, _________________ ,and TLP ACK and NAK packets.
Answer: power management packets
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Chapter 4: Cache Memory
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Q1) The L1 cache is slower than the L3 cache.
A)True
B)False
Q2) The Pentium 4 processor core consists of four major components: fetch / decode unit,out-of-order execution logic,memory subsystem,and __________.
Q3) With write back updates are made only in the cache.
A)True
B)False
Q4) When using the __________ technique all write operations made to main memory are made to the cache as well.
A)write back
B)LRU
C)write through
D)unified cache
Q5) The processor requires its own local memory.
A)True
B)False
Q6) The three key characteristics of memory are capacity,access time,and _______.
Q7) External,nonvolatile memory is referred to as ___________ or auxiliary memory.
Page 6
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Chapter 5: Internal Memory
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Q1) In earlier computers the most common form of random-access storage for computer main memory employed an array of doughnut-shaped ferromagnetic loops referred to as __________.
Q2) __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.
A)DDR2
B)RDRAM
C)CDRAM
D)DDR3
Q3) A _________ RAM is made with cells that store data as charge on capacitors.
Q4) ___________ is a new type of Magnetic RAM,which features non-volatility,fast writing / reading speed,and high programming endurance and zero standby power.
Q5) The simplest of the error-correcting codes is the _________ code.
Q6) A __________ error is a random,nondestructive event that alters the contents of one or more memory cells without damaging the memory.
Q7) The two traditional forms of RAM used in computers are DRAM and SRAM. A)True B)False
Page 7
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Chapter 6: External Memory
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Q1) Data is organized on the platter in a concentric set of rings called ________.
Q2) In most contemporary systems fixed-length sectors are used,with _________ bytes being the nearly universal sector size.
A)64
B)128
C)256
D)512
Q3) RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance.
A)True
B)False
Q4) SSD performance has a tendency to speed up as the device is used.
A)True
B)False
Q5) __________ heads are used in sealed drive assemblies that are almost free of contaminants and the head is actually an aerodynamic foil that rests lightly on the platter's surface when the disk is motionless.
Q6) The time required to move the disk arm to the required track is the __________.
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Chapter 7: Input Output
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Q1) An external device connected to an I / O module is often referred to as a __________ device.
Q2) When the processor,main memory,and I / O share a common bus,two modes of addressing are possible: memory mapped and ________.
Q3) A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device.
A)True
B)False
Q4) The U.S.national version of the International Reference Alphabet is referred to as __________.
Q5) A set of I / O modules is a key element of a computer system.
A)True
B)False
Q6) The ________ contains I / O protocols that are mapped on to the transport layer.
A)cable
B)application
C)common transport
D)physical
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Chapter 8: Operating System Support
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Q1) A _________ is a special type of programming language used to provide instructions to the monitor.
A)job control language
B)multiprogram
C)kernel
D)utility
Q2) In an _________ system the user / programmer interacts directly with the computer,usually through a keyboard / display terminal to request the execution of a job or to perform a transaction.
Q3) The __________ ,or nucleus,contains the most frequently used functions in the OS.
Q4) The five defined states for a process are: new,ready,waiting,halted,and ________.
Q5) Privileged instructions are certain instructions that are designated special and can be executed only by the monitor.
A)True
B)False
Q6) _________ paging means that each page of a process is brought in only when it is needed.
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Chapter 9: Number Systems
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Q1) Hexadecimal notation is only used for representing integers.
A)True
B)False
Q2) In the decimal system,________ different digits are used to represent numbers with a base of 10.
Q3) Binary digits grouped into sets of four bits are called a _________.
Q4) The _________ system has only two digits,0 and 1.
Q5) In a __________ number system,each number is represented by a string of digits in which each digit position i has an associated weight ri,where r is the radix of the number system.
Q6) Hexadecimal has a base of _________.
A)2
B)8
C)10
D)16
Q7) Another term for "base" is __________.
A)radix
B)integer
C)position
D)digit
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Chapter 10: Computer Arithmetic
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Q1) "To subtract one number from another,take the twos complement of the subtrahend and add it to the minuend" is the _________ rule.
Q2) If two numbers are added,and they are both positive or both negative,then _________ occurs if and only if the result has the opposite sign.
Q3) A __________ is one in which the most significant digit of the significand is nonzero.
Q4) ________ is when the result may be larger than can be held in the word size being used.
A)Overflow
B)Arithmetic shift
C)Underflow
D)Partial product
Q5) When the divisor is able to divide the number,a 1 is placed in the quotient and the divisor is subtracted from the partial dividend; the result is referred to as a ________.
Q6) __________ format is a fully specified,fixed-length binary encoding that allows data interchange between different platforms and that can be used for storage.
Q7) The use of subnormal numbers is referred to as _________ underflow.
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Chapter 11: Digital Logic
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Q1) The basic logical operations of Boolean algebra are AND,OR,and ________.
Q2) Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained.
A)True
B)False
Q3) A ________ is an interconnected set of gates whose output at any time is a function only of the input at that time.
Q4) Binary addition is exactly the same as Boolean algebra.
A)True
B)False
Q5) In the absence of parentheses,the AND operation takes precedence over the OR operation.
A)True
B)False
Q6) Claude Shannon,a research assistant in the Electrical Engineering Department at M.I.T.,proposed the basic principles of Boolean algebra.
A)True
B)False
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Chapter 12: Characteristics and Functions
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Q1) Zero-address instructions are applicable to a special memory organizations called a _________,which is a last-in-first-out set of locations.
Q2) ________ instructions operate on the bits of a word as bits rather than as numbers,providing capabilities for processing any other type of data the user may wish to employ.
A)Logic
B)Arithmetic
C)Memory
D)Test
Q3) ARM processors support data types of 8 (byte),16 (halfword), and 32 (word)bits in length.
A)True
B)False
Q4) The instruction set is the programmer's means of controlling the processor.
A)True
B)False
Q5) _________ instructions are those that can be executed only while the processor is in a certain privileged state or is executing a program in a special privileged area of memory.
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Chapter 13: Addressing Modes and Formats
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Q1) __________ is a design principle employed in designing the PDP-10 instruction set.
A)Orthogonality
B)Completeness
C)Direct addressing
D)All of the above
Q2) __________ explicitly specifies which segment register an instruction should use,overriding the default segment-register selection generated by the x86 for that instruction.
Q3) The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer.
A)PDP-1
B)PDP-8
C)PDP-11
D)PDP-10
Q4) The value of the mode field determines which addressing mode is to be used. A)True
B)False
Q5) The simplest form of addressing is __________ addressing.
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Chapter 14: Processor Structure and Function
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Q1) An instruction cycle includes the following stages: fetch,execute,and _______.
Q2) A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.
A)True
B)False
Q3) The ________ controls the movement of data and instructions into and out of the processor.
A)control unit
B)ALU
C)shifter
D)branch
Q4) It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.
A)True
B)False
Q5) _________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.
Q6) Data are exchanged with the processor from external memory through a
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Chapter 15: Reduced Instruction Set Computers
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Q1) With simple,one cycle instructions,there is little or no need for microcode.
A)True
B)False
Q2) The acronym SPARC stands for __________.
Q3) The MIPS R4000 processor chip is partitioned into two sections,one containing the CPU and the other containing a _________ for memory management.
Q4) To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.
A)True
B)False
Q5) Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program.
A)True
B)False
Q6) The acronym RISC stands for __________.
Q7) ________ can improve performance by reducing loop overhead,increasing instruction parallelism by improving pipeline performance,and improving register,data cache,or TLB locality.
Q8) The acronym CISC stands for _________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.
Q2) The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.
Q3) ________ refers to the process of initiating instruction execution in the processor's functional units.
A)Instruction issue
B)In-order issue
C)Out-of-order issue
D)Procedural issue
Q4) Utilizing a branch target buffer (BTB),the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions. A)486
B)Pentium
C)Intel Core
D)Pentium Pro
Q5) An alternative to _________ is a scoreboarding.
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Chapter 17: Parallel Processing
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Q1) The four principal approaches to multithreading are: interleaved (fine-grained),blocked (coarse-grained),simultaneous,and ________.
Q2) The most important measure of performance for a processor is the rate at which it executes instructions.
A)True
B)False
Q3) With multithreading the instruction stream is divided into several smaller streams,known as threads,such that the threads can be executed in parallel.
A)True
B)False
Q4) The four deployment models defined by NIST are: public cloud,private cloud,community cloud,and __________ cloud.
Q5) An attractive feature of an SMP is that the existence of multiple processors is transparent to the user.
A)True
B)False
Q6) The four states of the MESI protocol are: modified,shared,invalid,and ______.
Q7) _________ is the easiest multithreading approach to implement.
Page 19
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Chapter 18: Multicore Computers
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Q1) _______ applications embrace threading in a fundamental way.
A)Multi-instance
B)Multi-process
C)Java
D)Threaded
Q2) ________ is a multithreaded process that provides scheduling and memory management for Java applications.
Q3) __________ applications are characterized by having a small number of highly threaded processes.
Q4) ________ threading is when many similar or identical tasks are spread across multiple processors.
Q5) An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.
A)True
B)False
Q6) With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.
A)True
B)False
Page 20
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) A kernel typically will have few to no branching statements.
A)True
B)False
Q2) Threads are uniformly bundled in _________ .
Q3) All but one set of GPU processor cores will be idle,while one SM is bearing the full processing load.
A)True
B)False
Q4) The __________ is designed specifically to be optimized for fast three-dimensional (3D)graphics rendering and video processing.
A)CPU
B)GPU
C)CU
D)ALU
Q5) The fundamental building block of the Gen8 architecture is the ________ unit.
Q6) ___________ is a GPU processing technology.
A)Fermi
B)Kepler
C)Maxwell
D)All of the above
Page 21
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Chapter 20: Control Unit Operation
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Q1) Each of the smaller cycles involves a series of steps,each of which involves the processor registers,referred to as _________.
Q2) The ____________ generated by the control unit cause the opening and closing of logic gates,resulting in the transfer of data to and from registers and the operation of the ALU.
Q3) In a __________ implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals,which are the control signals.
Q4) The _____________ must control the state of the instruction cycle.
Q5) The execution of a program consists of the sequential execution of instructions. A)True B)False
Q6) The __________ register contains the value to be stored in memory or the last value read from memory.
Q7) The __________ register specifies the address in memory for a read or write operation.
Q8) The _________ of a processor generates the control signals that cause each micro-operation to be executed.
Page 22
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Chapter 21: Microprogrammed Control
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Q1) Microprogramming became a popular technique for implementing the control unit of CISC processors.
A)True
B)False
Q2) The _________ is a 32-bit ALU with 64 registers that can be configured to operate as four 8-bit ALUs,two 16-bit ALUs,or a single 32-bit ALU.
A)PDP-11
B)8832
C)3033
D)8818
Q3) A _________ is a combinatorial circuit that generates an address based on the microinstruction,the machine instruction,the microinstruction program counter,and an interrupt register.
A)microsequencer
B)vertical microinstruction
C)translation array
D)control word
Q4) In a __________ microinstruction every bit in the control field attaches to a control line.
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