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Digital Systems Design introduces students to the principles and practices of designing digital electronic systems, focusing on the fundamental building blocks such as logic gates, multiplexers, flip-flops, and counters. The course covers combinational and sequential logic circuits, system modeling using hardware description languages (HDLs) like VHDL or Verilog, and the design and implementation of programmable devices including FPGAs. Emphasis is placed on the analysis, synthesis, and optimization of digital circuits, as well as practical aspects of testing and troubleshooting. Through theoretical learning and hands-on laboratory experience, students develop the skills necessary to design, implement, and evaluate digital systems for various engineering applications.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Q1) Architectural attributes include __________ .
A)I / O mechanisms
B)control signals
C)interfaces
D)memory technology used
Answer: A
Q2) The number of bits used to represent various data types is an example of an architectural attribute.
A)True
B)False
Answer: True
Q3) When data are received from or delivered to a device that is directly connected to the computer,the process is known as __________.
Answer: input / output (I / O)
Q4) The _________ controls the operation of the CPU and hence the computer. Answer: control unit
Q5) The major structural components of the CPU are: control unit,register,CPU interconnection,and __________.
Answer: arithmetic and logic unit (ALU)
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Q1) Traditionally found on a plug-in graphics card,a _________ is used to encode and render 2D and 3D graphics as well as process video.
Answer: GPU (graphics processing units)
Q2) The best-known collection of benchmark suites is defined and maintained by an industry consortium known as __________.
Answer: System Performance Evaluation Corporation (SPEC)
Q3) A(n)__________ Mean is a good candidate for comparing the execution time performance of several systems.
A)Composite
B)Arithmetic
C)Harmonic
D)Evaluation
Answer: B
Q4) Cloud service providers use massive high-performance banks of servers to satisfy high-volume,high-transaction-rate applications for a broad spectrum of clients.
A)True
B)False
Answer: True
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Q1) The _________ lines are used to control the access to and the use of the data and address lines.
Answer: control
Q2) A _________ register contains the data to be written into memory or receives the data read from memory.
Answer: memory buffer (MBR)
Q3) At a top level,a computer consists of CPU,memory,and I / O components.
A)True
B)False
Answer: True
Q4) Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies,Princeton.
A)John Maulchy
B)John von Neumann
C)Herman Hollerith
D)John Eckert
Answer: B
Q5) A __________ is a communication pathway connecting two or more devices. Answer: bus
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Q1) In reference to access time to a two-level memory,a _________ occurs if an accessed word is not found in the faster memory.
A)miss
B)hit
C)line
D)tag
Q2) Internal memory capacity is typically expressed in terms of _________.
A)hertz
B)nanos
C)bytes
D)LOR
Q3) __________ computing deals with super computers and their software.
Q4) The __________ units execute micro-operations,fetching the required data from the L1 data cache and temporarily storing results in registers.
Q5) External memory is often equated with main memory.
A)True
B)False
Q6) The ________ rate is the rate at which data can be transferred into or out of a memory unit.
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Q1) RAM must be provided with a constant power supply.
A)True
B)False
Q2) Which of the following memory types are nonvolatile?
A)erasable PROM
B)programmable ROM
C)flash memory
D)all of the above
Q3) NOR memory is better suited for external memory such as USB flash drives and memory cards.
A)True
B)False
Q4) RAM,ROM,PROM,EPROM,EEPROM,and flash memory are all examples of __________ memory types.
Q5) With _________ the microchip is organized so that a section of memory cells are erased in a single action.
A)flash memory
B)SDRAM
C)DRAM
D)EEPROM
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Q1) When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.
A)multiple sided
B)substrate
C)double sided
D)all of the above
Q2) The _________ strategy employs multiple disk drives and distributes data in such a way as to enable simultaneous access to data from multiple drives,thereby improving I / O performance and allowing easier incremental increases in capacity.
Q3) RAID levels 2 and 3 make use of a _________ access technique in which all member disks participate in the execution of every I / O request.
Q4) There are typically hundreds of sectors per track and they may be either fixed or variable lengths.
A)True
B)False
Q5) The _________ disk is a small,flexible platter and the least expensive type of disk.
Q6) The time required to move the disk arm to the required track is the __________.
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Q1) An I / O module that is quite primitive and requires detailed control is usually referred to as an _________.
A)I / O command
B)I / O controller
C)I / O channel
D)I / O processor
Q2) A ________ is used to connect storage systems,routers,and other peripheral devices to an InfiniBand switch.
A)target channel adapter
B)InfiniBand switch
C)host channel adapter
D)subnet
Q3) A disadvantage of memory-mapped I / O is that valuable memory address space is used up.
A)True
B)False
Q4) When the processor,main memory,and I / O share a common bus,two modes of addressing are possible: memory mapped and ________.
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Q1) ________ is when the processor spends most of its time swapping pages rather than executing instructions.
A)Swapping
B)Thrashing
C)Paging
D)Multitasking
Q2) The _________ is a program that manages the computer's resources,provides services for programmers,and schedules the execution of other programs.
Q3) The OS maintains a __________ for each process that shows the frame location for each page of the process.
A)kernel
B)page table
C)TLB
D)logical address
Q4) The ________ scheduler is also known as the dispatcher.
A)long-term
B)medium-term
C)short-term
D)I / O
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Q1) A number with both an integer and fractional part has digits raised to both positive and negative powers of 10.
A)True
B)False
Q2) Binary digits grouped into sets of four bits are called a _________.
Q3) Although convenient for computers,the binary system is exceedingly cumbersome for human beings.
A)True
B)False
Q4) The decimal system has a radix of 100.
A)True
B)False
Q5) In the decimal system,_________ is the maximum value that a position can hold before it flips over into the next higher position.
Q6) Another term for "base" is __________.
A)radix
B)integer
C)position
D)digit
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Q1) _________ are included in IEEE 754 to handle cases of exponent underflow.
A)Subnormal numbers
B)Guard bits
C)Normal numbers
D)Radix points
Q2) It is not necessary for the ALU to signal when overflow occurs.
A)True
B)False
Q3) Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers.
A)True
B)False
Q4) For each 1 on the multiplier,an add and a shift operation are required; but for each 0 only a shift is required.
A)True
B)False
Q5) _________ occurs when an arithmetic operation results in an absolute value greater than can be expressed with an exponent of 128.
Q6) The use of subnormal numbers is referred to as _________ underflow.
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Q1) Logical functions are implemented by the interconnection of decoders.
A)True
B)False
Q2) In general,a decoder has n inputs and 2S1U1P1n S1S1P0outputs.
A)True
B)False
Q3) The ________ flip-flop has two inputs and all possible combinations of input values are valid.
A)J-K
B)D
C)S-R
D)clocked S-R
Q4) Binary addition is exactly the same as Boolean algebra.
A)True
B)False
Q5) A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS)form.
A)True
B)False
Q6) The simplest form of sequential circuit is the _________.
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Q1) The focus of MMX technology is multimedia programming.
A)True
B)False
Q2) The address of the next instruction to be fetched must be a real address,not a virtual address.
A)True
B)False
Q3) It has become common practice to use a symbolic representation of machine instructions.
A)True
B)False
Q4) A(n)_________ expresses operations in a concise algebraic form using variables.
A)opcode
B)high-level language
C)machine language
D)register
Q5) Procedures do not allow programming tasks to be subdivided into smaller units.
A)True
B)False
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Q1) "All instructions should have the 'natural' number of operands" and "all operands should have the same generality in specification" are two criteria that were used in designing the __________ instruction format.
Q2) For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.
A)True
B)False
Q3) __________ is when the increment or decrement of the index register after each reference to it is done automatically as part of the same instruction cycle.
Q4) For the _________ mode,the operand is included in the instruction.
A)immediate
B)base
C)register
D)displacement
Q5) Programs written in assembly language are translated into machine language by an _________.
Q6) The simplest form of addressing is __________ addressing.
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Q1) Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.
A)True
B)False
Q2) While the processor is in user mode the program being executed is unable to access protected system resources or to change mode,other than by causing an exception to occur.
A)True
B)False
Q3) The ________ determines the opcode and the operand specifiers.
A)decode instruction
B)fetch operands
C)calculate operands
D)execute instruction
Q4) Condition codes facilitate multiway branches.
A)True
B)False
Q5) The three types of data hazards are: read after write (RAW),write after write (WAW),and _________.
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Q1) A large number of general-purpose registers,and / or the use of compiler technology to optimize register usage,a limited and simple instruction set,and an emphasis on optimizing the instruction pipeline are all key elements of _________ architectures.
Q2) Individual variables,compiler assigned global variables,register addressing,and multiple operands addressed and accessed in one cycle are characteristics of __________ organizations.
Q3) __________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.
Q4) The acronym SPARC stands for __________.
Q5) RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.
A)True
B)False
Q6) Cache memory is a much faster memory than the register file. A)True
B)False
Q7) The acronym CISC stands for _________.
Q8) The acronym RISC stands for __________.
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Q1) ARM architecture has yet to implement superscalar techniques in the instruction pipeline.
A)True
B)False
Q2) Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?
A)duplication of resources
B)out-of-order issue
C)renaming
D)all of the above
Q3) The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.
Q4) ________ indicates whether this micro-op is scheduled for execution,has been dispatched for execution,or has completed execution and is ready for retirement.
A)State
B)Memory address
C)Micro-op
D)Alias register
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Q1) With no multithreading,_________ is the simple pipeline found in traditional RISC and CISC machines.
A)superscalar
B)single-threaded scalar
C)blocked multithreaded scalar
D)interleaved multithreaded scalar
Q2) SMPs,clusters,and NUMA systems fit into the ________ category of computer systems.
A)SISD
B)MIMD
C)SIMD
D)MISD
Q3) Computer systems that fall into the __________ category have a sequence of data that is transmitted to a set of processors,each of which executes a different instruction sequence.
Q4) A ________ is a group of interconnected,whole computers working together as a unified computing resource that can create the illusion of being one machine.
Q5) The four states of the MESI protocol are: modified,shared,invalid,and ______.
Q6) _________ is the easiest multithreading approach to implement.
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Q1) The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15 cores.
A)True
B)False
Q2) The _________ is a cache-coherent,point-to-point link based electrical interconnect specification for Intel processors and chipsets that enable high-speed communications among connected processor chips.
Q3) The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.
A)True
B)False
Q4) The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.
A)True B)False
Q5) The principal building block of the IBM zEnterprise EC12 mainframe is the
Q6) A single piece of silicon is called a ________.
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Q1) The fundamental building block of the Gen8 architecture is the ________ unit.
Q2) All but one set of GPU processor cores will be idle,while one SM is bearing the full processing load.
A)True
B)False
Q3) A group of threads assigned to a particular SM is a __________ .
A)block
B)grid
C)unit
D)kernel
Q4) A subslice includes a unit called the _________,which is used for sampling texture and image surfaces.
A)stride
B)sampler
C)EU
D)floating-point
Q5) The first NVIDIA GPU with added GPGPU support hardware was the _________ .
Q6) __________ is a parallel computing platform and programming model created by NVIDIA and implemented by the GPUs that they produce.
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Q1) The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices.
A)True
B)False
Q2) The prefix __________ refers to the fact that each step is very simple and accomplishes very little.
Q3) Control unit implementation techniques fall into two categories: microprogrammed implementation and ___________ implementation.
Q4) Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations.
A)True
B)False
Q5) The timing of processor operations is synchronized by the __________ and controlled by the control unit with control signals.
Q6) The key control unit inputs are: clock,instruction register,control signals from control bus,and _________.
Q7) The __________ register specifies the address in memory for a read or write operation.
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Q1) Each microinstruction cycle is made up of two parts: fetch and _________.
Q2) It is easier to design in hardware than in firmware.
A)True
B)False
Q3) It is important to design compact,time-efficient techniques for microinstruction branching.
A)True
B)False
Q4) The _________ contains the address of the next microinstruction to be read.
A)control memory
B)control address register
C)control word
D)control buffer register
Q5) The _________ is a 32-bit ALU with 64 registers that can be configured to operate as four 8-bit ALUs,two 16-bit ALUs,or a single 32-bit ALU.
A)PDP-11
B)8832
C)3033
D)8818
Q6) A sequence of instructions is known as a ___________,or firmware.
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