Computer Engineering Fundamentals
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Course Introduction
Computer Engineering Fundamentals introduces students to the essential principles and practices at the intersection of computer science and electrical engineering. The course covers foundational topics such as digital logic design, microprocessor architecture, computer organization, memory systems, input/output devices, and basic networking concepts. Students will gain a solid understanding of how computers are constructed and how hardware and software interact to perform computing tasks. Through theoretical lessons and practical exercises, the course prepares students for more advanced studies in computer engineering, embedded systems, and related technology fields.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Chapter 1: Basic Concepts and Computer Evolution
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Q1) __________ refers to those attributes of a system visible to a programmer.
Answer: Computer architecture
Q2) It is a(n)_________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.
A)architectural
B)memory
C)mechanical
D)organizational
Answer: D
Q3) Control signals,interfaces between the computer and peripherals,and the memory technology used are all examples of _________ attributes. Answer: organizational
Q4) When data are received from or delivered to a device that is directly connected to the computer,the process is known as __________.
Answer: input / output (I / O)
Q5) The four main structural components of the computer are: main memory,I / O,system interconnection,and __________.
Answer: central processing unit (CPU)
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Chapter 2: Performance Issues
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Q1) The best known of the SPEC benchmark suites is __________ .
A)SPEC CPU2006
B)SPECjvm2008
C)SPECsfs2008
D)SPEC SC2013
Answer: A
Q2) __________ enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed.
Answer: Speculative execution
Q3) The __________ is a relatively small fast memory interposed between a larger,slower memory and the logic that accesses the larger memory.
A)peripheral
B)cache
C)processor
D)arithmetic and logic unit
Answer: B
Q4) ___________ is the ability to issue more than one instruction in every processor clock cycle.
Answer: Superscalar execution
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) A(n)________ interrupt is generated by an I / O controller to signal normal completion of an operation,request service from the processor,or to signal a variety of error conditions.
Answer: I / O
Q2) There are three important groups of DLLPs used in managing a link: flow control packets, _________________ ,and TLP ACK and NAK packets.
Answer: power management packets
Q3) The von Neumann architecture is based on which concept?
A)data and instructions are stored in a single read-write memory
B)the contents of this memory are addressable by location
C)execution occurs in a sequential fashion
D)all of the above
Answer: D
Q4) The _________ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data.
Answer: flow control
Q5) A __________ is a communication pathway connecting two or more devices. Answer: bus
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Chapter 4: Cache Memory
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Q1) The three performance parameters for memory are: access time,transfer rate,and
Q2) The unit of transfer must equal a word or an addressable unit.
A)True B)False
Q3) The Pentium 4 processor core consists of four major components: fetch / decode unit,out-of-order execution logic,memory subsystem,and __________.
Q4) For set-associative mapping the cache control logic interprets a memory address as three fields: Set,Word,and __________.
Q5) _________ is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match,and to do this for all words simultaneously,thus retrieving a word based on a portion of its contents rather than its address.
Q6) All of the Pentium processors include two on-chip L1 caches,one for data and one for instructions.
A)True B)False
Q7) __________ memory consists of peripheral storage devices,such as disk and tape.
Page 6
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Chapter 5: Internal Memory
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Q1) __________ can be caused by harsh environmental abuse,manufacturing defects,and wear.
A)SEC errors
B)Hard errors
C)Syndrome errors
D)Soft errors
Q2) The simplest of the error-correcting codes is the _________ code.
Q3) Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.
A)True
B)False
Q4) In earlier computers the most common form of random-access storage for computer main memory employed an array of doughnut-shaped ferromagnetic loops referred to as __________.
Q5) A DDR3 module transfers data at a clock rate of __________ Mbps.
A)600 to 1200
B)800 to 2133
C)1000 to 2000
D)1500 to 3000
Q6) A _________ RAM is made with cells that store data as charge on capacitors.
Page 7
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Chapter 6: External Memory
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Q1) Data are recorded on and later retrieved from the disk via a conducting coil named the _________.
Q2) The transfer time to or from the disk does not depend on the rotation speed of the disk.
A)True
B)False
Q3) A removable disk can be removed and replaced with another disk.
A)True
B)False
Q4) The SSDs now on the market use a type of semiconductor memory referred to as flash memory.
A)True
B)False
Q5) ________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center.
A)Constant angular velocity (CAV)
B)Magnetoresistive
C)Constant linear velocity (CLV)
D)Seek time
Q6) The time required to move the disk arm to the required track is the __________.
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Chapter 7: Input Output
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Q1) The disadvantage of the software poll is that it is time consuming.
A)True
B)False
Q2) A ________ controls multiple high-speed devices and,at any one time,is dedicated to the transfer of data with one of those devices.
Q3) It is the responsibility of the processor to periodically check the status of the I / O module until it finds that the operation is complete.
A)True
B)False
Q4) An I / O module that takes on most of the detailed processing burden,presenting a high-level interface to the processor,is usually referred to as an _________.
A)I / O channel
B)I / O command
C)I / O controller
D)device controller
Q5) ________ enables servers,remote storage,and other network devices to be attached in a central fabric of switches and links,connecting up to 64,000 servers,storage systems,and networking devices.
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Chapter 8: Operating System Support
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Q1) With demand paging it is necessary to load an entire process into main memory.
A)True
B)False
Q2) A _________ is a collection of memory regions.
A)APX
B)nucleus
C)domain
D)page table
Q3) Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS.
A)utility
B)multitasking
C)JCL
D)logical address
Q4) With _________ the virtual address is the same as the physical address.
A)unsegmented unpaged memory
B)unsegmented paged memory
C)segmented unpaged memory
D)segmented paged memory
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Chapter 9: Number Systems
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Q1) Another term for "base" is __________.
A)radix
B)integer
C)position
D)digit
Q2) Binary digits grouped into sets of four bits are called a _________.
Q3) Hexadecimal notation is more compact than binary notation.
A)True
B)False
Q4) Because of the inherent binary nature of digital computer components,all forms of data within computers are represented by various binary codes.
A)True
B)False
Q5) In any number,the rightmost digit is referred to as the most significant digit.
A)True
B)False
Q6) The decimal system has a radix of _________.
Q7) Hexadecimal notation is only used for representing integers.
A)True
B)False
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Chapter 10: Computer Arithmetic
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Q1) The register contains additional bits,called __________,which are used to pad out the right end of the significand with 0s.
Q2) __________ means that the number is too small to be represented and it may be reported as 0.
A)Negative underflow
B)Exponent underflow
C)Positive underflow
D)Significand underflow
Q3) Overflow can only occur if there is a carry.
A)True
B)False
Q4) IEEE 754-2008 defines an __________ format as a format with a precision and range that are defined under user control.
Q5) Positive numbers less than 2-127 are called ________.
A)positive underflow
B)positive overflow
C)negative underflow
D)negative overflow
Q6) The use of subnormal numbers is referred to as _________ underflow.
Page 12
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Chapter 11: Digital Logic
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Q1) ________ are used in digital circuits to control signal and data routing.
A)Multiplexers
B)Program counters
C)Flip-flops
D)Gates
Q2) The unary operation _________ inverts the value of its operand.
A)OR
B)NOT
C)NAND
D)XOR
Q3) An asynchronous counter is also referred to as a ________ because the change that occurs to increment the counter starts at one end and "ripples" through to the other end.
Q4) A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.
A)SPLD
B)FPGA
C)PAL
D)PLA
Page 13
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Chapter 12: Characteristics and Functions
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Q1) The instruction set is the programmer's means of controlling the processor.
A)True
B)False
Q2) The ________ specifies the operation to be performed.
A)source operand reference
B)opcode
C)next instruction reference
D)processor register
Q3) The collection of different instructions that the processor can execute is referred to as the processor's _________.
Q4) Intel's ________ technology is a set of highly optimized instructions for multimedia tasks.
Q5) The focus of MMX technology is multimedia programming.
A)True
B)False
Q6) _________ instructions are those that can be executed only while the processor is in a certain privileged state or is executing a program in a special privileged area of memory.
Q7) ________ instructions are those that change the format or operate on the format of data.
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Chapter 13: Addressing Modes and Formats
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Q1) In a system without virtual memory,the effective address is a virtual address or a register.
A)True
B)False
Q2) The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field.
A)True
B)False
Q3) Not common on contemporary architectures,___________ requires only one memory reference and no special calculation,but provides only a limited address space.
Q4) If a programmer wished to program directly in machine language it would be necessary to enter the program as ________ data.
Q5) The __________ byte consists of three fields: the Scale field,the Index field and the Base field.
A)SIB
B)VAX
C)PDP-11
D)ModR / M
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Chapter 14: Processor Structure and Function
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Q1) The ARM architecture supports _______ execution modes.
A)2
B)8
C)11
D)7
Q2) Data are exchanged with the processor from external memory through a
Q3) The allocation of control information between registers and memory are not considered to be a key design issue.
A)True
B)False
Q4) __________ are bits set by the processor hardware as the result of operations.
A)MIPS
B)Condition codes
C)Stacks
D)PSWs
Q5) The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.
A)True
B)False
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Q6) An instruction cycle includes the following stages: fetch,execute,and _______.
Chapter 15: Reduced Instruction Set Computers
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Q1) Almost all RISC instructions use simple register addressing.
A)True
B)False
Q2) When using graph coloring,nodes that share the same color cannot be assigned to the same register.
A)True
B)False
Q3) The acronym RISC stands for __________.
Q4) The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses,registers,and the ALU.
A)16
B)32
C)64
D)128
Q5) _________ determines the control and pipeline organization.
A)Calculation
B)Execution sequencing
C)Operations performed
D)Operands used
Q6) The acronym CISC stands for _________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) ________ indicates whether this micro-op is scheduled for execution,has been dispatched for execution,or has completed execution and is ready for retirement.
A)State
B)Memory address
C)Micro-op
D)Alias register
Q2) The ________ protects critical data used by the operating system from user applications,separating processing tasks by disallowing access to each other's data,disabling access to memory regions,allowing memory regions to be defined as read-only,and detecting unexpected memory accesses that could potentially break the system.
Q3) The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.
Q4) In the scalar organization there are multiple functional units,each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.
A)True
B)False
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Chapter 17: Parallel Processing
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Q1) A ________ is a group of interconnected,whole computers working together as a unified computing resource that can create the illusion of being one machine.
Q2) _________ causes results issuing from one functional unit to be fed immediately into another functional unit and so on.
A)Chaining
B)Rollover
C)Passive standby
D)Pipelining
Q3) The __________ is the simplest mechanism for constructing a multiprocessor system.
Q4) A _________ problem arises when multiple copies of the same data can exist in different caches simultaneously,and if processors are allowed to update their own copies freely,an inconsistent view of memory can result.
A)cache coherence
B)cluster
C)failover
D)failback
Q5) _________ is the easiest multithreading approach to implement.
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Chapter 18: Multicore Computers
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Q1) With _______,register banks are replicated so that multiple threads can share the use of pipeline resources.
A)SMT
B)pipelining
C)scalar
D)superscalar
Q2) The generic timer handles interrupt detection and interrupt prioritization.
A)True
B)False
Q3) __________ are characterized by the ability to support thousands of parallel execution threads
A)CPUs
B)QPIs
C)GPUs
D)ISAs
Q4) The _________ is a cache-coherent,point-to-point link based electrical interconnect specification for Intel processors and chipsets that enable high-speed communications among connected processor chips.
Q5) A single piece of silicon is called a ________.
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) All but one set of GPU processor cores will be idle,while one SM is bearing the full processing load.
A)True
B)False
Q2) The first NVIDIA GPU with added GPGPU support hardware was the _________ .
Q3) __________ is a parallel computing platform and programming model created by NVIDIA and implemented by the GPUs that they produce.
Q4) CUDA C is a C / C++ based language.
A)True
B)False
Q5) The _________ performs transcendental operations,such as cosine,sine,reciprocal,and square root,in a single clock cycle.
A)SM
B)SIMD
C)SFU
D)FMA
Q6) The grid and the block need to have the same dimensions.
A)True
B)False
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Chapter 20: Control Unit Operation
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Q1) The execution of a program consists of the sequential execution of instructions.
A)True
B)False
Q2) The control unit is the engine that runs the entire computer.
A)True
B)False
Q3) In a __________ implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals,which are the control signals.
Q4) The ________ portion of the control unit issues a repetitive sequence of pulses.
A)instruction register
B)flag
C)control bus signals
D)clock
Q5) The __________ register specifies the address in memory for a read or write operation.
Q6) __________ is when the control unit examines the opcode and generates a sequence of micro-operations based on the value of the opcode.
Q7) The _____________ must control the state of the instruction cycle.
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Chapter 21: Microprogrammed Control
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Q1) In a ________ microinstruction a code is used for each action to be performed and the decoder translates this code into individual control signals.
Q2) The terms _________ microprogramming are used to suggest the degree of closeness to the underlying control signals and hardware layout.
A)hard / soft
B)horizontal / vertical
C)direct / indirect
D)packed / unpacked
Q3) Which of the following is a LSI-11 microinstruction?
A)add word
B)test word
C)Jump
D)all of the above
Q4) Microprogramming became a popular technique for implementing the control unit of CISC processors.
A)True
B)False
Q5) The LSI-11 is a good example of a __________ microinstruction approach.
Q6) Each microinstruction cycle is made up of two parts: fetch and _________.
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