College of Engineering

Rhea Dutta

College of Engineering

Computer Engineering

Faculty Mentor: Dr. Baris Taskin

Electrical & Computer Engineering

Ragh Kuttappa Co-Mentor

Automatic Layout Generation for Custom Cells

Modern microprocessors are designed using complementary metal oxide semiconductor (CMOS) logic to design transistor level circuits. Technology scaling and energy efficiency of modern processors require novel techniques to address the growing needs of the semiconductor industry. CMOS logic involves a standard pull-up and pull-down system where energy is often dissipated between high and low transitions. Most recently, charge recovery logic (CRL) has been recognized as a way to recycle power dissipated to power up the designs. CRL can reduce power dissipated by a logic block to improve power efficiency and save on area. CRL employs sinusoidal power-clock signals that require less power for operation. CRL designs require full custom design motivating the need for design automation. In this research project, a methodology to automate the layout design for CRL and CMOS gates is presented. This methodology can be scaled to any technology node and bring down the design time of the layout. On an average the time to design the layout is reduced by 60%. The CRL gates operate at the same frequency of the standard CMOS gates while consuming 40% less power on an average.