VITA Technologies Winter 2020 with Application Guide

p. 5 Editor’s Foreword Kovid Krazy

p. 6 Defining Standards VPX performance boost

Advertiser Index Page Advertiser

Annapolis Micro Systems – 3U VPX chassis is SOSA-aligned and 100Gb Ethernet capable.

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VITA EDITORIAL DIRECTOR Jerry Gipper jerry.gipper@opensysmedia.com GROUP EDITORIAL DIRECTOR John McHale john.mchale@opensysmedia.com

Behlman Electronics, Inc. – Beware of copycats.

Rely on the VPXtra 800B.

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28 13

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ASSISTANT MANAGING EDITOR Lisa Daigle lisa.daigle@opensysmedia.com ASSOCIATE EDITOR Emma Helfrich emma.helfrich@opensysmedia.com ONLINE EVENTS MANAGER Josh Steiger josh.steiger@opensysmedia.com

Behlman Electronics, Inc. – 3 Phase. 3U. 1 Choice.

CREATIVE DIRECTOR Stephanie Sweet stephanie.sweet@opensysmedia.com SENIOR WEB DEVELOPER Aaron Ganschow aaron.ganschow@opensysmedia.com

Elma Electronic – Award-winning and innovative OpenVPX solutions

WEB DEVELOPER Paul Nelson paul.nelson@opensysmedia.com CONTRIBUTING DESIGNER Joann Toth joann.toth@opensysmedia.com EMAIL MARKETING SPECIALIST Drew Kaufman drew.kaufman@opensysmedia.com

LCR Embedded Systems, Inc. – Beat the heat! Rugged VPX packaging

SALES/MARKETING DIRECTOR OF SALES AND MARKETING Tom Varcie tom.varcie@opensysmedia.com (734) 748-9660

Sealevel Systems, Inc. – Thrives in rugged environments.

Lives to test limits.

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MARKETING MANAGER Eric Henry eric.henry@opensysmedia.com (541) 760-5361 STRATEGIC ACCOUNT MANAGER Rebecca Barker rebecca.barker@opensysmedia.com (281) 724-8021

Vector Electronics – VME/VXS/cPCI chassis, backplanes & accessories

STRATEGIC ACCOUNT MANAGER Bill Barron bill.barron@opensysmedia.com (516) 376-9838 STRATEGIC ACCOUNT MANAGER Kathleen Wackowski kathleen.wackowski@opensysmedia.com (978) 888-7367 SOUTHERN CAL REGIONAL SALES MANAGER Len Pettek len.pettek@opensysmedia.com (805) 231-9582 ASSISTANT DIRECTOR OF PRODUCT MARKETING/SALES Barbara Quinlan barbara.quinlan@opensysmedia.com (480) 236-8818

Profile Index Advertiser

AVIONICS AIM

Page

INSIDE SALES Amy Russell amy.russell@opensysmedia.com

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COMMUNICATIONS Sponsored by AZ-Com Inc.

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Hartmann Electronic

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INDUSTRIAL Sponsored by Smart EC (Smart Embedded Computing)

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Smart EC (Smart Embedded Computing) 24 Smart EC (Smart Embedded Computing) 25 OPENVPX Sponsored by Annapolis Micro Systems Annapolis Micro Systems RADAR Interface Concept RUGGED Sponsored by Red Rock Technologies

TAIWAN SALES ACCOUNT MANAGER Patty Wu patty.wu@opensysmedia.com CHINA SALES ACCOUNT MANAGER Judy Wang judywang2000@vip.126.com EUROPEAN MARKETING SPECIALIST Steven Jameson steven.jameson@opensysmedia.com +44 (0)7708976338

www.opensysmedia.com PRESIDENT Patrick Hopper patrick.hopper@opensysmedia.com EXECUTIVE VICE PRESIDENT John McHale john.mchale@opensysmedia.com EXECUTIVE VICE PRESIDENT Rich Nass rich.nass@opensysmedia.com EMBEDDED COMPUTING BRAND DIRECTOR Rich Nass rich.nass@opensysmedia.com

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ECD EDITOR-IN-CHIEF Brandon Lewis brandon.lewis@opensysmedia.com

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TECHNOLOGY EDITOR Curt Schwaderer curt.schwaderer@opensysmedia.com SENIOR EDITOR Sally Cole sally.cole@opensysmedia.com

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ASSOCIATE EDITOR Perry Cohen perry.cohen@opensysmedia.com ASSISTANT EDITOR Tiera Oliver tiera.oliver@opensysmedia.com CREATIVE PROJECTS Chris Rassiccia chris.rassiccia@opensysmedia.com

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Dawn VME Products

25

Interface Concept

26

TE Connectivity

26

TE Connectivity

27

W-IE-NE-R Power Electronics

27

UAV Dawn VME Products

STRATEGIC ACCOUNT MANAGER Glen Sundin glen.sundin@opensysmedia.com (973) 723-9672

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2 | VITA Technologies Application Guide Winter 2020

PROJECT MANAGER Kristine Jennings kristine.jennings@opensysmedia.com MARKETING COORDINATOR Katelyn Albani katelyn.albani@opensysmedia.com FINANCIAL ASSISTANT Emily Verhoeks emily.verhoeks@opensysmedia.com FINANCE Rosemary Kristoff rosemary.kristoff@opensysmedia.com SUBSCRIPTION MANAGER subscriptions@opensysmedia.com CORPORATE OFFICE 1505 N. Hayden Rd. #105 • Scottsdale, AZ 85257 • Tel: (480) 967-5581 REPRINTS WRIGHT’S MEDIA REPRINT COORDINATOR Wyndell Hamilton whamilton@wrightsmedia.com (281) 419-5725

www.vita-technologies.com

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Lives to test limits.

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WINTER 2020 | VOLUME 38 | NUMBER 2

@VitaTechnology

On the cover The VITA Technologies 2020 Application Guide showcases technologies and products based on VITA standards, including those in the avionics, communications, industrial, OpenVPX, radar, rugged, and UAV categories. Featured on the cover: Annapolis Micro Systems – 3U VPX chassis is SOSA-aligned & 100Gb Ethernet capable.

VPX and OpenVPX: Design aspects of enclosure technology » p. 10

FEATURES

10 Technology Feature

By Alexander Jäger, Heitec Electronics

Enclosures

VPX and OpenVPX: Design aspects of enclosure technology

By Alexander Jäger, Heitec Electronics

14 Technology Feature

Packaging with optics

Advancing electronic packaging with optics gives VPX a 450% bandwidth boost

By Mark Benton and Jim Mosier, TE Connectivity

18 Technology Feature Can you really simulate an FPGA device?

Advancing electronic packaging with optics gives VPX a 450% bandwidth boost » p. 14

FPGAs

By Max Taylor-Smith, Entropy Electro-Mechanical Solutions

By Mark Benton and Jim Mosier, TE Connectivity

DEPARTMENTS

5 Editor’s Foreword

Jerry Gipper

KOVID Krazy

6 Defining Standards

Jerry Gipper

VPX performance boost

8 VITA Standards Update VITA Standards Organization activity updates

24 2020 VITA Technologies Application Guide

Can you really simulate an FPGA device? » p. 18

Avionics • Communications • Industrial OpenVPX • Radar • Rugged • UAV

By Max Taylor-Smith, Entropy Electro-Mechanical Solutions

To unsubscribe, email your name, address, and subscription number as it appears on the label to: subscriptions@opensysmedia.com

All registered brands and trademarks within VITA Technologies magazine are the property of their respective owners. ™VPX and its logo is a registered product/trademark of VITA. © 2020 OpenSystems Media © 2020 VITA Technologies enviroink.indd 1

4 | VITA Technologies Application Guide Winter 2020

10/1/08 10:44:38 AM

www.vita-technologies.com

Editor’s Foreword

By Jerry Gipper, Editorial Director @VitaTechnology

jerry.gipper@opensysmedia.com

KOVID Krazy Last spring, I wrote about our entry into the first phase of COVID-19 pandemic with sheltering in place to slow the spread. That went reasonably well for a couple of months, but the natives got restless and now we are breaking new case and death numbers every day, in every corner of the U.S. In fact, our country is leading in nearly every category. We have a new president-elect that has his plate very full right now with getting a COVID plan in place as his first priority. At this point I’m not sure that much can be done now except to “ride it out” as we wait for a vaccine and herd immunity to kick in. On the good news front, as I am writing this, there is talk of a several good vaccines being widely available to the U.S. general public by the end of March. Other countries are on the verge of the same great news.

I’m sure that by now most of you are “Zoom zapped,” weary of all those online video calls. Well over 90% of my human interactions the past several months has been via Zoom. Everything from business meetings to happy hours are now conducted online. I’ve been able to break out by taking four trips away from home since March, all of them in a very COVID-wary fashion. Other than that, it has only been the occasional trip out for supplies and the daily trip to the mailbox out front!

Has anyone besides me noticed how time moves differently?

Every week starts with me wondering how I will make it through the week and then all of a sudden – its Friday! I do find that the lack of deadlines for certain actions driven by travel tend to make me defer projects, as motivation is different or missing.

Fortunately, in the VITA community, we have not experienced any significant changes in business. Standards are still being developed and new products and design wins are announced at a normal pace. VITA standards meetings since March have been virtual and well attended while also being very productive. Members find it easier to participate, especially when all parties are virtual. The face-to-face aspect is still greatly missed in maintaining existing friendships and developing new relationships. Some things are just very difficult to do in a virtual environment, despite some of the clever things that virtual event tools are innovating to engage participants.

I previously contemplated: “What will business look like when we emerge on the other side? Will we snap back to the old ways of doing business or will we see a substantial bump in the use of technology to conduct our lives?” I know that everyone is anxious to get back to life as we previously knew it, but I also am more convinced that much of it will never be the same. The video technology available today has demonstrated that a lot www.vita-technologies.com

Jerry Gipper, VITA editorial director and executive director of the VITA organization, shows off his Halloween 2020 costume.

of routine business travel can easily be replaced with a video conference. Even many office meetings with everyone in the building can be done more productively in a virtual world.

Several companies have come out and stated that more employees will be encouraged, even required, to work from home. Brick and mortar will be replaced by green screens and virtual backgrounds. The travel industry is going to have to adjust their model for the potential shift between business and leisure travel.

I’ve had to make the decision to not hold our annual Embedded Tech Trends event in January. This industry forum gave us the chance to network and share ideas for the coming year.

Networking was the primary focus but because of all the restrictions on travel it has become clear that it will not be possible to accomplish the desired goals for the 2021 event. We’ll definitely be back in 2022 – I’m already scouting suitable venues.

In addition, the VITA org hopes to be back hosting face-to-face standards meetings by July 2021: Our destination in Dallas has been booked!

Next year is the 40th anniversary of the introduction of VMEbus.

The wheels are spinning for ideas on possible ways to celebrate this great milestone. Hopefully, we will be back close enough to normal to allow us to celebrate this milestone in style!

Stay healthy, stay safe.

VITA Technologies Application Guide Winter 2020 |

5

Defining Standards

By Jerry Gipper exec@vita.com

VPX performance boost VITA members have been working on performance improvements to the VPX roadmap for the past several years. The trends: New applications demand everincreasing amounts of bandwidth. At the same time, the community seeks a migration path that preserves the work done over the past 15 years.

Higher data-rate protocols are being designed into OpenVPX systems, enabled by processor-technology advancements supporting higher signal speeds and more cores. Newer protocols such as PCIe Gen 4 and 100GBASE-KR4 Ethernet are being implemented; these protocol standards have road maps for higher data rates, in some cases doubling every two to three years.

When the VPX connector was standardized in VITA 46.0 in 2006, it supported signaling rates of 3.125 Gbaud, with a path toward reaching 6.25 Gbaud. This connector is now implemented in 10 Gbaud applications through advances in board technology and system design. As signaling rates increase above 10 Gbaud, the VPX slot connector needs to evolve to support signal-integrity requirements in the channel.

The effort to boost the data-transfer rates of VPX started a couple of years ago with discussions between the connector suppliers – primarily TE Connectivity – and the module designers and end users wanting more bandwidth. These discussions led to the formation of VITA working groups to address the issue.

The VITA 46.30 working group developed a standard that defines a higherperformance connector that can get VPX to the next level. VITA 46.31 is working on an alternative-footprint connector that may also be standardized in the future.

VITA recently completed the ratification by ANSI and VITA of the ANSI/VITA 46.302020 Higher Data Rate VPX Standard. VITA 46.30 defines a standard for a VPX connector that supports higher data rates, to at least 25 Gbaud, for protocols such as 100GBASE-KR4 Ethernet and PCIe Gen 4. The higher-data-rate connectors compliant to VITA 46.30 are intermateable to legacy VITA 46.0 connectors and follow the same form factor. This standard was ratified under the VITA and ANSI processes, reaching full recognition under the guidance of VITA. VITA 46.30-compliant connectors are part of a system, supporting a channel with signal-integrity requirements in VITA 68.x standards. The format of this standard follows VITA 46.0; because the connector meets the same form factor and is intermateable, most sections refer to VITA 46.0.

A key physical difference with the higher-data-rate connectors as opposed to the original VITA 46.0 connector is the smaller PCB hole size, which is documented in the standard. Compliant pins are reduced in size to reduce crosstalk and minimize impedance discontinuity at the connector/PCB interface.

Hybrid connectors with power, single-ended, and higher-data-rate differential-pair signals in a common connector will have a mix of compliant pin sizes, implementing the smaller pins only where applicable for the higher-data-rate signaling. Examples of these hybrid configurations are connectors for rear-transition modules (with pinouts defined in VITA 46.10) and select SpaceVPX connectors (with pinouts defined in VITA 78.0). The rules in this VITA 46.30 standard define the implementation for higher data rates in these hybrid connectors.

The VITA 46.31 working group, consisting of the same team members, has completed work on VITA 46.31. The connector defined in this standard takes VPX to the same data rates as ANSI/VITA 46.30. A key physical difference with the VITA 46.31 higherdata-rate connectors versus the VITA 46.0 and 46.30 connectors is a short solder tail, which is documented in the standard. Contact tails extend below the connector surface to enter into blind vias in the printed circuit boards and are soldered. This termination approach is intended to reduce crosstalk and also frees up space for components on the opposite side of the board with the elimination of plated through holes.

Hybrid connectors with power, single-ended, and higher-data-rate differential pair signals in a common connector can have a mix of solder tails and compliant pins for connector retention during processing or support power/lower-speed signal contacts.

The VITA 46.31 working group brought the standard to “trial use-only” status as they await final results from ongoing testing of the connector. The long-term goal is to release this version as a full ANSI/VITA standard in the coming month.

Both the ANSI/VITA 46.30-2020: VPX Higher Data Rate standard and the VITA 46.31 VPX: Higher Data Rate, Solder Tail standard are available now.

Discussions regarding data bandwidth never stop. Thoughts about next steps are already under consideration.

6 | VITA Technologies Application Guide Winter 2020

www.vita-technologies.com

BEWARE OF

COPYCATS RELY ON THE ORIGINAL

VPXtra 800B ®

Copycat VPX

THE 3U VPX POWER SUPPLY ALIGNED WITH VITA 62.1 Don’t be fooled by questionable knockoffs! Rely on the military’s choice: the proven original VPXtra® 800B from Behlman. The only VPX solution of its kind built to MIL-STD 704F for mission-critical applications.

Key Features: > 3-phase AC or 270 VDC input > High-power 28 VDC output > Overvoltage, short circuit, over-current and thermal protection > Operates 100 percent through abnormal transients with available holdup card

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VITA Standards Update

By Jerry Gipper jerry.gipper@opensysmedia.com

VITA standards activity updates Note: Since March, the VITA standards meetings have all been virtual-only via WebEx. This update is based on the results of the September meeting. Contact VITA if you are interested in participating in any of these working groups.

Visit the VITA website (http://www.vita.com) for details on upcoming VITA meetings.

ANSI accreditation Accredited as an American National Standards Institute (ANSI) developer, VITA provides its members with the ability to develop and promote open technology standards.

Status: The standard is open for revisions. The working group is reviewing updates for compliance requirements and requirements for 12 V power.

ANSI/VITA 46.11: VPX System Management The following standards has recently been ANSI and VITA ratified via public ballot:

Objective: The VITA 46.11 standard defines a systemmanagement architecture for VPX systems.

› ANSI/VITA 46.30-2020: VPX Higher Data Rate Standard › ANSI/VITA 67.2-2020: VPX Coaxial Interconnect, 8-Position SMPM Configuration

Status: The standard is due for its five-year review. Improvements based on feedback from the community are under consideration.

The following standard has recently been VITA-ratified as a VITA Draft Standard for Trial Use:

VITA 51.4: Reliability Component Derating Objective: The goal of this working group is to develop a new component-derating standard.

› VITA 46.31 VPX: Higher Data Rate, Solder Tail Status: This working group has joined forces with the IEEE to jointly develop this standard under IEEE-2818. A draft document has been developed.

These standards are available for download by VITA members and is posted at the VITA Store for purchase by nonmembers.

VSO study and working group activities Standards within VITA may be initiated through the formation of a study group and developed by a working group. A study group requires the sponsorship of one VITA member, while a working group requires sponsorship of at least three VITA members.

Several working groups have current projects underway. Here’s a roundup of these projects:

ANSI/VITA 42.0: XMC: Switched Mezzanine Card Objective: The VITA 42.0 XMC standard defines a popular mezzanine-card architecture using a PCIe interconnect to host carrier modules.

Status: The standard is due for its five-year review. The working group is reviewing revisions to bring the standard in line with current practice in related standards.

ANSI/VITA 46: VPX Baseline Objective: The VITA 46.0 base standard defines physical features that enable high-speed communication in a compliant system.

8 | VITA Technologies Application Guide Winter 2020

ANSI/VITA 61: XMC 2.0 Objective: The VITA 61 XMC 2.0 standard, based upon VITA 42.0 XMC, defines an open standard for supporting highspeed, switched-interconnect protocols on an existing, widely deployed form factor, but utilizing an alternate, ruggedized, high-speed mezzanine interconnector.

Status: The standard is due for its five-year review. Revisions to match VITA 42 changes are in review.

ANSI/VITA 65: OpenVPX Architectural Framework for VPX Objective: The OpenVPX architectural framework standard is a living document that is regularly updated with new profile information and corrections.

Status: New profiles based on work with the Sensor Open Systems Architecture (SOSA) are being developed.

VITA 66.5: Optical Interconnect on VPX – Hybrid Variant Objective: This document describes an open standard for configuration and interconnect within the structure of VITA 66.0 enabling an interface compatible with VITA 46 containing www.vita-technologies.com

blind-mate optical connectors with fixed contacts on the plugin module and floating displacement on the backplane.

Status: The working group has developed a draft document of the standard that is currently in working-group ballot.

Status: The working group is developing the draft document.

VITA 87: MT Circular Connectors

ANSI/VITA 67.3: VPX: Coaxial Interconnect on VPX, Spring-Loaded Contact on Backplane Objective: The VITA 67.3 standard defines an open standard for configuration and interconnect within the structure of VITA 67.0, enabling an interface compatible with VITA 46 containing multiposition blind-mate analog connectors with SMPM-style contacts having fixed contacts on the plug-in module and spring action on the backplane.

Status: The standard is open for revision. The document has completed public ANSI/VITA review and is in the commentresolution phase.

VITA 68.2: VPX: Compliance Channel Objective: This standard defines a VPX compliance channel, including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates. This standard allows backplane developers to design a backplane that supports required bit-error rates (BER) for multiple fabric types. This also allows module developers to design plug-in modules that are interoperable with other modules when used with a compliant backplane.

Objective: The VITA 87 MT circular-connector standard defines a standard for circular connectors with optical MT. Circularconnector shells are compliant to MIL-STD-38999. MT offer options for 12 or 24 fibers per MT and for physical contact or lensed MT. Status: The working group is developing a draft document.

VITA 88: XMC+ Objective: The VITA 88 XMC+ standard defines an improved electrical/mechanical mezzanine connector for XMC applications. Mechanically, the proposed connector is compatible with VITA 42/61 footprints, achieving backward compatibility while offering improved mating/unmating forces. Electrically, speeds up to PCIe Gen 5 (32 Gbps) and maximum SI performance are supported.

Status: The working group is developing a draft document.

Copies of all standards reaching ANSI recognition are available from the VITA online store (www.vita.com/Purchase).

For a more complete list of VITA standards and their status, go to www.vita.com/Standards.

Status: The document is in public ANSI/VITA review and ballot.

VITA 74.4: SpaceVNX Objective: The VITA 74.4 standard defines a mechanical format for standardization of switched serial interconnects for smallform-factor applications.

Status: The study group is gathering inputs for development of a potential standard for space platforms.

ANSI/VITA 78: SpaceVPX Systems Objective: VITA 78 is an open standard for creating high-performance, fault-tolerant interoperable backplanes and modules to assemble electronic systems for spacecraft and other highreliability (availability) applications. Such systems will support a wide variety of use cases across the aerospace community, including some non-spacecraft systems. This standard leverages the VPX standards family and the commercial infrastructure that supports these standards in non-space applications.

Status: The standards are open for revisions. The documents have completed public ANSI/VITA review and are in the comment-resolution phase.

VITA 78.1: SpaceVPX Lite Systems Objective: This standard leverages the work done on ANSI/ VITA 78 to create a standard with an emphasis on 3U module implementations. The most significant change from SpaceVPX is to shift the distribution of utility signals from the utility-management module to the system-controller module to allow a radial distribution of supply power to up to eight payload modules. www.vita-technologies.com

SOSA and VITA: Enabling Open Standards for Improved Capability Sponsored by Annapolis Micro, Epiq Solutions, Pentek, and TE Connectivity Elements of the Sensor Open System Architecture (SOSA) technical standard are leveraging standards developed by the VITA Standards Organization, specifically VITA 65, also known as OpenVPX. VITA has also become a participating member of the SOSA Consortium along with the Air Force, Army, and Navy.

Join a panel of industry experts for this webcast, which will cover how the SOSA Consortium is working with VITA to enable standardization of VITA-based standards within the SOSA Technical Standard.

To watch the webcast: https://bit.ly/32HedJr

WATCH MORE WEBCASTS:

https://militaryembedded.com/webcasts/

VITA Technologies Application Guide Winter 2020 |

9

TECHNOLOGY FEATURE

Enclosures

VPX and OpenVPX: Design aspects of enclosure technology

By Alexander Jäger

The VPX standard (VITA 46) is an advanced development of the VME standard, which was introduced in 1981. Similar to VME, VPX defines the electrical and mechanical specifications for assemblies and systems; in addition, the mechanics are based on the 19-inch standards IEC 1101-1 and IEEE 1101-10. These standards specify boards and backplanes in the Eurocard format 3U as well as in 6U and a depth of 160 mm each (assemblies 6U by 160 mm – 233.35 mm by 160 mm or 9.187 inch by 6.299 inch or 3U by 160 mm – 100 by 160 mm or 3.937 inch by 6.299 inch).

The development of the standards VPX fills the need for modular serial structure with robust performance and also specifies interfaces between plugin modules and chassis for products intended for use in harsh environments.

VPX combines the latest connector and packaging technology with innovative bus and serial fabric technology, resulting in lower pin count, reduced power requirements, and smaller chip/ board space. For its part, VITA 48 specifies the mechanical or cooling interface between plug-in and housing, while VITA 65 defines the electrical interface between plug-in module and backplane and addresses the various requirements of the industry.

To ensure backward compatibility with existing hardware, the VPX specification includes regulations for 6U hybrid backplanes for VME64, VXS, and VPX boards. It supports a range of switched fabrics such as PCI Express, Serial RapidIO, and 10 Gbit Ethernet that can be configured in a variety of backplane topologies. VPX provides a powerful upgrade to switched-fabric technology for the processing of large amounts of data for users already deploying VME. Another advantage of VPX is its high overall I/O capacity: VPX offers 160 high-speed differential pairs, each nominally rated for a maximum performance of 10.3 Gbaud. Because of the high-speed signals, board and system designers must consider integrity analysis throughout the entire design phase of VPX products.

Complementary mechanical standards have been developed to further extend the benefits of VPX for rugged integrated systems. For example, the VITA 48 VPX Ruggedized Enhanced Design Implementation (REDI) standards specify alternative mechanical formats for extended functionality beyond the traditional IEEE 1101.1 and 1101.10 formats. This standard improves the cooling of embedded systems, including conductive cooling (fanless cooling via heat conduction) through larger and more efficient thermal interfaces and other cooling methods such as air and liquid cooling. Depending on the

10 | VITA Technologies Application Guide Winter 2020

www.vita-technologies.com

HEITEC ELECTRONICS

www.heitec-electronics.com

TECHNOLOGY FEATURE

Voltage Level

3U watts/slot

6U watts/slot

Per wafer due to connector limits

Only 3V

69

N/A

23 Amps †

Only 5V

115

115

23 Amps †

Only 12V

276

384

23 Amps † (3U), 16 Amps ‡ (6U)

VS1, VS2 and VS3

240

348

12 Amps §

Only 48V per VITA 46

N/A

768

16 Amps ‡ (VS1 and VS2)

Note: † = 1 power wafer used, ‡ = 2 power wafers used, § = 3 power wafers used

TABLE 1

FIGURE 1

Rugged half-ATR enclosure. HEITEC image.

cooling method, the insertion height can vary. Because VPX enables a wide range of options, it’s important to get the exact specifications. That’s where the challenge comes in, as all the options have resulted in a wide variety of implementations.

(Figure 1.)

System approach The VPX specification focuses primarily on the board level, but the wide variety of heterogeneous solutions has made it increasingly necessary to consider the system level in order to ensure interoperability; simplify adaptations; and reduce testing, cost, and risk. As a result of these efforts, OpenVPX (VITA 65) is the standard that defines VPX interoperability for integrated system environments with multiple modules as well as module and backplane designs including slot definition, while maintaining compatibility with VPX. The OpenVPX framework defines clear interoperability points required for module-to-module, module-to-backplane, and chassis integration; the backplane configuration tells the user which slot profiles are used, including information about data rate, routing topology, and implemented fabrics. Prior to the release of OpenVPX, an almost unlimited number of implementations with arbitrary slot assignments were in the market.

Although they were implemented according to VITA 46, each system was so individual that board and backplanes could rarely be reused in other systems, even if they came from the same vendor. www.vita-technologies.com

VPX performance overview. Courtesy HEITEC.

OpenVPX has made it possible to develop open architectures and powerful embedded-hardware solutions as well as middleware layers. A number of recommendations exist to support the evaluation, prototyping, and development of VPX systems. By using the OpenVPX standard and architectural “toolbox” in combination with the existing connectivity, system developers can derive content and rules of the standard for their applications instead of starting from scratch. By limiting configurations, these profiles increase seamless interaction and reusability.

However, different types of applications typically require different system architectures with different backplane connectivity. OpenVPX supports central switching, distributed switching and master/slave topologies. Central switching uses dedicated switches in multiple topologies (e.g., Dual Star), whereas distributed switching includes full or partial network switching. The master-slave topology generally consists of a master host single-board computer (SBC) with attached slave PCIe fabric I/O cards (e.g., an SBC complex connected to I/O cards via PCIe).

OpenVPX offers a total of fifteen ANSI/VITA 65 6U backplane profiles, fourteen 6U module profiles, thirteen 3U backplane profiles and 22 3U module profiles to choose from. In addition, OpenVPX currently offers a range of recommended profiles for the selection of development enclosures, covering basic issues such as slot count, module type, module size, cooling, and power supply. (Table 1.)

Requirement profile and decision criteria After defining the requirement profile for an application, a few decisions have to be made. First can be: Should 3U or 6U formats be used? If different modules – possibly from different manufacturers – are used, reliable system management may be required, which has some impact on the enclosure design. Factors that must be defined include slot and module payload profiles, as well as switch module profiles for the values to be achieved for data processing, throughput, and management. Pinouts, placements, and protocols should be precisely defined for the system design to eliminate errors from the start. Other questions that need asking: Are optical connectors in use or is an RF connector interface needed? Which baud rates are required by the application?

What are the requirements for maintainability? Key decisions include cooling method, performance profile, backplane profile, protocols, and enclosure type.

Keeping cool An important factor in the choice of chassis is the cooling system. The power dissipation of VPX-based modules is often much higher than that of conventional VME or CompactPCI-based modules. Depending on the supply voltage, the power dissipation is usually around 100 watts, compared to most VME or CompactPCI modules, which run about 40 watts. There had been no standardization of power supply or cooling until the ANSI/VITA 65 OpenVPX standard came about; for the first time, VITA Technologies Application Guide Winter 2020 |

11

Enclosures

TECHNOLOGY FEATURE

specific criteria for power supply and the cooling of enclosures were defined, at a level usually two to four times the cooling capacity that typical VME or CompactPCI development chassis can handle for harsh environments. The ANSI/VITA 48.1 to 48.8 standards cover the different cooling methods such as air, liquid, or conduction cooling; also described is the wattage per plug-in module, components, and connectors.

Only a very small number of existing enclosures are capable of providing the required high cooling level of 18 CFM [cubic feet per minute] per slot, covering the vast majority of modules. It is up to the system developer to define the effort. For example, Intel Atombased SBC modules typically dissipate 15 watts, while DSP-oriented multiprocessor and FPGA [field-programmable gate array] modules often range from 100 to 150 watts. The cooling concept also plays an important role when configuring a module, for example, when adapting the plug-in modules to I/O requirements using mezzanine cards, which can be in conflict with the selected heat dissipation or airflow. Things to look at: The impact of rear-transition modules and their cabling requirements on the cooling scheme, whether cooling is possible on the rear panel at all, or whether the power has to be kept low there to avoid hot spots. Conduction-cooling enclosures dissipate the heat generated into the environment via cooling fins without a fan. If necessary, housings with liquid-cooled side panels must be used.

Another factor: The influence of each respective measure on maintainability.

Choosing the right concept from the beginning can save considerable money.

Power-supply options Another important criterion for the choice of housing is the performance profile.

VPX enables the use of different power supplies, which reduces interoperability.

OpenVPX recommends 5-volt and 12-volt power supplies, which should handle most applications. The choice of one or the other depends on the power consumption of the payload modules to be installed. Applications with a mix of 5-volt and 12-volt payload power

profiles may require a modified power-supply configuration. The appropriate power profile is derived by taking the sum of the requirements of the selected payload modules. OpenVPX specifies up to 276 watts per slot in 3U and 768 watts per slot in 6U.

Selecting a backplane profile The selection of a suitable backplane profile is also on the checklist. To wit: The backplane topology must support the application requirements and offer compatibility with the selected payload module profiles. Backplane profiles minimize size and cost and are designed for specific application types, such as master-slave control applications. They maximize data throughput in high-performance multiprocessing applications, efficiency for small numbers of slots in daisy chain and mesh topologies, and higher performance for large numbers of slots in central-switch topologies. More than one module profile may be compatible with a specific slot in a particular backplane profile. VITA 65 lists a single slot profile, but there are several other module profiles that are compatible.

Compatibility depends on the pins and signals connected in each respective backplane profile. All signals connected on the backplane must match defined signals that are the same type on the modules. They may have additional defined signals that are not connected on the backplane, but this is irrelevant for the compatibility of the module and the slot. For example, control-level and/or extension-level signals may be defined in the module profile that have no equivalent in the backplane profile.

The module can be used in this slot, as long as the application has not connected these additional signals in the backplane. Fabric protocols and baud rates for modules at both ends of backplane profile connections must also match. To simplify this, all compatible module profiles for available OpenVPX standard backplanes have been identified. The standards thus cover the basics such as slot count, module type, module size, cooling, and power supply. HEITEC supports OpenVPX-compliant development chassis and backplanes, suitable for the vast majority of OpenVPX module profiles.

Front-panel decisions Ideally, the goal is facilitating general interchangeability between different versions and between manufacturers of similar systems. The Eurocard standard – according to IEC60297-3 or IEEE1101 – had the objective of standardizing the front-panel geometry and modularity of the plug-in units and defines the required dimensions and tolerances to ensure mechanical functional compatibility. This standard is based on the first card position, 3.27 mm from the left reference line of the opening; following card positions are based multiples of 5.08 mm (1HP) seen from the first card position. To allow for a uniform working distance between front panels, the total width of a front panel is usually 0.4 mm less than the nominal HP by 5.08 mm.

IEEE1101-1 and -11 extend the specifications and describe typical features for VME64x, CompactPCI, and PXI. Heights are nominally specified in U (multiples of 44.45 mm). A 2.5-mm-wide rim is provided at the top and bottom for mounting card guides and guide rails. Front panels and board sizes should be adapted if Eurocards with card holder are attached to the front panel. Strong tensile forces due to high pin counts require special handles and horizontal rails, while demanding applications also require electrostatic protection, which must be included in the mounting as well.

In the case of VPX, the VITA 48 standards specify the mechanical standard for 3U and 6U modules with air, conduction, or liquid cooling methods. The distance between the modules has been increased to 1 inch, compared to the 0.8 inch of the IEEE1101 standard. However, it is vital to consider that according to the definition in the VPX standards, there is an offset of the device to the front panel, which makes a mixed assembly of 4HP and 5HP VPX boards in one system difficult. Guide rails and moldings must be optimally adapted in this case.

12 | VITA Technologies Application Guide Winter 2020

www.vita-technologies.com

Alexander Jäger is portfolio solution manager for the electronics business area at HEITEC AG in Eckental, Germany. He joined HEITEC to strengthen the company’s product management team in 2019. His professional career includes the position of Product Solution Manager for fail-safe 19-inch systems for rail/transportation and industrial solutions at MEN Mikro Elektronik. In addition, as a hardware engineer, he was involved in the development of 40 Gb/sec DWDM transponders at Cisco Systems and Core Optics. He attended the Rudolf Diesel School and the Georg Simon Ohm University in Nuremberg and holds a degree as a state-certified electrical engineer.

FIGURE 2

Mounted EMC spring with preparation for a restored card head for variable integration. Heitec image.

Maintenance aspects Critical applications often require a twostage maintenance scheme, so appropriate precautions must be taken during system design; that is, plug-in modules can be replaced in the field. The two levels refer to the organizational level – the area of application – as well as the depot level. Exchangeable plug-in modules must be repairable or exchangeable with a minimum of tools. EMC protection must be conceived to prevent damage during the handling (Figure 2). The time of intervention must be as short as possible, and the probability of errors must be minimized from the outset, e.g., by coding or the use of slot keying (exclusive slot assignment). Front panel connections may complicate maintenance, so the alternative of rear connections must be considered. Modules with several accessories may complicate the interchangeability of boards, so placement options must be carefully considered right from the start.

For most complex applications that VPX is designed to handle, a holistic approach makes sense to prevent unwanted incompatibilities and minimize costs and risks. The interoperability enables scalable, robust and flexible solutions, performance migration when needed, as well as technology upgrades with lower obsolescence barriers. Especially for demanding applications in regulated markets, an individual concept is often the best solution. The system-level approach uses all advantages of the standard. HEITEC’s portfolio offers not only immediate access to the technology and immediate availability, but also all system design options including evaluation and service. www.vita-technologies.com

Sources www.vita.com OpenVPX – Tutorial and Common Practices (Greg Rocco, MIT Lincoln Laboratory, 22nd January 2019.)

Award-Winning and Innovative OpenVPX Solutions

Get ready for next-gen sensor platforms with chassis, boards and system management solutions aligned to the new SOSA™ standard.

With you at every stage!

Elma Electronic Inc.

elma.com

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TECHNOLOGY FEATURE

Packaging with optics

Advancing electronic packaging with optics gives VPX a 450% bandwidth boost

By Mark Benton and Jim Mosier

Implementing optics for Level Four electronic subassembly packaging in VPX systems enables significantly higher bandwidth over purely copper interconnects.

The signal-processing requirements of today’s active electronically scanned antenna (AESA) radar, infrared search and track (IRST), and surveillance systems are demanding. This situation challenges designers to squeeze more processing power and electronics into VPX (ANSI/ VITA 46) and OpenVPX (ANSI/VITA 65) systems. One answer is to use a new generation of 3U-form factor VPX cards that offer significantly more bandwidth thanks to several new optical interconnects that conform to the forthcoming VITA 66.5 standard. These interconnects – integrating high-density MT ferrule interfaces and 24-lane optical transceivers – in Level Four electronic packaging will enable up to 900 Gb/sec duplex data throughput within a half-size connector module. That

rate nearly quadruples the linear bandwidth capability compared to backplanes using the latest copper-based VITA 46.30-compliant interconnects.

Bringing Level Four electronic packaging for VPX up to light speed While VITA standards continue to improve copper alloy-based interconnects used in electronic packaging for VPX systems, evolving VITA 66 “dot” standards are doing the same for optical interconnects. Advanced optical connectors give VPX backplanes and modules the benefits of higher bandwidth and other inherent advantages of optical technology, which include: › Low signal loss: Propagating light signals through optical fiber requires far less amplification than moving electrons through copper. As a result, attenuation (loss of power) is significantly less likely. › Less electromagnetic interference (EMI) and crosstalk: Nonmetallic fiber-optic cables are inherently EMI-resistant and require no electromagnetic shielding. Crosstalk is negligible between signals in different fiber-optic cables. › Size and weight reductions: With lighter and more compact components, optical technologies minimize space and mass.

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www.vita-technologies.com

TE CONNECTIVITY

https://www.te.com/usa-en/home.html

TECHNOLOGY FEATURE

› Safety: Fiber-optic bundles are not electrically conductive and are inherently resistant to indirect lightning strike effects. The pure-glass (SiO2) core withstands common wet and corrosive environments without degrading. › Security: Light traveling through glass does not radiate signals, making optical fiber extremely difficult to tap. › Flexibility: Optical fiber’s small diameter, high strength, and various jacketing options provide flexibility and resistance to cracking and breaking. The typical minimum recommended long-term bend radius for conventional fiber optic cable is ten times the outside cable diameter. Optical flex circuits can accommodate smaller bend radii and multiple stacked layers and fiber crossings. › Cost: Reductions in material cost of fiber cable, components, and hardware give fiber optics a price/performance advantage in many applications.

Along with high signal integrity and robustness, fiber optics offer density and bandwidth advantages that are extremely attractive in data-intense VPX applications.

Consider, for example, a 3U VPX module with a VITA 46.30-compliant MULTIGIG RT 3 high-speed backplane connector employing copper-alloy contacts. Each half-size connector uses eight printed circuit board (PCB) wafers that deliver 16 differential pairs.

With each pair capable of supporting duplex bandwidth of 25 Gb/sec, the total duplex bandwidth amounts to 200 Gb/sec.

First compare that to a 3U VPX module employing a forthcoming half-size VITA 66.5 Style E (a.k.a. 66.4 HD derivative) fiber-optic connector for 0.800-inch card-to-card pitch applications. The smaller size allows a higher density in which two 24-fiber MT ferrules enable 24 duplex channels. With each channel capable of providing duplex bandwidth of 25 Gb/sec, the total duplex bandwidth amounts to 600 Gb/sec, a bandwidth increase of 300% percent over the latest copper interconnects.

The forthcoming VITA 66.5 Style D fiber-optic connectors provide additional bandwidth capability for 1.000-inch pitch applications (Figure 1). These connectors accommodate up to three 24-fiber MT ferrules within a half-width connector module, providing up to 36 duplex channels, enabling up to 900 Gbps in the same linear space, a 450 percent increase in bandwidth compared to VITA 46.30-compliant copper interconnects.

This substantial increase in bandwidth is achieved at Levels Three, Four, and Five in the electronic packaging of a VPX system.

By convention, interconnections occur between two levels of the electronic packaging scheme. At Level One, a basic circuit element, such as an integrated-circuit (IC) chip, is permanently and directly connected to its leads, such as the frame of a chip carrier.

At Level Two, the device is connected to a PCB. At Level Three, boards are connected together. Subsystems are connected together at Level Four, while at Level Five, subsystems are connected with a system’s input/output (I/O) interface. Finally, at Level Six, systems are physically connected from box to box across distances ranging from centimeters to kilometers.

Besides the obvious use of optics in board-mount I/O modules at Level Five and fiber-optic networking at Level Six, optics can be employed at other electronicpackaging levels:

FIGURE 1

VITA 66.5 Style D – 3MT half-size connector.

Courtesy TE Connectivity.

www.vita-technologies.com

› At Level One: Applying the optical equivalent of a chip-on-a-chip carrier involves direct connection of a laser diode or a photodetector chip connected to a waveguide. A photonic “flip-chip” technique may be used, or cleaved fibers may be aligned in these interconnects.

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Packaging with optics

TECHNOLOGY FEATURE

› At Level Two: Implementing optics may involve pluggable transceivers – such as single-channel SFP+ or MT-based parallel mid-board transceivers – and can include the subassemblies inside those transceivers. › At Levels Three and Four: Advances in optical interconnects make it possible to combine Level Three board-edge solutions with Level Four subsystems. These advanced optical interconnects between VPX plug-in modules and the backplane significantly expand bandwidth.

This bandwidth boost is the direct result of developments in VITA standards for optical interconnects. In particular, VITA 66.5 addresses Level Three and Four interfaces, while VITA 87 defines interfaces for Level Five.

CONTINUE TO IMPROVE COPPER ALLOY-BASED INTERCONNECTS USED IN ELECTRONIC PACKAGING FOR VPX SYSTEMS, EVOLVING VITA 66 “DOT” STANDARDS

Arrays and parallel transceivers To increase density, board and system-level designs are generally moving away from bulky discrete connectors to array-based solutions using smaller and more densely packaged circular and rectangular connectors. New connector module designs can integrate optical signals in a common block for the backplane interface. The block uses less space in a slot versus conventional side-by-side solutions. This trend is affecting Levels Three, Four, and Five within VPX systems. For high fiber counts in small spaces, optical flex circuits may be used to support tight-bend radii and simplify routing by accommodating up to 12 layers stacked and up to six fiber crossings.

To increase bandwidth, both card-edge and midboard parallel optical transceivers can be used to allow simultaneous transmission and reception of data over multiple fibers.

VITA 66.5-compliant MT optical interfaces also support this application.

ARE DOING THE SAME FOR OPTICAL INTERCONNECTS. style offers different benefits in terms of density, ruggedness, repairability, and other characteristics. The forthcoming VITA 66.5 standard defines the highdensity fiber-optic interconnects for ANSI/VITA 65 OpenVPX architectures.

Blind-mate transceivers on the card edge

VITA 66.5 evolves The ANSI/VITA 66.0 base standard defines a family of blind-mate fiber optic interconnects for ANSI/VITA 46 VPX backplanes and plug-in modules (Table 1.). Each termini Maximum Fibers

Maximum Duplex Lanes

2 MT ferrules – up to 12 fibers per MT ferrule

24

12

VITA 66.2: Optical interconnect on VPX – ARINC 801 Optical Termini

ARINC 801 termini – four discrete termini

4

2

VITA 66.3: Optical interconnect on VPX – Expanded-Beam

Expanded Beam (EB) insert – four modularized fiber termini

4

2

VITA 66.4: Optical interconnect on VPX – Half P MT variant

1 MT ferrule per connector – up to 12 fibers per MT ferrule

12

6

VITA 66.5: Optical Interconnect on VPX – Half P Hybrid variant AND MT variant

Style A: 1 MT ferrule per connector – up to 24 fibers per ferrule

24

12

Style B: 2 MT ferrules per connector – up to 24 fibers per MT ferrule

48

24

Style C: Hybrid – RF contacts with 1 MT – up to 24 fibers per MT ferrule

24

12

Style D: Half P, 3MT – up to 24 fibers per MT ferrule

72

36

Style E: Half P, 2MT – up to 24 fibers per MT ferrule

48

24

Connector Standard

Connector Style

VITA 66.1: Optical interconnect on VPX – Full P MT variant

TABLE 1

WHILE VITA STANDARDS

Family of VITA 66 standards. Courtesy TE Connectivity.

16 | VITA Technologies Application Guide Winter 2020

An active blind-mate optical interconnect design offers several benefits. A floating insert within the backplane connector module provides prealignment before the MT ferrules start to engage (Figure 2).

Additionally, the interaction of the cardlevel guide pins and guide modules provides error-free mating and prevents damage to the connectors. Moreover, the system can be assembled only one way to avoid miswiring and mishandling.

The low-profile VITA 66.5 Style A plug-in module connector and transceiver are integrated. The module is screwed onto the board edge along with an interposer; this assembly style is designed to be removable to enable future upgrades.

The design also eliminates the need to locate transceivers midboard, which saves board space and eliminates fiber cable routing on board.

Features of the backplane optical connector module include a floating insert and pins or a blade that align in X and Y directions with the MT ferrule mating interface, a design that complies with VITA 66.5 mating requirements. Features of the plug-in module connector include the optical transceiver with its MT www.vita-technologies.com

circular connector shells compliant to MIL-STD-38999 (Figure 3).

Options for 12 or 24 fibers per MT and for physical contact or lensed MT will be available.

FIGURE 2

Ruggedized blind-mate MT optical modular/backplane interconnects that meet VITA 66.1 and 66.4 open architecture specifications for VPX systems.

Blind-mate transceiver shown in large detail. (Courtesy TE Connectivity.)

ferrule, an LGA interposer, and the front connector housing with its corresponding alignment feature(s).

The soon-to-be-released VITA 66.5 standard defines two different blind-mate optical connector interface configurations. Connectors incorporating edge-mounted transceivers contain fixed MT ferrule interfaces on the plug-in module and spring-supported (floating-displacement) MT ferrules on the backplane. Connectors containing cable-to-cable variants incorporate spring-supported MT ferrules within both the backplane and plug-in module connector halves.

What’s new is the increase in density possible with VITA 66.5 Style D and Style E connector variants. This standard defines both half-width and full-width connector modules for dual MT ferrules. The dual-MT ferrule combination can provide up to 48 (2 × 24) lanes, while Style D supports up to 72 (3 × 24) lanes.

This MT development not only boosts bandwidth, but the forthcoming VITA 66.5 standard also makes other critical contributions by supporting: › Multifiber termination (MT) ferrules: The MT interconnect for MT ferrules was described in the first “dot” specification published (VITA 66.1). Of all industrystandard ferrules, the MT provides the highest-density interconnections for both multimode and single-mode fibers. It serves as the foundational ferrule type for VITA 66.5. Over time, MT modules for multifiber terminal ferrule connectors at the VPX backplane interface have doubled or tripled in the same physical space on the boards. Fiber counts per MT module are increasing from 12 to 24 to 48 to 72. MT is a physical-contact-style terminus, meaning the glass end faces are in direct contact for very low loss. VITA 66.5-compliant designs use a springloaded MT backplane connector to provide mating force between the backplane and the plug-in module. The spring-loaded interface ensures secure MT-to-MT mating to minimize return loss and the effects of vibration. › Hybrid RF/optical modules: The forthcoming VITA 66.5 standard encompasses more than optics: The standard also aims to achieve further density with hybrid RF/optical modules by combining the RF and optical links within the same connector module. The floating insert can house both an array of RF contacts andMT ferrules, adapting up to 10 NanoRF contacts and an MT within a 3U half-module space. › Higher-density VPX enclosure optical I/O connectivity: The VITA 87 standard for optical MT circular connectors is also under development. This standard will define www.vita-technologies.com

FIGURE 3

D38999 Series III Style circular connectors with up to four MT ferrules accommodating up to 96 optical channels.

(Courtesy TE Connectivity.)

Entering the future: VITA and SOSA working together The development of the VITA 66.5 and VITA 87 standards has been leveraged in another influential standards organization – the Sensor Open Systems Architecture (SOSA) Consortium. Comprised of U.S. military, government, and related industry representatives, the SOSA Consortium aims to develop interoperability standards for next-gen sensor systems. SOSA-aligned architectures are being developed for signal intelligence (SIGINT), electronic warfare (EW), radar, and communications applications. SOSA is adopting ANSI/VITA 65 OpenVPX architecture within the boxes and collaborating with VITA to leverage existing standards while also driving new VITA standards.

Evolving VITA standards have driven the development of valuable optical and RF technologies for VPX systems. As a result, tomorrow’s VPX systems can keep pace with demanding signal-processing requirements by adding more fast lanes to boost bandwidth.

Mark Benton is Engineering and Products Manager at TE Connectivity; Jim Mosier is R&D/ Product Development Engineer at TE Connectivity.

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TECHNOLOGY FEATURE

FPGAs

Can you really simulate an FPGA device?

By Max Taylor-Smith

FPGAs – field-programmable gate arrays – are an incredibly diverse method of extracting multifunctionality from a single piece of silicon. The usefulness of these devices is encouraging a renaissance of their use in military-focused embedded systems as developers scramble to be at the front of the queue for new interoperability contracts in FACE [Future Airborne Capability Environment] and SOSA [Sensor Open System Architecture] systems. Higher-power FPGA [field-programmable gate array] versions, coupled with continuing reduction in transistor size, ensures there is higher criticality to meet the environmental demands set out in VITA 47, but the approach to thermal solutions has remained relatively stagnant for the last 10 years. The newer generation of size, weight, power, and cost (SWaP-C)-optimized systems simply will not allow for thermal margin built in to deal with inaccuracy.

FPGA [field-programmable gate array] structures vary depending on the vendor, but fundamentally they follow the same structure. Basic functional logic elements are connected through programmable interconnections between fixed wires. Figure 1 shows the functional units as gray boxes, I/O elements as white boxes, and wires and programmable interconnects as black lines. The strategic connection of these functional units can replicate larger-scale logic units, such as processors or memory, in an interconnected network on the chip.

In an FPGA most of the delay in the chip comes from the interconnect. Connecting one functional unit to another functional

unit in a different part of the chip often requires a connection through many transistors and switch matrices, each of which introduces extra delay (Zeidman, 2006).

Figure 2 shows in more detail the level of switching required to determine connectivity between functional blocks.

The sheer programmability of FPGAs implies that more transistors are needed to implement a given logic circuit in comparison with custom ASIC [application-specific integrated circuit] technologies. This leads to a higher power consumption per gate and increased power demand per device (Anderson & Najm, 2004).

FPGA shapes and logic The configurability of an FPGA is delivered using large amounts of logic collated into fundamental building blocks called CLBs [configurable logic blocks], formed of smaller components: flip-flops and look-up tables. The allocation and control of signals between these blocks drives the functionality of the FPGA and so position and density of active logic is entirely user-dependent. This situation presents a real challenge to accurate thermal simulation of a device, and using a typical junction to case resistance can give wildly inaccurate results as operability is adjusted to each device.

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www.vita-technologies.com

ENTROPY ELECTRO-MECHANICAL SOLUTIONS https://engineeringentropy.co.uk/

TECHNOLOGY FEATURE

Designing an FPGA architecture from scratch using only these CLBs is extremely labor-intensive due to the high level of functional detail needed for modern computing. When developing logic using CLBs only, the resultant logic is referred to as “soft blocks,” so named because of their high configurability.

“Hard blocks,” by contrast, are embedded functionality on an FPGA that can only be used for a predetermined purpose.

Examples of these could be processors, memory blocks, or high-speed transceivers. These are beneficial in that they have optimized routing and increased logic density enabling reduced timing restrictions, while consequentially reducing the configurability of the chip (Weber & Chin, 2006) and significantly increasing the heat flux density in these dedicated areas (Sundararajan, et al., 2006).

FIGURE 1

FPGA structure (Santangelo, 2014)

FIGURE 2

FPGA interconnecting switch method (Zeidman, 2006)

Logical distribution When a circuit is implemented, the place-and-route tools place critical logic close together and spread other logic as far as allowed by the circuit constraints (Velusamy, et al., 2005). Logic distribution is typically dependent on, and local to, pinout placement because timing restrictions on certain I/O require minimized interconnection length between pin and active logic. This mirroring is not a perfect prediction, however, as not all logic requires these strict timing restrictions, the die size is typically much smaller than the solder balls, communication with other control logic may need more optimal placement, and physical logic must be available and so can divert routing.

Software such as Intel’s Quarts Prime or Xilinx’s Vivado Design Suite will handle the majority of this floorplanning and can also offer the user the opportunity to prioritize switching performance, thermal performance, or a balance between the two. Unfortunately from a thermal perspective, however, choosing this focus may significantly affect the latency of an FPGA where some high-density logic is critical to functionality of the device, and this option is rarely available. www.vita-technologies.com

Chips heat up in any transistor-based switching device, some power will be lost as heat due to inefficiencies in the device or due to the nonzero resistances to current in a gate (Engineering Entropy, 2020). This situation is ubiquitous for all semiconductor architecture and creates a requirement for suitable chip- and system-level cooling.

Accurate thermal management of these devices is critical to maintaining the desired operating lifetime of electronic devices, which is exponentially shortened by increasing temperature (V. Lakshminarayanan & N. Sriraam, 2014). Overengineering a thermal solution, ironically, can have a negative impact on a product by increasing undesirable factors such as mass and cost.

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FPGAs

TECHNOLOGY FEATURE

Thermal power dissipation in FPGA CMOS transistor devices can primarily be divided into dynamic and leakage – also known as static – power dissipation. Dynamic losses arise from capacitive charging and discharging of the transistors plus short-circuit power, typically providing the majority of thermal dissipation in an FPGA device. In legacy FPGAs, dynamic power contributed up to 67% of power usage, with static power providing just 22%. In more recent 28 nm devices, static power has increased its dissipation contribution to closer to 40% of the total thermal loss (Intel FPGA, 2018).

The lack of knowledge of how exactly leakage power is distributed across the chip leads to highly inaccurate power traces, and therefore unreliable thermal estimation (Amouri, et al., 2013).

The dynamic power varies greatly with design and is characterized in detail through vendor power-estimation tools (Intel’s Powerplay Quartus or Xilinx’s XPower, for example). It is a function of the known logic quantity, switching frequency and toggle rate.

P_dynamic=[1/2 〖CV〗^2+Q_ShortCircuit V]f∙activity

( 1)

Where C is the capacitance of the transistor, V is the power rail voltage, QShortCircuit is the power consumed during a change in the CMOS logic gate, f is the net frequency, and activity, or toggle rate, is the average number of signal transitions relative to a clock rate (%).

Leakage power is as a result of the noninfinite resistance across an inactive gate threshold, and is heavily dependent on the device temperature (Kushwaha, et al., 2018). The following equation describes the exponential relationship between leakage power, Pleak, and temperature, T. P_leak=P_0×e^((-k)⁄T)

( 2)

Where P0 and k are process dependent constants (Amouri, et al., 2013).

Unlike in an ASIC, logic that is not utilized in an FPGA remains on the device and so remains powered even though not in use, creating a large power demand for a device even with a low logic load. Static power generally does not vary significantly with logic utilization, but is more greatly dependent on the amount of logic on the die (Intel FPGA, 2018) (Tuan & Lai, 2003). The impetus is therefore on the design engineer to select the smallest device for the given application.

While the design engineer should take steps to ensure that the FPGA has been sized correctly for the functionality desired, it is almost impossible to achieve full utilization in a device due the limited supply of programmable routing resources. Generally speaking, a highly utilized FPGA architecture holds around 75% utilization, which is not an unreasonable estimate given the 62% utilization reported (Gayasen, et al., 2004). This report is slightly dated and it is expected that FPGA technology has developed since then. For an extreme example, Xilinx claims the Ultrascale can accommodate utilization of up to 90% (Xilinx Inc., 2015) although this will be entirely dependent on the desired functionality.

Circuit gating is an additional option commonly used to reduce power (Lach, et al., 2004), whereby blocks of unused logic are “turned off” from the voltage rail until needed and so have no static power draw. This technique has been shown to be used

by Xilinx (Xilinx Inc., 2015) and Intel (Intel Corp., 2020) on recent devices.

A significant contributing factor to both the dynamic and static power dissipation in an FPGA is the joule heating of the interconnects. Research completed by Shang et al.

(Shang, et al., 2002) shows as much as 50% to 70% of the total power dissipated in a

20 | VITA Technologies Application Guide Winter 2020

Xilinx Virtex-II was from the interconnection network, shown in Figure 3. While the allocation of this loss to the static or dynamic power contribution is not fully determined, it is expected that with the programmable nature of the interconnect switching the majority of this power is concentrated around active logic.

This high dissipation factor is a result of significantly longer interconnect lengths in FPGAs than ASICs due to the larger area consumed by the logic (Anderson & Najm, 2004). Observing the joule heating and electrical resistivity equations we can identify this relationship: P=I^2 R

( 3)

R=ρL/A

( 4)

where P is power consumed, I is electrical current, R is the wire resistance, ρ is the resistivity of the material, L is the length of the wire and A is the crosssectional area.

Equations (3) and (4) can then be combined to give a linear relationship between the length of and the power dissipated in the interconnect.

P=I^2

ρL/A

( 5)

Finally, the most power-hungry input on an FPGA will usually be the power rail, often denoted as Vcc. This is understandable because the core power rail drives the logic, the use of which is central to any FPGA design (Intel Corp., 2017).

How should I simulate it?

In good rugged system design, the resistance of the heat sink will be dependent on the cooling requirements of the system, including adjacent thermally critical devices, and be both cost- and massefficient. Using a predetermined thermal resistance will not allow for optimization of the thermal solution.

In high-ruggedization environments, such as those set out by VITA-47 ECC4, the rack temperature must be set at +85 °C, meaning the junction temperature must be higher than this. www.vita-technologies.com

The typical approach to junction temperature distribution Considering the unequal and varied distribution of logic within each individual FGPA architecture, there is inherent inaccuracy in assuming the temperature – and therefore power – in the die can be considered with a single value, or applied uniformly across the surface of the die (Intel FPGA, 2018). This effect is likely to be mitigated with the onset of increased leakage power significance on small transistor dies and with the wide distribution of interconnect heating, but there will inevitably be some variance.

Both Intel and Xilinx provide Delphi and detailed IC models of their FPGAs; however, these are calibrated using a uniform heat flux on the die only. Intel reports that this method gives an average accuracy of only 10% for the resistance of the device (Altera Corp., 2012).

Thermal-design tools Given the variability of factors described above, an accurate thermal simulation can be truly achieved only with a user-guided approach bespoke to each FPGA architecture. Some research (Amouri, et al., 2013) (Velusamy, et al., 2005) (Huang, et al., 2009) has been completed into how to more accurately predict the temperature variation within the silicon. W. Huang et al. (Huang, et al., 2004) proposed a modeling methodology, HotSpot, which divides the FPGA die into discrete blocks. Each of these blocks is assigned a thermal resistance generated from the geometry of the block and material properties of the silicon die, and an assigned thermal power.

(Figure 4.)

This method has shown tremendous accuracy for temperature distribution, but it does not describe the method of identifying power source and its dependency with temperature.

To extract much more applicable thermal information for embedded design, Amouri et al. (Amouri, et al., 2013) describe a process which uses the Hotspot methodology for estimating temperature variation, but iteratively calculates the impact of leakage power distribution across the die using the following inputs available from FPGA development tools: www.vita-technologies.com

FIGURE 3

The power distribution in a “real” FPGA circuit (Shang, et al., 2002)

FIGURE 4

Showing the discrete method Hotspot employs to derive local die temperatures (Huang, et al., 2013)

› Die dimensions (taken from data sheet) › A floorplan circuit description of the device › A detailed power report This method assumes initially that the junction has a uniform temperature and so leakage power is evenly distributed across the die. It then provides Hotspot with power per block information on the given design, which in turn calculates the temperature distribution, which is in turn discretized and fed into a leakage model based on equation (2).

This method is the most complete found in literature research and if implemented correctly will provide a designer with a highly accurate temperature distribution (average error of 1 °C) across a die (Amouri, et al., 2013). Using the discretized power data, this can be applied to the detailed IC package geometry within a CFD package giving genuine high confidence in thermal simulation results.

What’s a thermal engineer to do?

The 10% inaccuracy derived from uniform heat flux thermal models can be significantly improved upon by considering the physical floorplan of each device. Using available software tools and processes, thermal simulation can be tailored not only to a device level, but to an architecture level with a high degree of accuracy. Thermal engineers should be mindful that while test data has shown these iterative simulation studies can provide an impressive 1 °C of accuracy, there is no validation of power figures at the test stage. These results typically use an off-the-shelf heat sink which is applicable with the given development tools, while more complicated heat sink design should be calibrated against the power estimator results.

Until further validation can be provided and quantified for the true power consumption of an FPGA, a conservative solution should always be evaluated. For a Xilinx device, this may be as significant as simulating a device at 48 W for a given 40 W power consumption.

Product developers are stuck between a rock and a hard place. MIL-STD-810 is not going to relax its temperature stipulations, and so until more creative cooling solutions such as ultra-high conductivity chassis and/or VITA 48.8 (Air Flow Through) become commonplace, the +85 °C cold wall will remain the driving factor for outstanding VITA Technologies Application Guide Winter 2020 |

21

FPGAs

TECHNOLOGY FEATURE

product performance. Conversely, more stable semiconductor compounds look destined for the power-electronics and automotive market, meaning embedded designers are stuck with a thermal runoff just as things become difficult.

References Altera Corporation, 2012. Thermal Management for FPGAs. Altera Corporation.

Amouri, A. et al., 2013. Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits, Karlsruhe: IEEE. Anderson, J. H. & Najm, F. N., 2004. Power Estimation Techniques for FPGAs. IEEE. Engineering Entropy, 2020. Engineering Entropy. https://secureservercdn. net/160.153.138.53/nm2.751.myftpupload. com/wp-content/uploads/2020/02/3.-Whatactually-is-TDP-and-why-is-it-important-3. pdf?time=1589271825 Gayasen, A. et al., 2004. Reducing Leakage Energy in FPGAs Using Region-Constrained Placement, Monterey..

Huang, W. et al., 2004. HotSpot:ACompact Thermal Modeling Methodology for EarlyStage VLSI Design. IEEE. Huang, W. et al., 2009. Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design, Boston: IEEE. Intel Corporation, 2017. Understanding and Meeting FPGA Power Requirements.

Intel Corp.

Intel Corporation, 2020. Intel Stratix 10 Power Management User Guide. Intel Corporation.

Intel FPGA, 2018. Power Analysis. www.youtube.com/watch?v=8y6M-rmz19I Intel FPGA, 2018. Thermal Management in Intel Stratix 10 Devices. https://www.youtube.com/ watch?v=IiX97BwjhyM&t=331s Kushwaha, A., Verma, G. & Kakar, V. K., 2018.

Thermal Analysis and Modelling of Power Consumption for FPGAs, Paris: International Conference of Advances in Computing and Communication Engineering.

Lach, J., Brandon, J. & Skadron, K., 2004.

A General Post-Processing Approach to Leakage Current Reduction in SRAM-based FPGAs. IEEE. Santangelo, L., 2014. Viv2XDL: a bridge between Vivado and XDL based software, Pisa: University of Pisa.

Shang, L., Kaviani, A. & Bathala, K., 2002.

Dynamic Power Consumption in Virtex-II FPGA Family.

Sundararajan, P., Gayasen, A., Vijaykrishnan, N. & Tuan, T., 2006. Thermal Characterization and Optimization in Platform FPGAs. ICCAD. Tuan, T. & Lai, B., 2003. Leakage Power Analysis of a 90 nm PGA. IEEE. V. Lakshminarayanan & N. Sriraam, 2014.

The Effect of Temperature on the Reliability of Electronic Components, Bangalore: IEEE. Velusamy, S. et al., 2005. Monitoring Temperature in FPGA based SoCs, San Jose: IEEE.

www.vita-technologies.com

Weber, J. M. & Chin, M. J., 2006. Using FPGAs with Embedded Processors for Complete Hardware and Software Systems. American Institute of Physics.

Xilinx Inc., 2005. Static Power and the Importance of Realistic Junction Temperature Analysis.

Xilinx Inc. Xilinx Inc., 2015. Proven Power Reduction with Xilinx UltraScale FPGAs. Xilinx Inc. Zeidman, B., 2006. All about FPGAs. https://www.eetimes.com/all-about-fpgas/

Max Taylor-Smith is the engineering director for Entropy Electro-Mechanical Solutions. He has been involved with specialized simulation and management of high-performance electronic devices throughout his career, focusing on embedded systems and hybrid powertrains at Abaco Systems and Mercedes AMG HPP, respectively. Max is an active participant in VITA Standards Working Groups and ADS’s Special Interest Groups. Readers may reach him at max.taylorsmith@engineeringentropy.co.uk.

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23

VITA Technologiess Application Guide

Communications Sponsored Sponsored By: By:

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Hartmann Electronic Open Frame Development Chassis

The The VSFP24 VSFP24 isis the the newest newest product product in in the the line line of of off off the the shelf shelf offerings offerings allowing allowing system system designers designers and and developers developers to to test test their their VPX VPX systems systems with with up up to to 24 24 SFP+ SFP+ ports ports without without expense expense and and delay delay of of developing developing custom custom SFP+ SFP+ carriers carriers and and RTMS. RTMS. In In aa traditional traditional scenario scenario aa custom custom RTM RTM or or Carrier Carrier was was develdeveloped oped providing providing SFP+ SFP+ ports ports for for aa specific specific VPX VPX bus bus wafers. wafers. That That took took time time and and R&D R&D cost cost and and risk. risk.

VSFP+24 VSFP+24 product product connects connects to to the the VPX VPX bus bus using using MERITEC MERITEC cables cables allowing allowing functionality functionality and and performance performance of of the the system system to to be be verified. verified. After After completion, completion,aacustom customSFP+ SFP+RTM RTMor orCarrier Carrier board board can can be be developed. developed.

FEATURES FEATURES •• 24 24 SFP+ SFP+ ports ports capacity capacity •• 12 12 SFP+ SFP+ ports ports version version available available •• VSFP+24B VSFP+24B version version includes includes retimers retimers in in VPX VPX XMT/RCV XMT/RCV lines. lines.

•• Ports Ports connect connect to to EVEN EVEN or or ODD ODD VPX VPX wafers wafers •• Full Full I2C, I2C, SM0-SM1 SM0-SM1 or or SM2-SM3 SM2-SM3 interface interface to to all all SFP+ SFP+ I2C I2C ports ports •• Full Full I2C, I2C, SM0-SM1 SM0-SM1 or or SM2-SM3 SM2-SM3 monitoring monitoring and and control control of of all all SFP+ SFP+ status status and and control control pins pins •• LED LED indicator indicator of of TX-FAULT TX-FAULT and and LOS LOS •• signals signals •• 12", 12", 18" 18" and and 24" 24" Meritec Meritec cables cables are are available. available.

•• External External +12V +12V power power supply supply QSFP+, zSFP+, zSFP+, XFP, XFP, MINI MINI SAS SAS HD HD versions versions available available •• QSFP+,

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24 | VITA Technologies Application Guide Winter 2020

High Quality Open-Frame Chassis for Development and Testing Applications The Hartmann Electronic Open Frame Development Chassis Series is our most diverse system yet. Available for 3U or 6U, with 34HP (300W PS) or 50HP (600W PS) with space for up to 12 slots. A strong frame with an adjustable locking grab handle, along with a light-weight design make our Open Frame Chassis the perfect companion for easy transport from the lab to the testing grounds.

These systems are available with or without a backplane, in air cooled or conduction cooled variants. Backplane options include variants of cPCI, Serial, PXI, VME, VPX and more. Custom configurations available upon request. www.hartmann-electronic.com

Industrial

SMART Embedded Computing MVME250x

The SMART Embedded Computing MVME250x single-board computer (SBC) features the NXP® QorIQ® P2010 or dual-core P2020. This is a perfect migration path for our PowerQUICC processor boards (MVME3100 and MVME4100), as well as our G4 processor boards (MVME5100 and MVME5110).

On-board memory includes up to 2GB DDR3 memory and 512KB NV MRAM, ideal for critical non-volatile data storage, data logs, dynamic program updates, and dynamic security.

The MVME2502 variant has 8GB soldered eMMC solid state memory for additional rugged, non-volatile storage.

Extended temperature and rugged variants, as well as conformal coating are also available. https://www.smartembedded.com/ec/products/category/vmebus

www.vita-technologies.com

Industrial Industrial SMART Embedded Computing

VITA Technologiess Application Guide

Industrial

Sponsored SponsoredBy: By:

MVME810x

The MVME8100 and MVME8105 from SMART Embedded Computing are high performance 6U VME SBCs featuring the NXP QorIQ P5020 processor supporting high speed DDR31333MHz with ECC. They offers expanded IO and memory features with PCIe and SRIO fabric connectivity and multiple USB, Serial and Ethernet ports. Both models offer 512KB FRAM non-volatile memory, and 8GB eMMC NAND Flash.

VME VME Beyond Beyond2025 2025

The MVME8100 includes up to 8GB DDR3 memory while the MVME8105 variant removes the VXS interface, offers up to 4GB DDR3 memory and offers two Gigabit Ethernet ports on the front panel. https://www.smartembedded.com/ec/products/category/vmebus

Radar

Interface Concept ComEth4510e

The ComEth4510e is a new high-speed 6U OpenVPX control and data plane 40 Gigabit Ethernet switch for compute-intensive applications. The control plane and data plane are based on an independent Marvell Prestera DX switching matrix, providing 10/40 GbE interfaces and a high port density (up to 91 ports) together with high-speed switching capability (up to 720Gb/s) that significantly increase networking performances, required in defense and industrial application systems. The ComEth4510e switching is controlled be a separate management processor which runs Interface Concept’s “Switchware” switch management stack providing IPV6 support, RIPng, and OSPF v3. https://www.interfaceconcept.com/products/Ethernet-Switches/ 6U-VPX/365-ComEth4510e-6U-VPX-Dual-Plane-40-Gigabit-Ethernet-Switch

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Dawn VME Products Robust 7U 19" Rack Mount Enclosure for 3U VPX

Dawn’s RME-6430 was designed specifically to meet the stringent power and cooling needs of high slot count VPX systems. Designed for lab or deployed use, the RME-6430 offers a wide variety of features to suit most program needs. Featuring 2-16 VPX slots at 1" pitch backplane with extreme power and cooling.

Boards are flush mounted. Recessed rear TM cage provided for applications requiring rear TM’s. All cable routing is outside of critical cooling paths. Hinged rear door provides for multifunction mounting of rear fans, auxiliary power supplies and provides I/O space. Installed RuSH™ system health monitoring technology. Rugged, Reliable and Ready. www.dawnvme.com

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SMART Embedded Computing builds on the acquired heritage SMART Embedded Computing buildsComputer on the acquired of industry leaders such as Motorola Group heritage (MCG) of industry leaders such as Motorola Computer Groupcom(MCG) and Force Computers.

As part of the group of innovative panies thatComputers. invented VME technology, we have been supplyand Force As part of the group of innovative coming VME products for more than 40 years. panies that invented VME technology, we have been supplying VME products more than years.

Our portfolio is nowforarguably the 40 widest range of VME SBCs based on NXPis(Freescale) processors usingrange the Power ArchiOur portfolio now arguably the widest of VME SBCs tecture. based on NXP (Freescale) processors using the Power Archi-

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The SBCs featured here are offered in commercial and fully rugged variants for extreme environments with extended The SBCs featured here are offered in commercial and fully shock, vibration, temperatures and conduction cooling.

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https://www.smartembedded.com/ec/vme-beyond-2020 VITA Technologies Application Guide Winter 2020 |

25

VITA Technologiess Application Guide

OpenVPX OpenVPX OpenVPX

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Annapolis Micro Systems WILDSTAR™ 3XB9 FPGA Board -Aligned & 100Gb Ethernet capable • Form Factor: 3U OpenVPX • FPGA: Xilinx Virtex UltraScale+™ (XCVU5P / 7P / 9P / 13P) • MPSoC: Xilinx Zynq UltraScale+ (XCZU7EV)

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• Bandwidth: 100GbE per Backplane Port • I/O: WILD FMC+ next-generation I/O Site • Backplane I/O: VITA 66/67 Optical and RF support • Cooling Options: Air or Conduction or Air-Flow-Through • Temps: -55˚ to +85˚C Operating & -65˚ to +105˚C Storage • BSP: VHDL or CoreFire Next Application Design Suite • Security: Multiple levels for Hardware and Software • Standards: VITA 65 and SOSA™-alignment www.annapmicro.com/product-category/fpga-boards-2/

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Interface Concept ™ This This next-generation next-generation WILD100 WILD100™ 7-Slot 7-Slot3U 3UOpenVPX OpenVPXChassis Chassis ™™ (WC3170) (WC3170) isis both both SOSA SOSA -aligned -aligned and and 40/100Gb 40/100Gb Ethernet Ethernet capable. capable. The The COTS COTS benchtop benchtop Chassis, Chassis,Backplane, Backplane,and andsecure secure Chassis Manager are designed from the ground up Chassis Manager are designed from the ground up totoecoeconomically nomically speed speed development development of of 40/100GbE 40/100GbE Systems Systems that that are are aligned aligned with withthe theSOSA SOSATechnical TechnicalStandard.

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Also Also available availableare aremodules modulesfor forFPGA FPGADigitization Digitizationand andProcessProcessing, ing, Recording, Recording, SBC, SBC, and and Switching.

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26 | VITA Technologies Application Guide Winter 2020

ComEth4590a

The ComEth4590a is a 3U 1/10/40 Gigabit Ethernet Switch with Data and Control Planes. It is a high performance ruggedized dual plane 3U VPX Layer 2/3 Ethernet switch developed in alignment with the SOSA™ (Sensor Open Systems Architecture) Technical Standard. It integrates two sets of independent layer 2 (Ethernet) and layer 3 switches & control processors to support physically separated Control and Data Planes for highly secured 3U VPX systems. These two Ethernet packet processors, managed by the Dual core ARM processors, offer remarkable switching capabilities with 1G, 10G and 40G Ethernet configurations. https://www.interfaceconcept.com/products/Ethernet-Switches/ 3U-VPX/309-ComEth-4590a-3U-VPX-11040-Gigabit-Ethernet-Switchwith-Data-and-Control-Planes

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TE Connectivity’s (TE) NanoRF contacts and modules already offered the most advanced RF platform within the VITA 67 framework. Now, TE engineers have pushed the limits even further, integrating RF and optical in the same module for unprecedented density. NanoRF’s floating insert can house RF contacts and MT ferrules together, fitting up to 10 RF contacts and one MT per half module. www.te.com/sosa

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MULTIGIG RT 3 Connectors

THE FUTURE IS BACKWARDS COMPATIBLE. MULTIGIG RT 3 and RT 2-S backplane connectors meet VITA 46 standards while enabling speeds of 32+Gb/s. This makes them the fastest rugged backplane connectors TE Connectivity (TE) has ever designed.

They’re also fully intermateable with legacy VPX products, including standard RT-2 connectors – meaning you don’t need to sacrifice tomorrow’s speeds for flexibility today.

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W-IE-NE-R Power Electronics VPX336 / VPX340 Series

VPX336 / VPX340 are State-of-the-art, rugged VITA62 compliant 3U/0.8" conduction cooled VPX power supplies, built to satisfy the most challenging application requirements while providing up to 400W power at highest efficiency. A wide range 15-to-40V DC input combined with multi-stage input filter protects the power supply for reverse polarity and performs EMI filtering. MIL-STD-461, 704 and 1275 compliance as per VITA62 has been successfully tested at an accredited 3rd party test lab.

An embedded microprocessor with health monitor provides system status and monitoring/control via i2C bus or USB. Ruggedized to MIL-STD-810 with standard acrylic conformal coating to withstand sand, dust and salt atmosphere. Parylene coating on request! www.wiener-d.com/sc/power-supplies/VPX-PS/

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Dawn VME Products 800 Watt 3U OpenVPX Conduction Cooled Power Supply

The PSC-6238 is designed to operate in a military environment over a wide range of temperatures at high power levels, is extended shock and vibration compliant per MIL-STD810F and features an onboard real-time clock with switchable Battleshort and NED (Nuclear Event Detect) functions.

Dawn’s PSC-6238 is a wedge lock conduction cooled module on a 1 inch pitch with an operating temperature of -40°C to +85°C at the wedge lock edge. The up to 800 Watt power output true 6-channel supply provides full Open VPX support and is current/load share compatible with up to 4 PSC-6238 units.

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Add SSDs to your VPX system!

Add3U SSDs your VPX The VPXtocarrier withsystem! removable NVMe SSD module is for The 3U VPX that carrier with the removable SSDofmodule is for applications require frequentNVMe removal SSD, fast applications the frequent removal fast transfer ratesthat and require large capacities.

It consists of of twoSSD, components; the 3Uand VPX carrier board with PCI express (PCIe) transfer rates large capacities.

It consists of two cominterface VPX3Ubackplane that board mountswith in one of 3U VPX ponents;tothe VPX carrier PCIslot express (PCIe) chassis and module.

Theslot connectors interface tothe VPXremovable backplaneNVMe that SSD mounts in one of 3U VPX between the the driveremovable module and the carrier are ratedThe forconnectors 100,000 chassis and NVMe SSD module. mating cycles to support frequent removals. between the drive module and theinsertions carrier areand rated for 100,000 mating cycles supportcan frequent and Solid removals.

The NVMe SSDtomodule use anyinsertions COTS NVMe State Drive (SSD) providing capacities up any to 16TB transfer The NVMe SSD module can use COTSand NVMe Solidrates State of up to 3940 MB/S. Options for FIPS197, TCG opal and miliDrive (SSD) providing capacities up to 16TB and transfer rates tary No Tools option usesfor thumbscrews on drive of uperase. to 3940 MB/S. Options FIPS197, TCG opalmodule and milito allow easy removal. tary erase. No Tools option uses thumbscrews on drive module AtoPC kit iseasy available that allows NVME drive module to be used allow removal. with a PC for data transfer. The drive module can be easily A PC kit is available that allows NVME drive module to be used removed from VPX system and taken to PC. with a PC for data transfer. The drive module can be easily removed from VPX system and taken to PC. FEATURES • Capacities up to 16 TB FEATURES • 3940 MB/S Transfer rates • Capacities up to 16 TB • Removable SSD module • 3940 MB/S Transfer rates • PCIe Gen 3 x4 interface • Removable SSD module • 100,000 mating cycles PCIe Gen Fat 3 x4Pipe interface •• OpenVPX (FP) • 100,000 mating • VITA 46, 47, 48, 65cycles OpenVPX Fatstorage Pipe (FP) •• Boot and/or disk VITA 46, 47,or48, •• Conduction Air65 cooled Boot NVMe and/orSSDs storage disk •• COTS • Conduction or Air cooled • Military erase options • COTS NVMe SSDs • FIPS197, TCG Opal options Military erase •• VxWorks, Linux,options Windows support • FIPS197, TCG Opal options For more information, contact us at 480-483-3777.

• VxWorks, Linux, Windows support https://www.redrocktech.com/products/vpx-storage-products

For more information, contact us at 480-483-3777. https://www.redrocktech.com/products/vpx-storage-products VITA Technologies Application Guide Winter 2020 |

27

VITA Technologiess Application Guide

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