VITA Technologies Winter 2018 with Application Guide

p. 5 Editor’s Foreword Visions of Sugar Plums!

p. 10 R oadmaps VITA’s switched fabrics roadmap

Advertiser Index Page Advertiser

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2 | VITA Technologies Application Guide Winter 2018

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WINTER 2018 | VOLUME 36 | NUMBER 2

@VitaTechnology

On the cover The VITA Technologies 2018 Application Guide showcases technologies based on VITA standards, including FMC, OpenVPX, XMC/PMC, and related rugged boards, systems, and components. Featured on the cover: Annapolis Micro Systems’ WILD FMC+ GM60 ADC & DAC with RFSoC; Galleon Embedded Computing’s Galleon serial FPDP XMC quad channel VITA 17.1-2003; and Amphenol-BSI’s enabling the evolution of technology.

VITA’s switched fabrics roadmap »» p. 10

By Jerry Gipper, Editorial Director

FEATURES

10 Special Feature

Jerry Gipper

VITA’s switched fabrics roadmap

16 Technology Features 1, 2, 3, ... Slots are In

By Jerry Gipper

VITA 49: Software radio’s evolving language

By Rodger Hosking, Pentek

Next generation VPX backplane production technology

By Gary Rutledge, Amphenol

»» p. 20

VITA 49: Software radio’s evolving language

By Rodger Hosking, Pentek

DEPARTMENTS

5 Editor’s Foreword

Jerry Gipper

Visions of Sugar Plums!

6 VITA Standards Update VITA Standards Organization activity updates

8 Defining Standards VITA 57.4: FMC+

28 VITA Technologies Application Guide Next generation VPX backplane production technology

»» p. 24

OpenVPX

By Gary Rutledge, Amphenol

PMC/XMC VPX

All registered brands and trademarks within VITA Technologies magazine are the property of their respective owners. ™VPX and its logo is a registered product/trademark of VITA. © 2018 OpenSystems Media © 2018 VITA Technologies enviroink.indd 1

4 | VITA Technologies Application Guide Winter 2018

10/1/08 10:44:38 AM

www.vita-technologies.com

Editor’s Foreword

By Jerry Gipper, Editorial Director @VitaTechnology

jerry.gipper@opensysmedia.com

Visions of Sugar Plums!

We have 20 sponsors lined up for the 2019 edition of Embedded Tech Trends to be held at The Andaz in San Diego, California on January 28 and 29. Embedded Tech Trends is an industry-wide forum where suppliers of component, board and system level solutions meet exclusively with members of relevant industry media to discuss technologies, trends, and products.

The theme for 2019 is “The Future is Now.” With all of the work that has been done with standards related to VPX, FMC, and other technologies, we are finally starting to see the fruits of the labor in the form of significant design wins and contract awards. The technology of the future that we have all been working on so hard is here now. I will have a complete write-up summarizing the presentations in the next edition of VITA Technologies.

A tremendous amount of energy spent in 2018 was used in lining up three different programs from three U.S. Departments of Defense (DoD) services. These programs have come together with a common objective to solve their respective acquisition problems with an agreed upon, open architecture standard. The Navy’s Hardware Open Systems Technologies (HOST) standard, the Army’s Modular Open Suite of Standards (CMOSS) initiative, and the Air Force’s Sensor Open System Architecture (SOSA), have all converged under the SOSA Consortium which is maintained by The Open Group.

We have talked about this in the past, but 2018 saw a lot of intense activity from the various working groups in their quest to deliver a set of standards and conformance requirements. Weekly conference calls and bi-monthly face-to-face meetings were well attended by members representing all facets of the ecosystem. There is still a lot of work ahead, www.vita-technologies.com

but the membership list is growing each month and there is planning for imminent interoperability workshops to demonstrate progress. The leadership of the teams is pushing hard to keep on schedule and to not stray from the commitment to using open architecture standards.

OUR SINGLE BIGGEST DESIGN CHALLENGE REMAINS DEALING WITH SIGNAL INTEGRITY ISSUES AT THESE HIGH SIGNAL SPEEDS. Looking a bit into my crystal ball, I am seeing a lot of effort around pushing the performance level to the next step with standards based on serial switched fabric technology.

Ethernet, PCI Express, and InfiniBand standards bodies have all released their 25 Gbps standards. Now VITA is working to update related standards to incorporate connector technology to support the faster speeds. Check out my article on page 10 on “VITA’s switched fabrics roadmap” for some insight into what to expect. VITA is busy updating our roadmaps and will roll out new versions at Embedded Tech Trends.

Our single biggest design challenge remains dealing with signal integrity issues at these high signal speeds. Copper is at its limit even though the brilliant engineers in our industry continue to squeeze a bit more out each year. We are about to hit a wall forcing more effort into solutions based on optical technology. We have incorporated an increasing amount of optical interconnectivity into VPX through the VITA 66 optical standards, but this is only the first step towards eventual incorporation of optical links in backplanes.

Another area of concern under discussion within the industry is the need for even smaller form factor boards capable of withstanding the rugged environments of the critical embedded computing industry. These form factors must also be capable of maintaining the current roadmap for performance and I/O connectivity. We are going to have to think hard about what innovation is needed to address this issue.

With a strong business environment predicted for 2019, we should be in for an interesting year.

Christmas is coming and it’s time to start thinking about gifts! I’ve reached the point in my life where I can get by with sending checks to the kids and grandchildren, so I spend minimal time shopping for gifts. I can turn more of my focus on MY Christmas list. Being a gadget guy and lured by the light of bright shiny new gadgets, I’m pretty easy. But my tastes have gotten a bit more expensive.

Top of the list this year is a new iPad Pro with the Apple pen and keyboard, a DJI Mavic 2 Pro drone for my flying and photography itch, a Samsung Q9F QLED TV for my living room so I can display some of the 75,000+ photos and videos I have stored in Dropbox, and lastly, a Canon EOS 5D Mark IV so I can step up to the next level of photography. It’s great to have the kids out of college!

Here’s wishing everyone a great holiday season and a very happy new year!

VITA Technologies Application Guide Winter 2018 |

5

VITA Standards Update

By Jerry Gipper jerry.gipper@opensysmedia.com

VITA Standards Organization activity updates The September VITA Standards Organization (VSO) standards’ meeting was held in Huntsville, Alabama. This update is based on the results of that meeting. Contact VITA if you are interested in participating in any of these working groups.

Visit the VITA website (http://www.vita.com) for details on upcoming VSO meetings.

ANSI accreditation Accredited as an American National Standards Institute (ANSI) developer and a submitter of Industry Trade Agreements to the IEC, VITA provides its members with the ability to develop and promote open technology standards. The working groups meet face-to-face every two months to address embedded bus and board industry standards issues.

The following standards have recently received ANSI and VITA accreditation: ›› ANSI/VITA 17.3-2018: Serial Front Panel Data Port (sFPDP) Gen 3.0 ›› ANSI/VITA 46.9-2018: VPX: PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules ›› ANSI/VITA 48.4-2018: VPX REDI: Mechanical Standard Using Liquid Flow Through (LFT) Applied to VPX ANSI/VITA 57.4-2018: FMC+, FPGA Mezzanine Card These standards are available for download by VITA members and is posted at the VITA Store for purchase by non-members.

VSO study and working group activities Standards within VITA may be initiated through the formation of a study group and developed by a working group. A study group requires the sponsorship of one VITA member, and a working group requires sponsorship of at least three VITA members.

Several working groups have current projects underway; the following roundup summarizes those projects:

VITA 40: Service and Status Indicator Standard Objective: This standard defines the colors, behaviors, placement, and labeling of service indicator lamps for boards, field replaceable units, and enclosures.

Status: This standard was withdrawn several years ago. VITA has been requested to revive the standard. The original document has been updated to the current format for VITA standards. Minor updates have been made to correct errors in the original document. VITA 40 has been submitted for working group approval to proceed to ANSI balloting.

ANSI/VITA 46.0: VPX: Baseline Standard

ANSI/VITA 47: Environments, Design and Construction, Safety, and Quality for Plug-in Units Objective: Supplying vendors’ certification of commercial-off-the-shelf (COTS) plug-in units to this standard will facilitate the cost-effective integration of these items into larger systems.

Status: ANSI/VITA 47-2005 (R2007) has been opened for revision to improve interoperability, create less reliance on individual supplier ruggedization guidelines, and make sure environments are concurrent with recent VPX updates. The working group has placed the document in the ANSI ballot stage. The various dot standards are in final working group review.

Several dots standards have been started to support the original VITA 47.0 standard.

VITA 47.1: Defines the requirements common across the family of standards.

VITA 47.2: Defines the unique requirements related to products meant to align with the applications defined in IPC J-STD-001, Class 2.

VITA 47.3: Defines the unique requirements related to products meant to align with the applications defined in IPC J-STD-001, Class 3.

VITA 51.4: Reliability Component Derating

Objective: The VITA 46 base standard defines physical features that enable highspeed communication in a compliant system.

Objective: The goal of this study group is to develop a new component derating standard.

Status: The baseline VPX standard is scheduled for its five-year review. The working group is working to align it with recent work on VITA 65, VITA 66, and VITA 67 and to add performance enhancements.

Status: The study group has been meeting to discuss the scope and outline potential sources of data for this activity.

6 | VITA Technologies Application Guide Winter 2018

www.vita-technologies.com

VITA 57.1: FMC, FPGA Mezzanine Card Objective: This standard describes FMC I/O modules and introduces an electromechanical standard that creates a low overhead bridge. This is between the front panel I/O, on the mezzanine module, and an FPGA processing device on the carrier card, which accepts the mezzanine module.

Status: The working group has completed work on a revision to the original VITA 57.1 standard. They are moving to a working group approval ballot.

A new study group has been formed, VITA 57.5 Physical Tools to Aid in FMC+ Development, to define a set of development tools. Interested parties are invited to join this study group.

ANSI/VITA 65: OpenVPX Architectural Framework for VPX Objective: The OpenVPX architectural framework standard is a living document that is regularly updated with new profile information and corrections.

Status: New profiles based on work with Sensors Open Systems Architecture (SOSA) are being developed.

Rates (BER) for multiple fabric types. This also allows module developers to design plug-in modules that are interoperable with other modules when used with a compliant backplane.

Status: The working group is updating the draft of this standard.

VITA 78.1: SpaceVPX Lite Systems Objective: This document leverages the work done on ANSI/VITA 78 to create a standard with an emphasis on 3U module implementations. The most significant change from SpaceVPX is to shift the distribution of utility signals from the SpaceUM to the System Controller to allow a radial distribution of supply power to up to eight payload modules.

Status: The working group has developed a draft document of the standard that is currently under review.

VITA 86: High Voltage Input Sealed Connector Power Supply Objective: This standard defines an environmentally enhanced connector pair, which is compatible with the pinouts as defined in VITA 62.0 for power supplies operating in harsh environments operating off of a high voltage input (270VDC). The connector pair features wider separation between input pins and a sealed connection.

Status: The working group is collecting inputs before developing a draft document.

Copies of all standards reaching ANSI recognition are available from the VITA online store (www.vita.com/Purchase). For a more complete list of VITA standards and their status, go to www.vita.com/Standards.

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VITA 66.5: VPX: Optical Interconnect, SpringLoaded Contact on Backplane Objective: This document describes an open standard for configuration and interconnect within the structure of VITA 66.0 enabling an interface compatible with VITA 46 containing blind mate optical connectors with fixed contacts on the Plug-In Module and floating displacement on the backplane.

Status: The working group is developing the draft document.

VITA 68.2: VPX: Compliance Channel Objective: This standard defines a VPX compliance channel including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates. This allows backplane developers to design a backplane that supports required Bit Error www.vita-technologies.com

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VITA Technologies Application Guide Winter 2018 |

7

Defining Standards

By Jerry Gipper

VITA 57.4: FMC+ Field-programmable gate arrays (FPGAs) are utilized in many applications, with the range expanding as new variations of FPGAs emerge. By design, FPGAs are easily reconfigured as application needs change. But sometimes a change to the front-end hardware connecting the FPGA to a real-world application must also change. Until the advent of the FPGA Mezzanine Card (FMC), there was no universally accepted way to modularize the I/O. FMC must now continue to improve in order to meet the latest wave of performance requirements.

FMC, ANSI/VITA 57.1, is a very popular mezzanine card standard used in many different applications. It is host form factor independent, so you will find it used in everything from motherboards to VPX. The standard was driven and developed by the FPGA community to modularize I/O into an FPGA. As a result, it has established itself as the go-to mezzanine when using an FPGA. However, the original standard, ratified in 2008, needed a performance boost to keep up with today’s faster FPGAs. Gigabit serial interfaces at speeds approaching

32Gbps [Gigabits per second] necessitated an update to the standard.

Efforts under the VITA 57.4 working group were started in 2014 to make improvements to FMC. The primary goal of the working group was to extend the Gigabit transceiver support specified in the VITA 57.1 standard. A basic premise of the working group was to maintain backward compatibility between new VITA 57.4 carrier cards and existing VITA 57.1 mezzanine modules. VITA 57.4 was quickly dubbed FMC+ by the working group.

8 | VITA Technologies Application Guide Winter 2018

After a few false starts by the working group, the team at Samtec stepped up to take on the daunting task of bringing the efforts to a conclusion (See Figure 1).

It took well over two years, but the efforts

FIGURE 1

Samtec SeaRay Connector.

www.vita-technologies.com

were rewarded in July with the final accreditation of the ANSI/VITA 57.4-2018 “FPGA Mezzanine Card Plus (FMC+) Standard” both by ANSI and VITA. FMC+ extends the original FMC standard by specifying two new connectors that enable additional Gigabit transceiver interfaces that run at up to 28Gbps.

It also describes FMC+ I/O modules which support this enhanced version of the FMC electro-mechanical standard. Additional signals to support a backplane reference clock and synchronization have been added. The VITA 57.4 standard is backwards compatible in that a VITA 57.4 carrier card can still support a VITA 57.1 FMC. Two new connectors provide FMC+ capability. The High Serial Pin Count (HSPC) connector is in a 14 x 40 configuration yielding 560 pins. This increases the number of multigigabit interfaces from 10 to 24, capable of data rates up to 28Gbaud in each direction.

FMC+ also specifies an optional High Serial Pin Count extension (HSPCe) connector in a 4 x 20 array yielding an additional 80 pins. This supports up to eight additional multigigabit interfaces.

Utilizing both HSPC and HSPCe connectors presents 32 links capable of data rates up to 28Gbaud in each direction.

mezzanine developers in the form of additional standards under VITA 57.5 “Physical Tool to Aid FMC+ Development.” Their project list includes: ›› Loopback Cards – development tool for FPGA designers looking to test and confirm signal integrity between mezzanines and carriers. ›› Jumper Cables – appropriate for users looking to extend FMC+ signals over distances greater than the defined 8.5mm and 10mm stack heights. ›› Jackscrew Standoffs – useful to ease separation of FMC configurations with high-pin counts (i.e. double and triple wide FMC+ cards utilizing HSPCe).

Even this is not the end of efforts. The team is also looking at analysis and simulation tools that would make selecting compatible hosts and modules much easier for integrators.

Companies interested in the development of the FMC standards are encouraged to contact VITA (www.vita.com) to learn how become involved in the evolution of FMC.

Proven

Building Blocks

The standard defines air-cooled versions, which extend to cover a ruggedized conduction-cooled variant, making FMC+ ideal for a broad spectrum of operating environments.

Up to triple width modules are specified to facilitate applications requiring additional carrier card bandwidth, greater space on the front panel, or a larger PCB area.

A large ecosystem of FMC+ host and module suppliers have been expanding the market beyond Analog to Digital Converter (ADC)/Digital to Analog Converter (DAC) products. Several optical, Radio-Frequency (RF), and Digital Signal Processor (DSP) configurations have been released or are currently in development.

The work is not done. VITA 57.1 is open for some updates by the working group.

The team is also anxious to provide better tools and guidance to both host and www.vita-technologies.com

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VITA Technologies Application Guide Winter 2018 |

9

SPECIAL FEATURE

Roadmaps

VITA’s switched fabrics roadmap

By Jerry Gipper, Editorial Director

Over the years, VITA’s charter has evolved to embrace a host of new open architecture standards for critical embedded computing. Originally founded to develop standards and an ecosystem in support of VMEbus, VITA has evolved its interconnect strategy for high performance computing to be based on leading switched fabrics. Most popular are Ethernet, PCI Express, InfiniBand, and Serial RapidIO. Today’s working groups now spend their efforts on developing standards that implement the latest advancements in the roadmaps of these fabrics in various VITA form factors such as VPX, VNX, XMC, and FMC. The working groups are no longer responsible for defining the protocols but ensuring that the right connector technology is defined suitable for VITA form factors and ensuring that the correct connector technology is implemented as appropriate.

To that end, VITA switched fabric roadmaps are highly dependent on the roadmaps of industry established switched fabrics. In this article we will take a look at the current state of the art for the major serial fabrics and how they are being addressed in various VITA form factors.

A switched fabric is a network topology in which network nodes interconnect via one or more network switches in various topologies. Because a switched fabric network spreads network traffic across multiple physical links, it can yield higher total throughput than parallel buses or broadcast networks.

Switched fabrics became popular in the early 2000’s and are now the dominant

interconnect technique for high performance computing.

There are many tricks to extending bandwidth within given limitations. For example, making links wider and using a different modulation scheme to gain more per link bandwidth. All switched fabrics improve bandwidth performance in combinations of the following: ›› Baud rates: Increasing baud rates increase potential bandwidth.

Laws of physics limit performance, limits which we are quickly approaching. ›› Increasing links: Adding more links or lanes to increases

10 | VITA Technologies Application Guide Winter 2018

bandwidth. Spreading the traffic out into more links is like increasing lanes on a freeway, allowing more traffic to flow at the same speed. ›› Modulation scheme: Implementing various modulation schemes enables more bandwidth per link configuration to improve pin efficiency. ›› Transmission media: Moving from copper media to optical media gains the performance advantage of moving from slower electrons to much faster protons. Limitations in optical media make it hard to use this in all cases, but when it can be used, tremendous performance gains are achieved. www.vita-technologies.com

SPECIAL FEATURE

The good news for VITA working groups is that all of the serial fabrics are on a similar performance curve, challenged with the same advancements in transceiver and connector technologies. The VITA roadmap benefits from this in that we can make improvements across the appropriate VITA standards as determined by the target applications.

Ethernet https://ethernetalliance.org/ the-2018-ethernet-roadmap/ Ethernet is the industry workhorse.

Having been around even longer than VITA, it has evolved to stay relevant in today’s most demanding applications. In March, the Ethernet Alliance, the Voice of Ethernet, released the 2018 version of its roadmap (See Figure 1). The map provides the industry with the directions needed to navigate the many roads making up today’s Ethernet ecosystem.

With all the new standards released by the IEEE 802.3 Ethernet Working Group and the supporting technologies, navigating today’s Ethernet has grown increasingly complex.

Ethernet is used in a variety of ways in a typical system, from a backplane connection to tradition Ethernet ports, making cutting through all of the variations of Ethernet an interesting challenge. In the VITA technology application space, the relevant working groups consider the Ethernet roadmap before the appropriate speeds and solutions can be determined. The 2018 Ethernet Roadmap helps them understand how Ethernet is achieving 100 GbE [Gigabit Ethernet], 200 GbE, and 400 GbE. The roadmap also provides guidance in which Ethernet configurations are best suited for backplanes as utilized in many VITA standards.

PCIe https://pcisig.com/ The Peripheral Component Interconnect Special Interest Group (PCI-SIG) roadmap has PCI 5.0 ready in 2019 at 128 Gigabit per second (GB/s). Early revisions of www.vita-technologies.com

FIGURE 1

VITA 57.1 FPGA Mezzanine Card (FMC) simplified pin class definitions.

Raw Bit Rate

Link Bandwidth (BW)

BW/Lane/Way

Total BW x16

PCIe 1.x

2.5 GT/s

2 Gb/s

250 MB/s

8 GB/s

PCIe 2.x

5.0 GT/s

4 Gb/s

500 MB/s

16 GB/s

PCIe 3.x

8.0 GT/s

8 Gb/s

~1 GB/s

~32 GB/s

PCIe 4.x

16 GT/s

16 Gb/s

~2 GB/s

~64 GB/s

PCIe 5.x

32 GT/s

32 Gb/s

~4 GB/s

~128 GB/s

TABLE 1

PCI Express performance, courtesy of the PCI-SIG.

PCIe 5.0 have been made available to the SIG’s 700+ members to consider. Many of those members are also hard at work on products for version 4.0, which at version 0.9, is considered “feature complete” and awaits only final signoff. The SIG says it’s seeing “unprecedented interest in our PCIe 4.0 compliance testing and early adopters have already tested 16GT/s solutions.” The PCI-SIG is driven to double the bandwidth every three years, if only to keep up with other expected accelerations like the advent of 400 Gbps Ethernet.

Most implementations today are at PCIe 3.0. VITA applications are dependent on the integration of PCIe into processors, bridges and I/O devices. As these devices start to be used in next generation designs, the pressure will increase to improve the connector technology used in the various VITA standards. At some point, PCIe performance exceeds what is possible on a copper backplane, PCIe 5.0 may be that point. (See Table 1).

InfiniBand https://www.infinibandta.org/infiniband-roadmap/ InfiniBand is used in a variety of VPX products. A contraction of “Infinite Bandwidth,” in theory, a designer can keep bundling links so that there is no theoretical bandwidth limit. InfiniBand is a favorite serial fabric for high performance computing and storage systems.

VITA Technologies Application Guide Winter 2018 |

11

Roadmaps

SPECIAL FEATURE

The InfiniBand Trade Association’s (IBTA’s) InfiniBand roadmap is continuously developed as a collaborative effort from the various IBTA working groups. Members of the IBTA working groups include leading enterprise IT vendors who are actively contributing to the advancement of InfiniBand. The InfiniBand roadmap details 1x, 2x, 4x, and 12x port widths with bandwidths reaching 600 Gb/s data rate HDR (High Data Rate) in the middle of 2018 and 1.2Tb/s data rate NDR (Next Data Rate) in 2020. The roadmap (See Figure 2) is intended to keep the rate of InfiniBand performance increase in line with systems-level performance gains.

Architecture processors. The RapidIO Trade Association has mapped out a plan for future performance enhancements that keep it in step with the other switched fabrics (See Figure 3).

Current situation Pin count and connector capability are the two major limiting factors in most VITA form factor standards. Where possible, the working groups project as far into

RapidIO http://www.rapidio.org/ rapidio-roadmap/ Though not as widely implemented on VITA technology-based products, RapidIO is used with several VPX products, particularly those based on Power

FIGURE 2

InfiniBand roadmap, courtesy of the InfiniBand Trade Association.

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the future as is reasonable. Here is a recap of where the VITA technologies stand today.

VPX The VITA 46 working group, responsible for the core VPX standards, is currently documenting updates to the standard. Top on the list are performance enhancements to take VPX to 25 Gbps and beyond. New connector technology has been proposed

and plans for testing are underway.

This should be enough head room to accommodate bandwidth performance improvements on the near horizon. Expect to see an approved standard in 2019 with products to soon follow.

VPX has also defined a set of standards (VITA 66.x Optical Interconnect On VPX) that support optical interconnects in several different blind mate connector styles. While not a backplane distributed solution, VITA 66 provides a very high bandwidth channel for direct access to VPX slots. These optical interconnect options provide even more bandwidth for the most demanding applications.

The same switched fabric protocols used on the copper interconnections can also be used on these optical links.

FMC

FIGURE 3

FMC+ ANSI/VITA 57.4-2018 was recently ratified, bringing the maximum multigigabit interfaces to 32 full duplex channels. Additionally, throughput per

RapidIO Roadmap, courtesy of the RapidIO Trade Association.

“I need COTS, but ... ” ... the environment is too harsh. ... there might be a lot of design changes. ... our I/O needs are very complex. ... we require a lot of customization. ... our previous COTS vendor failed.

LCR Embedded Systems design and manufacturing can help you take advantage of all the cost and schedule benefits of COTS while still meeting your custom application and environmental requirements.

Chassis • Backplanes • Integrated Systems • VPX • AdvancedTCA • VME • CompactPCI • Custom (800) 747-5972 • sales@lcrembedded.com • www.lcrembeddedsystems.com www.vita-technologies.com

VITA Technologies Application Guide Winter 2018 |

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Roadmaps

SPECIAL FEATURE

multigigabit interface has increased to 28 Gbps in each direction. This allows for higher data rates and expanded bandwidth to fit within the same form factor as FMC. The next steps here will likely lead to a new form factor and optical interconnections. FMCs with optical I/O are already in production, pushing the need for more bandwidth to the carrier even harder.

XMC The popular mezzanine card, XMC, supports PCIe 3.0. Nothing is currently in the works but watch for new mezzanine standards to emerge as processor technology shifts to faster fabric solutions.

Optical interconnections could also be in the “cards.”

Faster in the Future New schemes for improving data movement are continuously being proposed for study, this is one area where there is

no shortage of innovation. One protocol scheme in particular has started some ­spirited conversation among a small group of VITA members. Chord signaling, developed by Kandou Bus, is a multiwire version of NRZ signaling, CNRZ-5 encoding, which transmits five bits over six wires (“C” stands for chord signaling). Even more intriguing is the drive of the Optical Internetworking Forum (OIF) to go beyond 112 Gbps at the chip die level, where hopefully some of the innovation will lead to improvements that can be extended to VITA technology.

CHORD SIGNALING, DEVELOPED BY KANDOU BUS, IS A MULTIWIRE VERSION OF NRZ SIGNALING, CNRZ-5 ENCODING, WHICH TRANSMITS FIVE BITS OVER SIX WIRES. EVEN MORE INTRIGUING IS THE DRIVE OF THE OPTICAL INTERNETWORKING FORUM (OIF) TO GO BEYOND 112 GBPS AT THE CHIP DIE LEVEL, WHERE HOPEFULLY SOME OF THE INNOVATION WILL LEAD TO IMPROVEMENTS THAT CAN BE EXTENDED TO VITA TECHNOLOGY. “Big data” systems are the driver for serial fabrics. VITA’s role is to be vigilant in tracking new advancements and then working with the user side of the VITA technology ecosystem to be sure connector technology is mapped to the appropriate form factors to meet the user’s needs with a mainstream, cost-effective solution.

CCIX, GEN-Z, OPA, AND OPENCAPI Cache Coherent Interconnect for Accelerators (CCIX), Gen-Z, Lightfleet Multiflo, Omni-Path Architecture (OPA), and Open Coherent Accelerator Processor Interface (OpenCAPI) are all interconnects that are addressing similar problems focused on tighter coupling between processors and accelerators (GPUs, FPGAs, etc.) and emerging memory/storage technologies utilizing 25 Gps and faster speeds. Each approach is different, and each has a strong list of supporters involved with their respective consortia or companies. Many of the more interesting interconnect solutions on the horizon are variations on data or memory centric architectures; move the data less frequently and the system performance goes up.

Here is a sampling of possibilities.

Cache Coherent Interconnect for Accelerators or CCIX (pronounced ‘see six’) is a chip–to-chip interconnect that enables two or more devices to share data in a cache coherent manner (https://www.ccixconsortium.com).

Gen-Z is a high performance, low latency, memory-semantic fabric that can be used to communicate to every device in the system. Gen-Z components use low-latency read and write operations to directly access data and use a variety of advanced operations to move data with minimal application or processor involvement. (https://genzconsortium.org)

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Lightfleet Multiflo data distribution system (DDS) is an adaptive interconnect designed to support parallel and distributed computing applications, based on the concept of self-directed data flow. The Multiflo DDS consists of one or more interconnected data-distribution modules (DDMs) that send and receive message packets to and from host-bus adapters (HBAs) mounted in the commodity computers or blades comprising the distributed computing system. (http://lightfleet.com/#intro) Omni-Path Architecture (OPA) is a high-performance communication architecture owned by Intel. It aims for low communication latency, low power consumption, and a high throughput. Intel plans to develop technology based on this architecture for exascale computing. (https://www.intel.com/ content/www/us/en/high-performance-computing-fabrics/ omni-path-driving-exascale-computing.html) Open Coherent Accelerator Processor Interface (OpenCAPI) provides an open, high-speed pathway for different types of technology – advanced memory, accelerators, networking and storage – to more tightly integrate their functions within servers. This data-centric approach to server design, which puts the compute power closer to the data, removes inefficiencies in traditional system architectures to help eliminate system bottlenecks and significantly improve server performance. (https://opencapi.org/) www.vita-technologies.com

TECHNOLOGY FEATURE

VPX Small Systems

1, 2, 3, ...

Slots are In

By Jerry Gipper, Editorial Director

When one envisions a VPX system, the image that often comes to mind is a multislot high performance computing system full of processing and I/O boards. But there is a completely different class of VPX “systems” that range from one to three slots in size, primarily in a 3U form factor. What do these “systems” look like and what is driving their existence?

Two applications seem to be leading the charge. Development systems with one to three slots provide engineers a quick way to get started with the development process. These are usually commercial grade, air-cooled chassis designed for use in development labs environments.

Two-slot: Also dedicated to very specific functions, with a fair amount of application essential functionality built into the chassis. The second slot provides a degree of expandability to add or change functionality as needed.

The second type are small, portable or mobile systems, usually conduction or passively cooled and designed for rugged operating environments.

Three-slot: The choices for three-slot VPX systems increase dramatically with many products available from virtually all VPX system suppliers. This is a sweet spot because it is still a very small size but has the capability to support a system with a dedicated processing board and a couple of slots for application specific I/O or additional processing. A three-slot system lends itself well to a simple full mesh backplane configuration for maximum bandwidth between modules. Many of the suppliers of three-slot systems offer customizable I/O so that the system can be effectively adapted to ­specific application needs.

Trends in slot count are emerging

To further understand what these systems look like, let’s look at a few examples.

One-slot: These tend to be dedicated to a very specific purpose, i.e. development system. The single slot is dependent on a backplane primarily for power and connection to external I/O.

Development Systems Many companies offer small development systems for VPX. In fact, these were the first of the products announced using VPX technology. They come with 1-3 VPX slots in a generic configuration so that board and software engineers can quickly begin the

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TECHNOLOGY FEATURE

FIGURE 1

prototyping stage. The chassis is small with a power supply and cooling for a small number of VPX boards.

One of the more extreme examples is a recently announced development system, the Model 8257, from Pentek that has only one 3U VPX slot (See Figure 1). It is intended to be a quick start development platform designed for a specific 3U VPX board with a mezzanine. The backplane simply provides power to the board and provides an interface to a rear transition module for I/O access. Developers can connect a notebook or desktop PC and develop, run, and debug their application right out of the box. The advantage to this strategy is that Pentek can use an off-the-shelf chassis and with a few minor tweaks, load it with a carrier card for whatever mezzanine is preferred so that a developer can be up and running in no time. The modularity of the architecture makes it easy to incorporate other options as new products are developed. In this case, both Pentek and their customers win with a proven, cost-effective solution that can be quickly modified.

Deployable Systems Here is where it starts to get interesting. 3U VPX lends itself well to small, mobile systems in rugged operating environments. To achieve the size, weight, and power (SWaP) goals of these applications, conduction or passive cooling strategies are often used, eliminating the need for fans.

SR Technologies implements an interesting low slot count product strategy for their products with capabilities that include waveform, protocol stack, and user interface (UI) development primarily for Signal Intelligence (SigInt)/Electronic Warfare (EW) markets. Historically these capabilities have been delivered, as individual federated tactical ‘black boxes’ incorporating general purpose processors (GPPs), RF front ends, and custom designed software-defined radios (SDRs). As open architecture standards such as VPX have emerged, customer requirements required redesigning and deploying these capabilities as 3U conduction cooled VPX modules. www.vita-technologies.com

Model 8257 3U VPX. Photo courtesy of Pentek.

As customer needs changed, SR Tech­ nologies needed to find a way to take these second-generation capabilities and deploy them back into the tactical market without large redesign efforts.

For the tactical market, SWaP is at a premium and there were no easy solutions to this without designing an ecosystem of chassis to support it. For SR Technologies, the concept of a small tactical VPX chassis, incorporating just the essential elements of a standard sensor module, quickly came into focus.

Each chassis has basic building blocks within it, that are deemed essential to any operation and worthwhile of being embedded into the chassis, for example, power supply, Global Position System (GPS), and chassis management. Each module slot gets its allocation of power along with GPS on either a serial link and/or Ethernet.

Once the initial roll out of SR Technologies’ developed capabilities was deployed, it was very quickly seen that any third-party capability could be inserted into the chassis with minimal cost and time. This is obviously the whole intent of the open modular standard and

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VPX Small Systems

TECHNOLOGY FEATURE

it played out as per this intent. From an integration viewpoint, the integration exercise became a 10-minute phone call with the third-party module developer followed up by one to two days of integration testing. Very few problems have been encountered and on a number of occasions it’s been plug and play.

One of SR Technologies VPX modules is called the LANShark so it was not a stretch to call the family of chassis Shark­ cages! (See Figure 2). Currently there are single slot and dual slot Shark­cages with up to four slots to follow.

With all of these variations, the funda­ mental philosophy of the cage has remained intact: ›› Embed the PSU, chassis management card and GPS. ›› Keep everything passively cooled ›› Use common off the shelf connectors and stock all the long lead items for quick delivery.

Figure 2B

FIGURE 2A & 2B Sharkcage, Photo courtesy of SR Technologies.

Figure 2A

These small systems point out how important a “system-level” strategy is to a success­ful VPX product line. One quickly notices that key functionality, very generic to a series of applications, can be built into the chassis. This functionality can be used over a broad range of products making it possible to swap out core VPX modules to quickly redefine a platforms mission without going through long and expensive development and integration processes.

One problem that is becoming apparent is the need for system level standards to ensure the interchangeability of system modules. A lot of focus is going into ensuring that board-level modules comply to standards, but more work needs to be done at the next level up. Many applications consider the box level to be a replaceable unit and standards are going to be needed to make this possible.

Expect to see many more of these small 3U systems.

OpenSystems Media works with industry leaders to develop and publish content that educates our readers.

Critical Techniques for High-Speed A/D Converters in Real-Time Systems

By Pentek An Analog-to-Digital converter (ADC) accepts an analog voltage at the input and produces a digital representation of that voltage at the output, which is called a “sample.” The two primary characteristics of ADCs are the rate of conversion or sampling rate and the accuracy of each digital sample expressed as the number of binary bits or decimal digits per sample.

In this white paper, dive into Pentek’s review of sampling techniques, FPGA technology, and the latest high-speed ADC products and applications based on them.

Read this paper at https://bit.ly/2DCdtu9

18 | VITA Technologies Application Guide Winter 2018

Check out our white papers at http://vita.mil-embedded.com/ white-papers/

www.vita-technologies.com

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TECHNOLOGY FEATURE

VITA 49

VITA 49: Software radio’s evolving language

By Rodger Hosking, Pentek

Overwhelming adoption of software radio as a critical technology for real-time embedded systems spurs defense customers to expand its capabilities for the constantly evolving needs of military applications.

With numerous vendors in the market, customers are seeking interoper­ ability and easy insertion of new technology. However, data protocols, metadata information, and control software have traditionally been vendor-unique, proprietary solutions, capable of meeting the require­ ments of any given system, but highly variable, even when delivered by the same vendor. To overcome these inconsistencies, VITA 49 offers standards for implementing these features to boost user confidence in multivendor, open architecture systems, and simplify life cycle support.

Software radio grows up Twenty-five years ago, digital signal processing (DSP) had already revolutionized acquisition and reproduction of audio and even video signals, spelling the certain demise of analog media like records and tape. Nevertheless, few engineers would have predicted how rapidly DSP would transform virtually every aspect of systems that use radio waves. Economical hardware capable of boosting data conversion and real-time signal processing rates by several orders of magnitude seemed a long way off.

Inspired by enormous commercial market potential for practical digital solutions for radio signals, innovative vendors of data converter and DSP technology began rolling out successive generations of faster, smaller, and less expensive devices. Software radio technology now dominates commercial, government, and military systems worldwide, growing at almost 10 percent annually and expected to reach $30 billion by 2022 according to the MarketsandMarkets, Inc. report titled: “Software Defined Radio Market – Global Forecast to 2022,” which published in March.

One common factor across this vast diversity of solutions is the universal requirement for handling digitized radio signals, both for receive and transmit operations. In disposable end products like a cell phone, a single vendor decides how to manage signal data, with no tangible impact on the user. However, larger systems that must be maintained throughout a life cycle or periodically upgraded with new features and technology greatly benefit from a well-defined methodology for representing

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PENTEK

www.pentek.com

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@Pentekinc

LINKEDIN

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TECHNOLOGY FEATURE

A separate Context Packet contains the same Stream ID, linking it logically to the associated IF Data Packet. It also contains metadata words so that the destination application can know how to process the samples in the IF Data Packet.

These packets are completely independent of the transport layer, so they can be conveyed through virtually any network or path. This includes point-to-point links between components, staging in shared memory, and transmission across multiboard backplanes, local area networks (LANs), and even the Internet. Packets can also be recorded on local disk arrays or storage area networks (SANs) for later processing. In spite of non-deterministic delays though these paths, once the packets are received or retrieved, the original time stamp and metadata allow the payload data to properly be identified and processed accordingly.

The time stamp information includes a coarse field with resolution in seconds, often derived from a Global Positioning System (GPS) or Network Time Protocol (NTP) reference. The fine resolution field precisely stamps the time for the first payload data sample as the count of elapsed data converter sample clocks since the latest second tick. This permits multiantenna diversity receivers and other beamforming applications to detect the relative time of arrival across the channels.

VITA 49.2 expands features and capabilities digital signals. This need is compounded when such systems contain components from different vendors, especially true for embedded military/aerospace applications.

Resonating well with the needs of vendors and customers, VITA 49 served as a proven springboard for extending its reach to standardize additional requirements of software radios. The latest version of the standard was ratified by ANSI and VITA in August 2017 as VITA 49.2.

As depicted in Figure 2, the original VITA 49.0 IF Data Packets were renamed as Signal Data Packets for added versatility. And, they were enlisted in a new role for delivering

VITA 49.0 overview With insightful forecasting of these emerging needs back in 2006, the VITA 49 working group began developing the VITA Radio Transport (VRT) protocol to define a standardized format for delivering digitized intermediate frequency (IF) radio signals. An initial goal was to define packet structures for received signals that contain not only the digitized signal samples but also metadata information that describes the signal.

The first release of the standard was VITA 49.0, which defined IF Data Packets and Context Packets. Figure 1 shows a software radio receiver with typical signal processing blocks from the RF analog signal at the antenna to digital IF output samples that are delivered as payload data into the IF Data Packet.

A precision time stamp and Stream ID, along with header and footer words, are added to form the packet frame. www.vita-technologies.com

FIGURE 1

Software radio receiver delivering VITA 49.0 IF Data and Context Packets.

FIGURE 2

VITA 49.2 supports transmitter Signal Data Packets plus command and control functions.

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VITA 49

TECHNOLOGY FEATURE

outgoing signals into radio transmitter equipment. Here, the time stamp can specify precisely when trigger transmit signals are generated, which is ideal for radar pulses.

VITA 49.2 greatly expands the scope of Context Packets to add many more standardized conventions for new receiver metadata parameters as well as to report operational status and parameter values for transmitters.

Perhaps the most significant new aspect of VITA 49.2 is the ability to control and monitor the status of software radio equipment. Previously, this was done using highly proprietary reads and writes to dedicated hardware registers unique to each product.

Command Control Packets standardize parameter formats for tuning, bandwidth, sampling rates, antenna angle, transmit power, receiver gain, and numerous other useful

You need it right. You want

TOGETHER, THIS VITAL COMMUNITY OF CONTRIBUTORS REPRESENTS A DIVERSE POWERHOUSE FOR SUSTAINED INNOVATION AND COLLABORATION TO MEET FUTURE CHALLENGES. functions. Command Acknowledge packets sent back to the VITA 49.2 Processing and Control System confirm successful execution of the Command Control Packets to help ensure system integrity.

New software radio initiatives Government defense and intelligence organizations have come to recognize the obvious benefits of open standards to take advantage of the latest technology, shorten procurement cycles, and promote market competition. With renewed imperatives and increased funding, these organizations are now actively pursuing and promoting several new initiatives to align with their current and future mission requirements.

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The Open Group consortium formed in 1996 promotes the development of vendor-neutral, open technology standards for successful achievement of business objectives. One recent initiative of The Open Group is the Future Airborne Computing Environment (FACE) Consortium, which includes members from both industry and government to define open standards for avionics systems across all military services. Major goals of FACE are improved interoperability across common components, portability across different deployed platforms, consistent data exchange formats, and a common software environment.

accessories, sub-racks, card cages, test boards, panels and system health monitors.

(510) 657-4444 dawnvme.com/vpx 22 | VITA Technologies Application Guide Winter 2018

Another Open Group initiative incu­bated in FACE is the Sensor Open System Architecture (SOSA) Consort­ium, which focuses attention on Command, Control, Communications, Computers, Intelligence, Surveillance and Recon­ naissance (C4ISR), Radar, Electronic Warfare (EW), electro-optical fusion, and communications systems. The goal www.vita-technologies.com

of SOSA is development of open standard specifications for cross-service applications to reduce costs, encourage industry competition, and speed up delivery of systems to exploit new signals and respond to new threats.

An important mission of the U.S. Army’s Communications-Electronics Research, Development and Engineering Center (CERDEC) is to evolve definition of converged open interface architectures for future systems. The Army’s C4ISR/ EW Modular Open Suite of Standards (CMOSS) initiative extends its earlier VICTORY architecture for vehicle electronics to now share hardware and software components among C4ISR/ EW capabilities, with interoperability across all platforms. Major goals are easier technology refresh, quick reaction “future-proofing” for unplanned capabilities, reduced developmental costs and acquisition costs through greater commercial competition. The CMOSS efforts are converging into the SOSA activities as SOSA has been expanded and broadened to fulfil the open architecture goals of both.

With many common goals, each of these initiatives has adopted VITA 49.2 as its transport protocol standard. By addressing all of the major requirements, it supports multiple applications using a common, standard signal delivery protocol. With sufficiently rich metadata information, the same packet streams can be exploited by different clients with diverse objectives, including SIGINT, ELINT, radar, communications, monitoring and reconnaissance.

Product examples Because of customer flow-down requirements for VITA 49, defense and government embedded systems integrators are increasingly seeking products that support the standard. Following these market incentives, the open architecture COTS vendor community now offers a range of software radio products with factory installed VITA 49 engines.

Figure 3 shows two 3U OpenVPX software radio modules based on the Xilinx Kintex UltraScale FPGA. The Model 52851 www.vita-technologies.com

FIGURE 3

3U VPX software radio modules include FPGA-based VITA 49 protocol engines.

provides two 500 MHz 12-bit A/D converters with digital downconverters (DDCs) and two 800 MHz 16-bit D/A converters. The Model 52141 features a 6.4 GHz 12-bit A/D or two 3.2 GHz 12-bit A/Ds, both with DDCs, and two 6.4 GHz 16-bit D/As with digital upconverters.

Both products include factory-installed IP modules for generating VITA 49.2 Signal Data Packets containing A/D or DDC output samples with precision time stamping. A PPS hardware input signal, typically provided by a system GPS receiver, ensures the data samples are tagged with a specific sample clock counts to support multiantenna TDOA [time difference of arrival] applications. All features are supported by an API library in Pentek’s Navigator Board Support Package.

Pentek’s Navigator FPGA Design Kit includes a complete FPGA project folder for Xilinx Vivado development tools. It contains all AXI-4 compliant IP modules installed in each product, including the VITA 49 Packetizer IP module with full VHDL source code, documentation, and a user manual so that customers can ­customize it as required.

Like any successful standard, VITA 49 continues to evolve as new technology emerges, and as the many active standards consortiums identify new requirements for deployed systems. Evidence of continued progress is ensured by the heightened participation in these efforts by three important groups:

›› Government and military organizations, who use and specify software radio systems for defense sectors and intelligence agencies. ›› Universities and research laboratories, often funded through government grants, who push the technology envelope of software radio by developing new waveforms, detection algorithms, signal exploitation techniques, spectral management strategies, electronic countermeasures, and new methods of encryption and security. ›› Equipment vendors and system integrators, who bring engineering skills, packaging experience, project management, and familiarity with open architecture standards for embedded software radio systems.

Together, this vital community of contributors represents a diverse powerhouse for sustained innovation and collaboration to meet future challenges.

Copies of the ANSI/VITA 49 standards are available from VITA at www.VITA.com.

Rodger H. Hosking is vice-president and co-founder of Pentek, Inc. where he is responsible for new product definition, technology development, and strategic alliances.

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TECHNOLOGY FEATURE

High-Speed Signal Integrity

Next generation VPX backplane production technology

By Gary Rutledge, Amphenol

The new generation of VPX protocols are here and the next generations are on the horizon. The exciting world of high speed has arrived and before we know it today’s technology will be superseded. VPX is “evolving.” The next generation of PCIe and Ethernet will add more complexities to the VPX signal channel.

We are seeing data rates increase exponentially and the evolution of VPX has begun.

What is changing with the evolution of VPX? What are the challenges to facilitate this evolution? There are obvious upgrades required for the hardware and our understanding of the high-speed channel, but we must also consider the production and test environment:

Signal Integrity – not the end of the road

›› ›› ›› ›› ›› ›› ›› ››

What happens when the next generation of products are in production? Our 30 years of experience in backplane design and assembly tells us that the production of high-speed backplanes is as equally important as signal integrity to ensure that all the engineering and design work is not undone during the production phase of the backplane.

Connector technology Engineering knowledge PCB materials Simulation capabilities PCB fabrication Automated production Automated assembly test Production level signal integrity testing

We all understand that the connectors and PCB materials need upgrading along with the engineering knowledge and expertise to design at high speed. PCB fabrication is also a challenge due to backdrills, aspect ratios, copper roughness, tolerances and impedance control (See Figure 1). Signal Integrity is an essential discipline required to define the parameters of the channel for performance at high speed. A huge amount of time and effort is spent on signal integrity which is understandable.

“VPX signal integrity over the backplane needs to be addressed in order to avoid interoperability issues which will become increasingly severe as we move to higher serial baud rates,” says Bob Sullivan, VITA Distinguished fellow.

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AMPHENOL

INSTAGRAM

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TECHNOLOGY FEATURE

“VPX SIGNAL INTEGRITY OVER THE BACKPLANE NEEDS TO BE ADDRESSED IN ORDER TO AVOID INTEROPERABILITY ISSUES WHICH WILL BECOME INCREASINGLY SEVERE AS WE MOVE TO HIGHER SERIAL BAUD RATES.” – BOB SULLIVAN,

VITA DISTINGUISHED FELLOW

As the signal integrity proves, higher data rates require smaller compliant pins and via holes. New connectors include compliant pins as short as 1.10mm and these are pressed into a 0.37mm plated hole. This puts the emphasis on ensuring these pins are assembled correctly and do not compromise the signal.

The assembly technology of yesterday will struggle to process the new generation of compliant pins because of the use of manual press machines and limited test technologies. We need to have 100 percent confidence that all compliant pins are correctly positioned in the via hole and this is the challenge in a production environment.

The importance of production and test The final stage of ensuring that the backplane will function and perform as designed is the production and test phase. Days, weeks, and months of engineering, Signal

FIGURE 1

Integrity simulations, PCB design and post simulation are spent tuning the PCB design, for optimal performance.

Months of engineering work can be quickly undone if the connector pin is not inserted into the PCB hole correctly.

With hundreds of pins in a connector pin field how can we detect one bent pin if we cannot physically see it? (See Figure 2). A pin that is not inserted correctly can cause a system failure and this needs to be detected and fixed before the backplane leaves the production environment.

Backplane PCB Hole Dimensions for Next Generation VPX

FIGURE 2 www.vita-technologies.com

X-ray image of bent compliant pin.

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High-Speed Signal Integrity

TECHNOLOGY FEATURE

Bent pins and the signal The smallest variance in design and production can have the biggest impact on performance at high data rates. What effects do production induced faults have on the signal? A bent pin will have clear effects on the signal including, but not limited to, impedance drop, insertion loss, return loss, and mode conversion (See Figure 3).

The effects of a bent pin are not only limited to the immediate effect on the signal.

What happens over time if the pin is undetected. VPX systems are often deployed in the harshest of environments. There is a risk that the compliant pin can, over time, cause damage to the connector and PCB due to shock and vibration. Causing wear on the protective surface of the PCB and potentially shorting to another copper feature.

The pin could break away from the connector and become a floating object that could cause a short between two other compliant pins.

of the new generation of compliant pin?

(See Figure 4) Unless you have visited a dedicated backplane production facility that is capable of producing backplanes up to 56G PAM4 then you might be surprised by the technologies involved:

Engineers, connector vendors, and PCB vendors have all stepped up and provided a path to higher data rates for VPX. The last link in the chain to ensuring that VPX makes the successful evolution into the next generation of products is the production environment. The investment and infrastructure must be in place to facilitate the production.

›› Light assisted connector placement ›› Pre-press compliant pin engagement ›› Automatic connector press machines ›› Automatic pin scan optical inspection ›› Automatic 100 percent X-Ray inspection ›› Automatic 100 percent automatic SI testing ›› Automatic electrical test ›› Hi-Pot power testing ›› Onsite Signal Integrity specialists

What equipment and processes do we need to be able to successfully assemble next generation VPX backplanes? How do we process the backplane to ensure the integrity

Our use of automated press machines enables us to program the machine to

Enabling the evolution of technology

FIGURE 3A

FIGURE 3B

FIGURE 3 The effects of compliant pints and compliant pins folded.

FIGURE 3C

26 | VITA Technologies Application Guide Winter 2018

FIGURE 3D

www.vita-technologies.com

recognize anomalies during the press process. Each connector has a set profile and an expected force to correctly press the connector. If the recorded force during assembly differs from the profile, then the assembly is flagged and inspected for any potential bent pins.

In addition to the equipment there is also the expertise and knowledge required to introduce a product into and through the production environment. This process often starts at the early stages of a project when signal integrity simulation is complete and PCB layout begins: ›› ›› ›› ››

Design for Manufacture Design for Assembly Design for Test Field Application Engineer (FAE) product support ›› Detailed and concise PCB manufacturing instructions ›› PCB fabricator control – correct drill size and plating, the correct drilling processes, pre-drill and multi-peck drilling, hole T/P and backdrill stub control.

As an example, to avoid plating knee within the plated hole for the compliant pin, the drill process should always be from the press-fit side of the PCB to ensure clean entry of the compliant pin into the plated hole. Clear instructions must be given to the PCB fabricator to control the integrity of the plated hole.

They do not know what the hole is used for or the data rate of the PCB. We conduct regular audits and spot checks on our PCB vendors to ensure quality is maintained and will not adversely affect the signal.

There is a huge amount of expertise and knowledge required to process high speed VPX backplanes. We see identical comparisons to our experiences during the years of evolution in the IT/Datacom markets where data rates also increased exponentially. All of the engineering and production expertise, equipment and infrastructure that we invested to facilitate the IT/Datacom evolution are now required for VPX. www.vita-technologies.com

FIGURE 4 100 percent production level Signal Integrity testing on every signal can identify missing or incorrect backdrills in the PCB that are otherwise invisible. This test will identify and eliminate PCB fabrication faults that otherwise go undetected.

Production and test are often the forgotten links in the chain to ensure the integrity of the signal and as with any chain – it is only as strong as the weakest link. Let’s not forget the importance of Production.

We see production as a vital part in ena­bling the evolution of technology.

Gary Rutledge is the Engineering Manager – EMEA & APAC at Amphenol Backplane & System Integration (ABSI)

RADAR &

Electronic Warfare The Radar/Electronic Warfare monthly newsletter provides features, news, columns, and more covering radar and electronic warfare technology as well as hardware and software designs for systems in the defense and aerospace markets.

Subscribe to receive your copy of the newsletter: http://url.opensystemsmedia.com/radar_quarterly_subscribe Archived newsletters at: mil-embedded.com/radar-electronic-warfare VITA Technologies Application Guide Winter 2018 |

27

VITA Technologiess Application Guide

OpenVPX

APPICATION GUIDE INDEX

Sponsored By:

Company Page

OpenVPX

WILD FMC+ GM60 ADC & DAC with RFSoC

Sponsored by Annapolis Micro Systems . . . . . . . . . 28 Sponsored by Mercury Systems . . . . . . . . . . . . . . 29 Annapolis Micro Systems . . . . . . . . . . . . . . . 28

The WILD FMC+ GM60 ADC & DAC is the industry’s first COTS Mezzanine to feature the new Xilinx® Zynq® UltraScale+™ RF System-on-Chip (RFSoC) technology (ZU25DR, ZU27DR, or ZU28DR).

This breakthrough RFSoC combines FPGA processing and A/D and D/A Converters in a single chip, giving the GM60 card remarkable density and performance.

For maximum performance, pair one GM60 with an Annapolis WILDSTAR™ 3U OpenVPX Baseboard or two GM60s with a 6U OpenVPX or PCIe Baseboard. Annapolis WILDSTAR Baseboards utilize up to three high-performance FPGAs, in addition to the GM60 Mezzanine’s RFSoC. Also designed for standalone use, the GM60 is ideal for applications limited by Size, Weight, Power, and Cost (SWaP-C). This WILD FMC+ card operates within a tight envelope; it is slimmer than a 3U OpenVPX board, with about 45% less depth.

Features: ADC • Channels: 4 • Sample Rate: Up to 4.0 GSps • Resolution: 12 bit DAC • Channels: 4 • Sample Rate: Up to 6.4 GSps • Resolution: 14 bit I/O Connectors (optional 50Ω SSMC or VITA 67) • Four analog outputs • Four analog inputs • One clock input • One trigger input Mechanical and Environmental • Integrated heat sink and EMI/crosstalk shields • Air- or conduction-cooled Clock Synchronization • Software-selectable clock input or onboard PLL clock • All ADCs / DACs across multiple cards easily synchronized wfinfo@annapmicro.com • 410-841-2514 https://www.annapmicro.com/product-category/mezzanine-boards/

28 | VITA Technologies Application Guide Winter 2018

Dawn VME Products . . . . . . . . . . . . . . . . . . 29

Interface Concept . . . . . . . . . . . . . . . . . . . 29

PMC/XMC Alphi Technology Corp. . . . . . . . . . . . . . . . . 30

Galleon Embedded Computing . . . . . . . . . . . 30

VPX

Interface Concept . . . . . . . . . . . . . . . . . . . 30

Red Rock Technologies, Inc. . . . . . . . . . . . . . 30

TE Connectivity . . . . . . . . . . . . . . . . . . . . 30

OpenVPX

Annapolis Micro Systems WILDSTAR™ 6XB2 6U OpenVPX FPGA Processor

This high-performance 6U board is shipping Now! • 2 Virtex UltraScale+™ FPGAs • 1 Zynq UltraScale+™ MPSoC Motherboard Controller • 2 WILD FMC+ (WFMC+™) I/O sites support 32 HSS &100 LVDS • RT3 backplane connectors deliver 100Gb per Fat Pipe • -55°C to 85°C Operating • -65°C to 105°C Storage • Optional VITA 66/67 support • Developed in alignment with SOSA™ • See our website for 3U & PCIe alternatives! www.annapmicro.com/product-category/fpga-boards-2/

www.vita-technologies.com

OpenVPX Dawn VME Products

VITA Technologiess Application Guide

Open VPX

Sponsored By:

PSC-6265

VITA 62 compliant 6U power supply for conduction cooled systems.

Dawn’s VITA 62 compliant 6U PSC-6265 can operate continuously in diverse environments over a wide range of temperatures at high power levels. The standard model is conduction to wedge lock cooled with an operating temperature range of -40° C to +85° C and a nonoperating range of -55° C to +105° C. The PSC-6265 operates continuously at a power level of 580 watts. For systems that require higher power levels, up to three supplies may be operated in parallel. Fault monitoring and control circuits protect the system from over-voltage, over-current, and over-temperature conditions.

EnsembleSeries LDS3517 3U OpenVPX blade

www.dawnvme.com/product-category/power-supplies

Open VPX

Dawn VME Products PSC-6236

Universal AC Input VITA 62 3U Power Supply Dawn VME Products PSC-6236 universal AC input VITA 62 compliant 3U power supply for air or conduction cooled OpenVPX systems. True 6 channel supply with up to 400 watts output. Mission critical wide temperature range at high power. Input 85 VAC to 264 VAC, 47 Hz to 400 Hz. Can be special ordered to support high current single channel applications. Embedded RuSH™ technology actively monitors voltage, current and temperature, and provides protective control. Ruggedized – VITA 47 compliant. Rugged, Reliable and Ready. www.dawnvme.com/product-category/power-supplies

OpenVPX

Interface Concept IC-FEP-VPX6e 6U OpenVPX UltraScale™ FPGA board with FMC+ site

The IC-FEP-VPX6e is a 6U OpenVPX front end processing board, featuring two Xilinx Virtex UltraScale FPGAs and one NXP QorIQ® TLS1046A quad 64-bit processor, for DSP intensive processing applications. The IC-FEP-VPX6e design is based on the Xilinx FPGA package B1204, offering a high scalability level to the board (Kintex® UltraScale™ KU115 standard configuration, or Virtex® UltraScale™/UltraScale+™ configurations).

Each FPGA interfaces with two DDR4 SDRAM memory banks (supporting up to 2400 MT/s transfers), two optional DDRII SRAM memory banks and SPI Mirror flash memories for local bitstreams storage and user parameters. The high-end IC-FEPVPX6e is controlled by a QorIQ® LS1046A processor. http://www.interfaceconcept.com/products/FPGA-Boards/6U-VPX/244IC-FEP-VPX6e-UltraScale-FPGA-6U-VPX-board-with-FMC-sites

www.vita-technologies.com

EnsembleSeries LDS3517 blades combine Intel’s Xeon D family of server-class processors with Xilinx’s UltraScale family of FPGA devices in a compact 3U OpenVPX form-factor. This union of contemporary commercial-item general processing and FPGA resources supported with densely packaged system memory produces a versatile, scalable building block for embedded, high performance compute applications, including on-platform AI, sensor and EW processing. Optionally enabled with embedded BuiltSECURE systems security engineering and packaged with MOTS+ technology LDS3515 compute blades support military missions anywhere.

Embedded BuiltSECURE technology: BuiltSECURE technology is proven, built-in, system-wide security across software, firmware and hardware in the domains of system security engineering (SSE), trust and cyber-hardening.

Dense, versatile processing capability: System-in-a-package (SiP) and stacked wafer fabrication technologies enable the required system memory to be miniaturized and fit neatly into this standard 3U OpenVPX module for on-platform AI processing.

Versatile mezzanine: A XMC mezzanine site supports I/O customization, making the LDS3517 exceptionally versatile for a wide variety of high bandwidth signal processing applications. Each blade is interoperable with Mercury’s other EnsembleSeries OpenVPX processing building blocks for lowrisk processing subsystem pre-integration.

Extreme packaging ruggedness: MOTS+ is an additional layer of environmental protection and ruggedness requiring the soldering of all board-level devices, regardless of their native packaging/terminations, to their respective substrates for reliability.

On-board AI processing: AI applications are characterized by their processing power and massive memory and storage requirements. The LDS3517’s Xeon D family processor is supported with a powerful FPGA and the memory required to run AI processing applications on-platform. https://www.mrcy.com/LDS3517/

VITA Technologies Application Guide Winter 2018 |

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VITA Technologiess Application Guide

PMC/XMC

VPX

Alphi Technology Corporation

Red Rock Technologies, Inc.

PCIe-Mini-DIO16/32 16 Channel RS-422/485 or 32 Channel LVTTL

VPX with Removable NVMe SSD Module

The PCIe-Mini-DIO16/32 is a PCI Express Mini board that uses an Altera Cyclone IV FPGA to provide a combination of size and I/O capability that is unique in today’s marketplace. Its 32 I/O channels can monitor or control the on/off (high/low) status of up to 16 RS 422/485 differential devices or up to 32 LVTTL channels. A separate transition module is not required.

Add removable data storage to VPX systems using NVMe SSD technology with 4x SATA transfer rates. VPX with Removable NVMe SSD Module consists of the VPX board and a removable drive module designed for frequent removal.

• Adds easily removable data storage to VPX system

Features: • Size: 30mm x 50.95mm • Operating temperature: -40° C to +85° C

• Capacities up to 16GB

• PCIe Gen 3 x4 transfer rates up to 3940 MB/S • Drive module rated for 100,000 mating cycles • -40 °C to 85 °C options • Discrete controlled Military Secure Erase options

www.alphitech.com/doc/PCIe-Mini-dio16.pdf

www.redrocktech.com

PMC/XMC

VPX

Galleon Embedded Computing

TE Connectivity MULTIGIG RT 3 Connectors

Titan sFPDP XMC

Titan sFPDP XMC is a flexible platform implementing a quad channel VITA 17.1-2003 sFPDP receive and transmit engine for high-performance image processing, SIGINT/COMINT, radar processing, software defined radio, sensor data capture, and more. The XMC has a low power FPGA, with up to four individually configurable sFPDP links, software configurable for several link speeds up to 4.25Gbaud.

Multiple boards can be synchronized. The board may be fitted with rugged front panel LC connectors or recessed rugged LC connectors for easy optical cabling in conduction cooled environments with no front panel connections. Alternatively, the highspeed serial interfaces can be routed through the P16 rear I/O for backplane communication. Linux and Windows supported. www.galleonec.com

480-483-3777

281-769-8211

MULTIGIG RT 3 connectors are the next generation, rugged, high speed backplane connector that supports data rates up to 25 Gb/s. Connectors are intermateable with legacy VPX systems and are compliant to VITA46. Draft standard VITA 46.30 is in process to document this higher speed VPX connector.

MULTIGIG RT 3 offers enhanced contacts and wafer designs to enable faster protocols and retains the same extreme ruggedness of the MULTIGIG RT 2-R family. Ideal applications for MULTIGIG RT 3 are military electronics/C4ISR, Avionics, Ground Defense, Missile Defense and Space.

www.te.com/embeddedcomputing

VPX

VPX

Interface Concept

TE Connectivity

ComEth 4590a 3U VPX 10/40 Gigabit Ethernet Layer 3 switch

NanoRF Module & Contacts

The ComEth4590a is the first and only 3U VPX 10/40 Gigabit Ethernet Layer 3 switch currently on the embedded market which has two separate and independent on-board Ethernet switch matrices – one for the Data Plane and one for the Control Plane. These two separate switch matrices or packet processors are managed by two independent dual core processors. Each matrix supports separate instances of Interface Concept Switchware network management which allows independent network configuration for features such as network optimization, monitoring and security. This high-performance Layer 3 switch can be remotely configured by the Switchware web interface, SNMP or CLI interfaces.

With twice the density of VITA 67 SMPM RF Modules, TE’s new NanoRF Modules and Contacts provide a high frequency nanominiature coax contact with modular packaging and are ideal for extreme rugged environments. Half and full-size module sizes can retain up to 12 or 18+ RF contacts, with options for customizing contact count and position. The design features a floating insert in the backplane module to pre-align RF contacts before engagement, and both radial and axial float within each contact to assure final alignment of the contacts and keeps them fully engaged for excellent RF performance under harsh environments.

http://www.interfaceconcept.com/products/Ethernet-Switches/3U-VPX/309ComEth-4590a-3U-OpenVPX-Gigabit-1010-Gigabit-Ethernet-switch

www.te.com/embeddedcomputing

30 | VITA Technologies Application Guide Winter 2018

www.vita-technologies.com

THE LATEST, MOST INNOVATIVE PRODUCTS AND TECHNOLOGY

THE RESOURCE GUIDE PROVIDES INSIGHT ON EMBEDDED TOOLS AND STRATEGIES FOR TECHNICAL SUBJECTS AND OPEN STANDARDS The Spring 2019 VITA Technologies Resource Guide provides the latest technical information and updates on VMEbus, VPX, OpenVPX, VXS, and other VITA standards to engineers, managers, and decisionmakers in the United States and internationally The Resource Guide will also highlight such key electronics-buying categories as FMC, OpenVPX, Operating Systems and Tools, PMC/XMC, VME, VPX, and VXS. Don’t miss this special jam-packed issue!

Enabling the Evolution of Technology

AMPHENOL INTRODUCES NEXT GENERATION VPX Modern demands on data, latency and security requires a new generation of interconnect product. Data rates are growing exponentially and this is driving the evolution of communications technology to meet those demands. This evolution in technology requires an advancement in the design, manufacture and test of your products.

Amphenol is uniquely positioned as the only vendor to design and supply both the VPX connector and the backplane.

This allows Amphenol to provide front-to-backend vertically integrated Interconnect support on your VPX Backplane assembly.

With our experience and expertise in the high speed market, Amphenol can be your VPX partner for generations to come.

Amphenol Next Generation VPX Backplanes

Amphenol R-VPX Evolution Module Capable of 16+Gbps.

Amphenol-BSI have been designing, assembling and testing backplanes for more than 30 years. As part of the Amphenol Corporation, we continue to invest in our technologies to ensure we remain positioned as the most extensively tooled Backplane Supplier in the industry.

Evolution is specifically designed to support the latest high speed protocols while still meeting open VPX requirements.

Meeting the performance requirements of VITA 46 & 47, Evolution is designed to be intermateable with existing VITA 46 backplane connectors and still achieve 16Gbps performance.

Our connector system is optimized for speed and is ruggedized to handle harsh environmental requirements in applications across the board.

•

Industry leading backplane technology

•

Fully automated production lines

•

Signal Integrity simulation

•

Fully customized solutions

•

Designed for future upgrade paths

•

Backwards compatible to legacy cards

•

High-speed, Next Generation Backplanes

•

Dynamic, global support

Amphenol - Your VPX Partner If your requirements are for VPX backplanes or connectors, then the Amphenol team is here to help. Our expertise and experience with VPX connectors and backplanes will help you today and also be there for you tomorrow.

Supports High Speed Protocols • PCIe Gen 3, Gen 4 & Gen 5

1Gbps

2.5Gbps

• 100GBASE-KR4 Ethernet

5Gbps

Backplanes Ron McKimm T : +1-613-612-3755 E : ron.mckimm@amphenol-tcs.com

8Gbps

• Infiniband SDR, DDR & QDR

10Gbps

Connectors Cat Brandas T : +1-607-643-5071 E : cbrandas@amphenol-aao.com

16Gbps

• Serial RapidIO 12.5 Gbaud

25Gbps

32Gbps

Backplanes Martin Walsh T : +353-41-9806971 E : martin.walsh@amphenol-tcs.com