This publication is intended as study material for wafer or die level reliability testing and electronics failure analysis.
Miniaturisation of electronics leads to new kinds of fault possibilities in microelectronics. Publication introduces test methods for ensuring wafer level reliability to support design and development of electronics. Guidance to failure analysis supports the development process with information of the root cause for failure, and how it can be prevented.
This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876362. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Finland, Austria, Belgium, Czechia, Germany, Italy, Latvia, Netherlands, Poland, Switzerland.