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CONTROLLING YIELD Model-based, closed-loop advanced process control for 0.18 to 0.13 µm technologies using in-line metrology tools

by Kevin M. Monahan, Director of Process Control Systems

the leveling of the technological playing field created by large semiW ithconductor manufacturing consortia — such as SEMATECH, the SRC,

Selete, and I300I — the remaining competitive opportunities for individual companies lie primarily in advanced circuit design and yield management.

In past years, yield management in semiconductor manufacturing has been dominated by particle and defect inspection technology to improve device yield. Largely due to the success of this inspection technology, future fabs are expected to ramp to mature yield in a matter of months and to achieve yield asymptotes above 80 percent, thereby limiting the opportunities for competitive advantage in this area. As a consequence, another component of yield (bin yield) is gaining in importance.1 Bin yield is based on parametric performance, so control of bin yield relies more on wafer metrology than on defect inspection. Thus, in this era of accelerated shrinks and the early introduction of 0.18 µm technology, yield control is driving the use of in-line metrology tools.

Accelerated shrinks and early technology introductions create a number of benefits for the semiconductor manufacturer. First, IC makers can increase density, thereby increasing 200 mm capacity and delaying costly investment in new 300 mm factories. Second, shrinks can also improve the performance of devices, such as the speed of microprocessors — allowing higher average selling prices. These commercial drivers are spurring investment in controlintensive DUV lithography equipment at a 50 percent compounded annual growth rate over the next few years.

Implications for metrology

The growth of DUV lithography is affecting the use of in-line metrology tools. Formerly, metrology tools were used in the context of standard statistical process control where an operator or engineer, using a set of well-estabSummer 1998

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When advanced process control is applied using in-line metrology tools, it is usually in the form of model-based, run-to-run process control. A wafer parameter is measured and compared to the desired value. Then, a process-specific model provides a corrected process setting to achieve the desired value for the wafer parameter. This correction is made on a run-to-run basis by changing the process recipe via the chip maker’s cell controller and Computer Integrated Manufacturing (CIM) system. For 0.18 µm technology and below, one can envision a number of APC applications, including feedback of overlay analysis and critical dimension (CD) data to DUV lithography tools, feedback of depth profilometry data to damascene etch tools, and feedback of film thickness data and uniformity analyses to CMP tools. Clearly, process equipment manufacturers that partner with full-line metrology suppliers stand to gain competitive advantage.

A closed-loop solution

Gate CD control in DUV lithography is one example. Since gate CDs predict the speed binning and average selling price of advanced microprocessors,2 they can have a profound effect on factory revenues.

Formerly, semiconductor manufacturers relied on electrical measurements of gate parameters to predict speed binning. Now, because of the long time delays associated with electrical testing, they are using 10

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DI CD Controller

Exposure Dose

Etcher

DI CD

CD SEM

FI CD Controller

Target DI CD

DICD=a x ED2 + ED + C

CD SEM

FI CD

Stepper/Track

Target FI CD

FICD=a x DICD+b

FI CD

DI CD

lished rules, decided to change the process based upon a wafer parameter measurement that went beyond process control limits. For 0.18 µm technology and beyond, a powerful trend toward advanced closed-loop control with a minimum of human intervention has been seen. The benefits of advanced process control (APC) include reduced process variation, accelerated shrinks, elimination of send-ahead wafers, fewer monitor wafers, shorter response times, reduced scrap, improved overall equipment effectiveness, lower parametric yield loss and better device performance.

Exposure Dose

DI CD

Figure 1. Closed-loop, model-based, cascade CD control with single set-point (after etch) and single control parameter (exposure dose). Such systems have been used in dedicated gate CD control loops to produce the results shown in figure 2.

high-throughput CD SEMs to provide the quick feedback required for advanced process control. The transition from conventional SPC methodology to run-to-run, model-based control, effectively integrates the CD SEM technology with the lithographic process equipment. In this scenario, metrology tools become “value-added,” where the metric for value is the increase in revenue generated by the product. In the microprocessor case, model-based gate control loops have been shown to add as much as $2 million per 1,000 wafer starts. This amount would pay for the world’s most advanced 200 mm CD SEM in less than a week.

DUV lithography tool. The strength of this design is in its simplicity; however, it provides no feedforward to etch from the post-develop CDs and no trim feedback to etch from the post-etch CDs. The trade-off is reduced system responsiveness and increased vulnerability to changes in the etch process, such as those introduced by chamber cleaning. This scheme works well for dedicated gate CD control loops, but general manufacturing requires a more comprehensive “factory-wide” solution that takes the etch cell into account.

General manufacturing puts stringent requirements on metrology response time. Electrical parametric measurements such as L-effective may arrive many hours or days after a process has gone out of control. In contrast, CD SEMs provide quick

In figure 1, a scheme to control gate CDs on a closed-loop, run-torun basis3 is shown. This approach uses post-develop inspection (DI) CDs 100 B and a process model to 90 provide feedback of Speed Bin 80 exposure dose correc70 tions as a means to 60 reduce process variation. The post-etch 50 % A inspection (FI) CDs 40 are used in the outer 30 control loop to set the 20 target CD of the inner 10 loop. This simple cascade controller has 1 2 3 4 5 only one input, the FI Figure 2. Speed binning histogram for a high-per formance microtarget CD, and one processor (A) before and (B) after run-to-run, model-based control parameter, the process control. Distribution B has been narrowed and shifted exposure dose of a into the higher performance bin without loss of yield.

Yield Management Solutions

C 40 35 30 25

APC off APC on

20 15 10 5 0 X-Field

X-Wafer

X-Lot

Lot-Lot

Figure 3. Run-to-run gate CD variation is the limiting component of the total variation. It completely dominates the cross-wafer and cross-lot components. Assuming six microprocessors per field, the actual cross-chip CD

In the previous case, APC was used to enable a process shrink by pushing down the “k-factor” of the DUV lithographic process.

Ultimately, gate CD design rules reach the limit of lithographic resolution, described by the Raleigh equation R=k λ NA

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0.18 µm Lithography Variation

3-SIGMA (nm)

feedback on a run-to-run basis, often directly after resist development or polysilicon etch. One result4 is shown in figure 2, where the gate CD distribution A was obtained using manual statistical process control, and the gate CD distribution B was obtained using run-to-run process control. In the latter case, the exposure dose of the DUV lithography tool was adjusted using a linear feedback loop. As a consequence, the CD variation for an advanced microprocessor was cut nearly in half, and the entire distribution could be shifted to a higher speed bin with no adverse effect on device yield.

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variation could be as low as 10 nm. Adding

R

bring the run-to-run CD variation down around 10 nm as well. Potentially, adding feedforward from film deposition to lithography and from lithography to etch could reduce run-to-run

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example (figure 4), in-line metrology tools easily address the metrology requirements for lot-to-lot variability, the dominant source of variation.

For the smaller components, higher bandwidth in-situ sensors may be more suitable in some cases.

However, systematic cross-field, cross-wafer and cross-lot errors can be measured to create model-based uniformity maps that are fed back to the stepper/track system on a run-torun basis. These critical applications will require the superior flexibility, accuracy, resolution, and mapping capabilities of in-line metrology tools. The only exclusive niche for in-situ metrology is high-bandwidth correction of the unmodeled error. circle RS#009

etch APC in addition to lithographic APC could

1 D. Boning and J. Chung, 1997 “Statistical metrology: Tools for understanding variation.” Future Fab International, vol. 1, issue 2, pp. 323-327.

2 D. G. Chesboro, J. W. Adkisson, L. R. Clark,

S. N. Eslinger, M. A. Faucher, S. J. Holmes, R. P. Mallette, E. J. Nowak, E. W. Sengle, S. H. Voldman, and T. W. Weeks, 1995.

“Overview of gate linewidth control in the manufacture of CMOS logic chips.” IBM J. Res. Develop., vol. 39, pp. 189-200.

CD variation to about 7 nm.

260.5

Etched Gate CD (nm)

3s = 0.6 nm, n = 9

where lambda is the exposure wavelength and NA is the numerical aperture of the optics. The value of k has been moving steadily lower from 0.8 in past years to about 0.5 in today’s 0.25 µm manufacturing lines. The reduction of k is anticipated to continue in 0.18, 0.15 and 0.13 µm generations, driven by new chemically amplified resists (CAR), off-axis illumination (OAI), optical proximity correction (OPC), phase shift masks (PSM) and advanced process control (APC).

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3 J. Sturtevant, M. Weileman, K. Green, J. Dwyer,

E. Robertson, and R. Hershey, 1998.

“Implementation of closed-loop CD and overlay controller for sub-0.25 µm patterning,” Proc. SPIE, vol. 3332.

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Si

4 D. Gerold, R. Hershey, K. McBrayer, and

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J. Sturtevant, 1997. SEMATECH AEC/APC Workshop.

Day Number

Figure 4. CD SEM long-term stability using the average of nine measurements. At 0.6 nm stability, CD SEM measurement capability meets the

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percent

precision/tolerance

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required for a 7 nm APC target over the time

Managing the trade-offs

period required for run-to-run control. The CD

For these generations, there will be trade-offs between in-line and insitu metrology, but model-based APC capability will become a requirement for both. The trade-offs arise from the time-scale and partitioning of process variation. In lithography, variability can be divided into at least four components: crossfield (~1 second), cross-wafer (~1 minute), cross-lot (~1 hour), and lotto-lot variability (~1 day). Figure 3 shows estimates of these components for a 0.18 µm process with APC enabled. As shown in our CD SEM

SEM throughput is much greater than required.

Kevin M. Monahan is director of Process Control Systems in the Metrology Group of KLA-Tencor Corporation.

Formerly, he was vice president and chief technical officer of Metrologix Incorporated, prior to its merger with KLA-Tencor in 1994.

He is also the founder of the SPIE Conference on Metrology, Inspection, and Process Control for Microlithography. He currently serves on the SIA Roadmap Coordinating Group as Metrology TWG vice-chair, on the Technical Program Committee for the 1998 IEEE Lithography Workshop and on the Technical Program Committee for ISSM ’98.

Dr. Monahan has a B.S. in Physics from the California Institute of Technology and a Ph.D. in Physics from the University of California Santa Barbara. His post-doctoral research at Stanford University was sponsored by the National Research Council.

Contact Information KLA-Tencor Corporation 160 Rio Robles, M/S H1-7100 San Jose, CA 95134

Tel 408.875.5023 Fax 408.875.6234 E-mail kevin.monahan@kla-tencor.com