GaNFast: The Power and the Quality

The Power and the Quality Robust, high-performance fast charging and power conversion with GaN power ICs Authors: Tom Ribarich | Anthony Schiro Foreword by Dan Kinzer

Contents

03 Foreword 04 Navitas Quality & Reliability Series Article #1 (Intro) 10 GaN Reliability: Beyond Performance and Efficiency 15

Application-Specific Reliability Methods Drive Successful Navitas GaNFastTM IC Field Results in High-Volume Production

21 Unlocking GaN’s Full Potential 26 Who Needs Avalanche?

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GaNSenseTM Power ICs Integrate Fast, Autonomous, Precise Protection Circuits for Ultimate System Robustness

Foreword

By Dan Kinzer, Co-Founder & CTO/COO, Navitas Semiconductor

Addressing our insatiable demand for energy in an environmentally sustainable manner requires that we Electrify Our WorldTM in the most efficient ways possible. This means both electrifying technologies that have previously relied on fossil fuels and dramatically improving the energy performance of existing electronics ranging from consumer products to industrial motor drives and renewable energy converters to electric vehicles (EVs).

Fundamental to making this happen are gallium nitride (GaN) semiconductors. These wide bandgap (WBG) devices deliver more efficient and faster switching than conventional silicon (Si) devices in existing designs and can be deployed in applications where silicon as a power conversion platform has hit its physical limits.

But efficiency and performance are only one part of the story. It is also important that engineers have the confidence that there is no risk - that GaN can offer the same or better quality, robustness and reliability than conventional silicon ICs. Which is where this guide comes in.

Collating a number of articles written by Navitas Semiconductor’s VP Quality and the company’s Senior Director of Strategic Marketing, the following pages explain how delivering quality and reliability – alongside industry-leading performance and efficiency – comes down to a combination of factors. Factors such as choice of fundamental operation mode; optimized monolithic integration that combines GaN power FET, gate drive circuit, gate voltage regulator and built-in protection; and a robust, application-specific approach to technology validation, product validation and lifetime modelling.

Finally, it should also be noted that delivering consistent performance, quality and reliability at scale is also a matter of company philosophy. Manufacturers need to challenge themselves to be innovative and curious when it comes to risk identification and mitigation. As the articles here show, this can mean everything from inventing new test methodologies to carefully planning product evolutions that are based on experience and real-life reliability data.

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Navitas Quality & Reliability Series Article #1 (Intro) Electrifying Our World™: The Navitas Quality Journey Delivering GaN Quality and Reliability at Scale Across a Growing Range of Powers and Applications

“Consistently delivering reliable GaN technology at scale and ever-increasing power ratings requires an application-focused, design for reliability approach combined with quality suppliers, comprehensive testing, continuous and exhaustive validation, and strong customer collaboration and co-development.”

Anthony Schiro VP Quality

It is only natural that when adopting any new technology that customers will seek assurance regarding quality and reliability. In delivering this assurance, how a company is built, the experience of its people, its culture and values are just as important as how the technology is designed, manufactured, tested and deployed.

Certainly, these factors have all played a key role in driving the quality and reliability that Navitas customers have come to expect as Navitas has moved gallium nitride into the mainstream. Here, and in subsequent articles, we will recount the journey to achieving our industry-leading quality and reliability.

The starting point for our journey is experience. Take the leadership team at Navitas, for example. This team has over 300 years of combined power semiconductor experience, had amassed more than 200 industry patents and was responsible for at least twenty generations of power semiconductors before founding Navitas. Since then, Navitas has an additional 130 patents granted or pending.

This experience has been fundamental to building a company that is at the forefront of a second power revolution - helping customers address design and sustainability goals by migrating from slower, legacy silicon semiconductors to faster, more efficient gallium nitride (GaN)-based solutions.

Figure 1: Over 130 patents and significant company secrets give Navitas a multi-year lead in gallium nitride

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Figure 2: Navitas GaN technology is at the forefront of the second power revolution

From this standpoint, the first step on the quality journey is understanding how to use a new technology to define products that are low risk to the customer. This means designing for quality and reliability from the outset and, in the case of Navitas, maximizing levels of integration to minimize potential points of failure at a product level and at the system level. Such quality-oriented design clearly demands technology expertise and a full understanding of the requirements of the target applications.

The next step is internal validation of the technologies and products through qualification, test-to-failure and lifetime analysis techniques, after which it is possible to partner with customers to demonstrate the disruptive performance and low risk. Only when all this is done can the ramp-up to high-volume production begin. Then, once product quality is proven in one market, it becomes possible to use that benchmark reliability as the basis for expanding into other application areas.

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The Navitas Quality Philosophy The Navitas quality philosophy is built on six fundamental elements:

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Exceed customer expectations by defining products with quality and reliability designed in

Collaborate with customers to co-develop quality-optimized system solutions

Partner with key suppliers to jointly develop processes that ensure quality and reliability

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Develop critical and proprietary testing techniques that are optimized for the new technology and target applications

Continuous and exhaustive qualification, validation and monitoring with a constant risk identification and mitigation focus

Demonstrate benchmark reliability customer by customer, application by application and market by market

Figure 3: Six key elements of the Navitas quality philosophy

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Delivering quality and reliability at scale demands that companies challenge themselves to be both innovative and curious when it comes to risk identification and mitigation. This means thinking of quality as more than simply following a standard.

For example, at Navitas, developing a robust process control plan and the effective use of design and process failure-mode and effects analysis (FMEA) is not about just using or following the quality tool or quality standard. It is about capturing risks to product performance or product variation in order to ensure we provide the best possible product for the customer and reduce the customer’s risk of implementing a brand-new technology. This is particularly true when it comes to newer disruptive technologies such as GaN, since legacy standards are unlikely to have been designed with the capabilities of these older technologies in mind.

In addition to looking at quality and reliability at a device level, it is also important to consider the overall customer problem that needs to be solved and how the devices will work in the context of the final application. It is only with such an approach that customers can have the confidence that replacing legacy silicon with GaN will not compromise – and can actually improve – quality and reliability.

That’s why Navitas not only puts effort into developing advanced GaN technologies that are inherently more reliable than legacy silicon but also considers ‘the bigger picture’ - how to address the challenges that customers face around improving performance and saving power in their applications.

Because addressing these challenges not only plays a part in realizing optimized designs but ensures better use of global energy resources while minimizing the impact of greenhouse gases on the planet. This is only possible by becoming experts at the system level and then using that expertise to define and drive the design of revolutionary products.

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Gaining Customer Trust by Minimizing Risk From the outset, Navitas made some critical decisions that determined the company’s ability to gain trust and provide peace of mind as customers looked to transition from a 40-year old incumbent technology that could no longer meet performance, efficiency and size goals. These ranged from choice of technology and manufacturing partners to an approach to product design that would ensure a flawless launch into the market.

Under-pinning all of these decisions has been a focus on how to reduce risk, how to ensure a robust product for the customer and how to continuously improve through risk identification and mitigation.

In recognition that existing test methodologies were not designed with the superior performance of GaN in mind, for example, it was seen as important to combine industry-standard validation testing with proprietary product and reliability methods focused on high-frequency switching and testing that mimics the target applications. This helped to eliminate the risk of adopting the new technology by making it possible to push the envelope on performance while ensuring quality and reliability levels equal to or greater than those associated with legacy silicon in those applications.

This advanced later testing became part of a new industry-wide standard when Navitas were founder members of the JEDEC JC70.1 GaN standards committee.

The proactive diligence and execution of engineering and operations teams has been an absolutely-essential element of successfully ramping from initial launch to high-volume production, as was a company culture built around quality as a fundamental. Such a ‘quality culture’ is about who you are, what you believe in and how you act. It takes experience, expertise and determined action to seek out risks and address them.

In the case of Navitas, this means not only proving the quality of the products, but the quality of each new aspect of the high-frequency, high-density power supply ecosystem in which those products are deployed.

A key aspect of the approach involves collaborating with customer engineering and manufacturing teams to challenge the status quo, jointly agree system level goals (often beyond the industry standards) and work together to exceed minimum requirements prior to launching into mass production.

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A Holistic Approach to Quality and Reliability To be at the forefront of the second revolution in power semiconductors requires a holistic approach to pushing current technology boundaries while launching every new product to market safely. The Navitas philosophy is to build customer confidence step-by-step by carefully planning product evolutions that are based on experience and real-life reliability data. As the world’s leading GaN power IC company, Navitas has an unrivalled dataset based on more than 25 million shipped devices and over 68 billion field use hours as of August 2021 (for up-to-date quality metrics please click here). This dataset provides customers across all markets with proof of the effectiveness of the company’s approach to quality and reliability. It also provides the confidence to take the next steps of the GaN journey.

Having delivered proven and reliable solutions at the lower end of the power spectrum (from 45W, then 65W, then 120W, then 240W, etc.), Navitas and its partners can be confident of pushing to the next power levels. As a result, whether it’s enterprise servers, electric vehicles or renewable energy, applications in the highest power sectors will benefit from the supply, at scale, of high-performance, ultra-efficient, reliable GaN ICs.

Figure 4: Navitas has shipped over 30 million GaNFast power ICs and amassed more than 90 billion hours of field data

A few charts and graphs are not enough to explain the premium that Navitas places on reliability and how quality is baked into the very core of the company and the values it holds. But the results of this culture are clear to see in the journey from the company’s creation in 2014 to a position where, as of August 2021, over 25 million Navitas GaNFast power ICs have been shipped with no GaN defects reported in the field.

Stay Tuned for More on Navitas Quality and Reliability

Useful links: Navitas up-to-date quality data What is gallium nitride?

In the coming weeks we’ll publish more articles on the Navitas approach to quality and reliability with topics that cover the benefits of integration, critical design and supplier choices, qualifying a revolutionary technology, maintaining a risk reduction focus through a steep production ramp and the importance of customer engagement and partnership.

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GaN Reliability: Beyond Performance and Efficiency Delivering Optimized Reliability Through Integration Anthony Schiro, VP Quality, Navitas Semiconductor

Figure 1: Integrated GaNFast Power IC

Designers are seeking alternatives to silicon to meet the performance and efficiency challenges of their next generation technologies. In addition, OEMs are looking for ways to reduce their carbon footprint by reducing materials and energy use related to their products. Gallium nitride (GaN) is rapidly becoming the semiconductor of choice as its physical properties and inherent voltage handling capabilities enable companies to address both these challenges. What’s more, in addition to performance and efficiency improvements, GaN can also make a significant contribution to enhancing system reliability.

Design Choices for Reliability The first thing to note is that, as a wide bandgap (WBG) material GaN is fundamentally more reliable than silicon.

Bandgap is the energy needed to free an electron from its orbit around the nucleus and, at 3.4 eV, the bandgap of gallium nitride is over three times that of silicon. As bandgap determines the electric field that a material can withstand, GaN’s wider bandgap allows it to accommodate higher breakdown voltages than silicon. Not only is GaN ten times more capable than silicon of supporting higher voltages, but it also offers better thermal stability at higher temperatures. While GaN has a slightly lower thermal conductivity than silicon, this is more than offset by the significant increases in efficiency - increases that mean that at similar voltages, GaN runs cooler than silicon, reducing thermal loads and reliability issues associated with heat.

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In terms of GaN IC design there are a number of factors that will contribute to the reliability of a given technology. The first is whether the GaN IC operates in enhancement mode or depletion mode.

Conventional GaN HEMT (high electron mobility transistor) technology, for example, typically deploys ‘normally-on’ depletion mode (dMode). This requires a negative gate voltage (VGS) to turn off, which is not a practical solution for offline applications as it would mean an immediate short-circuit across the AC mains. To mitigate this unwanted characteristic a second low-voltage ‘cascode‘ silicon FET is used to turn the GaN power device on and off. This not only compromises performance (the performance of the silicon FET is inferior to that of the GaN switch) but impacts reliability as a result of high parasitic inductance, a tendency for oscillation and internal overvoltage stress due to AC and DC mismatch of the GaN and silicon devices - and the need to add passive components to mitigate these effects.

Enhancement mode (eMode) devices, on the other hand, are naturally ‘normally off’ and behave in a safe, familiar way for power design engineers in that a current flows when a positive voltage is applied to the gate. However, if the voltage is too low the GaN FET is not fully turned on, resulting in higher resistance and higher losses, which impacts reliability through increased heat. If too high, the gate structure can be damaged due to avalanche breakdown and subsequent overheating at localized spots at the gate metal pGaN schottky junction. That’s why with ‘discrete 3-terminal’ (gate, drain, source) GaN FETs, complicated structures are typically required to control the GaN gate voltage safely. Again, these add complexity and multiple points of potential failure, not to mention slowing down the switching frequency of the application and, therefore, diluting the GaN performance benefits.

Figure 2: Fewer components translates to fewer potential points of failure

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Monolithic Integration In developing its own family of products Navitas has taken an advanced approach to deliver products that both simplify circuit design and improve reliability. Using lateral 650 V eMode GaN, the company has a proprietary AllGaN™ process design kit (PDK) that allows the monolithic integration of GaN FET, GaN analog (drive) and GaN logic into a single GaN Power IC as shown in figure 1.

In addition to specifying the IC design elements, the Navitas GaN Power IC PDK also includes a proprietary GaN power FET design. This design, coupled with Navitas’ unique GaN power production test methods and extensive reliability characterization and qualification processes delivers a robust voltage withstand capability that enables power ICs with an 800 V transient rating and continuous ratings of up to 700 V.

As well as outperforming both legacy silicon semiconductors and discrete GaN devices, these ICs offer much better system reliability than either of these technologies thanks to:

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Reduced electrical stress: Fewer spikes and less overshoot and ringing translates to longer life components

Fewer components and interconnects: Fewer components, as illustrated in Figure 2, reduces the number of potential failure points

Increased manufacturing automation: Elimination of through-hole devices, heatsinks and wire-wound magnetics all eliminate manual labor and risk of defects or excessive manufacturing variation.

The benefits of this integration can be illustrated by considering the respective waveforms of GaN discretes vs GaN power ICs as shown in Figure 3.

Figure 3: Waveforms of GaN discretes and integrated GaN ICs

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Recently, Navitas has further increased the level of integration of its GaNFast ICs with the launch of a third generation of devices that integrate real-time, accurate and fast sensing of system parameters including current and temperature and enable a patent-pending loss-less current-sensing capability.

GaNSense™ continues the evolution from legacy silicon to fully integrated GaN (Figure 4), can improve energy savings by a further 10% compared to prior generations. minimizes external component count and shrinks system footprints. And with GaNSense, if the GaN IC identifies a potentially dangerous system condition it is designed to transition rapidly to a cycleby-cycle sleep-state, for example, with a dangerous system short-circuit condition, the GaNSense chip can go from detect to protect in only 30 ns. This enhances system reliability by protecting both the device and the surrounding system, and has been adopted by Lenovo, Xiaomi, vivo and others. Finally, thanks to the industry’s tightest current-measurement accuracy and response time, GaNSense technology reduces dangerous overcurrent spikes and time in the ‘danger zone’ by 50% compared to previous best-in-class solutions.

Fabrication and Packaging The approach to semiconductor fabrication and packaging also plays an important role in device quality and reliability.

Navitas GaN power ICs are fabricated by TSMC, starting with a standard silicon wafer as an inert mechanical substrate. A very thin layer of GaN is then epitaxially grown onto the top surface. From there, standard CMOS processing techniques are followed including masking, etching, diffusion and sputtering to create a completed wafer containing thousands of GaN chips. While data-processing silicon chips require complex, extremely-expensive, sub-10 nm processing equipment, GaN-onSi production uses cost-effective, proven and widely-available 350 nm equipment ensuring maximum yields and repeatable quality and reliability.

Once fabricated, the wafers are accurately sawn into individual dice (chips) and packaged into frequency-optimized QFN packages. Navitas has been able to adapt industry-standard packaging processes to make patented high-voltage and high-power packages for GaN that are optimized for reliability.

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Beyond Technology – Other Choices for Quality and Reliability Beyond the technology there are other choices that device manufacturers can make to deliver optimum quality and reliability in real-world environments. One such choice is to develop technologies that focus on the application-specific needs of a given market rather creating a ‘one-size-fits-all’ solution. This approach gives customers in those markets the confidence that replacing legacy silicon with GaN will not compromise – and can actually improve – reliability.

Figure 4: GaNFast power ICs with GaNSense technology further enhance reliability to continue the evolution from legacy silicon to fully-integrated GaN

Take, for example, the mobile charger market on which Navitas focused with its first products. This sector was chosen as the company’s primary target because the value proposition of ‘portability’ is simple and compelling and an ideal fit for GaN. To develop the perfect GaN ICs for fast chargers and adapters Navitas engineers worked hard to understand the specific requirements of, first, single-port applications and subsequently multi-port applications that integrate multiple chargers into a single compact device.

Directing engineering efforts to address applicationspecific requirements has resulted in GaN power ICs that are optimized for ultra-efficient, high-power-density fast charging and the shipment of over 35 million GaN power ICs to this sector. GaNFast ICs can be found in over 170 tier-1

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and aftermarket mass production chargers). And, thanks to the focus on optimizing performance, quality and reliability for the application, there has not been one single reported GaN-related field failure. For up-to-date quality metrics please click here.

Finally, one big advantage of shipping high volumes of products is an unrivalled dataset that provides solid reliability data. This gives companies in new markets the confidence to take the next steps of the GaN journey. That means high-quality, high-performance reliable solutions for designs in the 2kW to 20kW power range, extending GaN’s performance, efficiency and reliability benefits to applications including data centers, solar inverters and electric vehicles.

Application-Specific Reliability Methods Drive Successful Navitas IC Field Results in High-Volume Production Successful implementation of a new semiconductor technology requires a robust, application-specific approach to technology validation, product validation and lifetime modeling.

Anthony Schiro

Llew Vaughan-Edmunds

Quality is paramount when introducing an innovative technology and device family into mass production. Establishing robust design rules and understanding intrinsic failure modes is key to exceeding customer performance and reliability expectations in high-volume manufacturing. Since Navitas was formed in 2014, its GaNFast™ power ICs are now proven in the field for the highest reliability and performance, with over 210 billion field hours, over 50,000,000 units shipped, and zero GaN-related field failures observed1. Additionally, Navitas offers a 20-year limited warranty for its GaNFast technology – 10x longer than typical silicon, SiC or discrete GaN power semiconductors. This success comes from several key factors in Navitas’ strategic leadership in GaN power.

Most of today’s power semiconductors are based on silicon, which originates from a single crystal ingot created using a CZ (Czochralski), MCZ (magnetic field applied Czochralski), or Float Zone (FZ) crystal-growth process. This monocrystalline lattice is then doped with boron or phosphorous to create an n-type or p-type semiconductor. GaN is different. It is a compound semiconductor that combines two elements (gallium and nitrogen), from groups III and V in the periodic table, forming a wide bandgap semiconductor. Creating a GaN crystal involves a completely different process than silicon, typically with a metal organic chemical vapor deposition (MOCVD) growth process.

Compound semiconductors behave differently to silicon and, therefore, have different physics-of-failure drivers in reliability. In 2016, the first working group of industry experts formed the GaN Standards for Power Electronic Conversion (GaNSPEC) Devices Working Group (DWG), to develop specific and credible standards for GaN power devices. Navitas was a key founding member and has collaborated to introduce guidelines for test methods, datasheet ratings and reliability testing. This was the basis of JEDEC’s subsequent JC-70 committee: JC-70 Wide Bandgap Power Electronic Conversion Semiconductors. The key outcome of the reliability testing committee has been broad agreement on the need for switching based stress testing in the reliability regime.

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Data as of May 2022.

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Typical Si-Based Qual Plan New GaN standards needed Tj

Courtesy: Stephanie Watts Butler (Texas Instruments) and Tim MsDonald (Infineon) “From GANSPEC DWG to JEDEC JC-70.1: An update on industry qualification standards for Gallium Nitride power conversion devices”

Figure 1: Navitas was a key founding member of GaNSPEC and JEDEC 70.1, focused on standards for GaN power devices

Navitas’ Approach to Reliability The Navitas approach to reliability is multi-faceted with an extensive quality and reliability methodology to demonstrate GaN as more reliable than its Si predecessor. Technology, design and manufacturing process choices are paramount to designing in quality and reliability from the start. Reliable products require robust design rules and characterization.

Navitas’ AllGaN™ proprietary process design kit (PDK) is the result of years of studying, improving, and optimizing Power FET and IC device performance and reliability. Each element is evaluated independently and screened for defects and robust, stable parametrics.

Application-specific testing is critical to understand how the device performs in target applications under various conditions. The application-specific reliability approach is essential in new technology assessment since it is common

to see high field failure rates in new technologies that simply retain legacy reliability test regimes such as hightemperature reverse bias (HTRB) and high-temperature gate bias (HTGB) for discrete power semiconductors. Combining application-specific testing with a test-to-failure approach is also important to identify key technology limitations and failure modes to drive improvements prior to technology and product release. Devices are assessed at expected and significantly accelerated application voltages, temperatures, and frequencies to develop acceleration factors and lifetime models in addition to standard reliability validation. While other GaN companies have experienced field reliability issues, Navitas’ application-specific test approach has proven successful with no field reliability concerns found in more than 50 million GaNFast ICs shipped in over four years since production release.

Figure 2: Many factors ensure Navitas GaN reliability

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Dynamic Testing GaN power switches are high-electron-mobility transistors (HEMTs) with exceptionally low capacitances. Because they switch extremely quickly, dynamic testing is critical. JEDEC provides general guidelines for switching reliability evaluation procedures for GaN devices (JEP180), including dynamic high-temperature operating life (DTHOL), based on Navitas’ original research. Dynamic testing is critical to understand the true reliability in the application. Navitas exceeds the guidelines for dynamic testing with proprietary in-house-designed test methods to ensure the highest quality and reliability covering soft switching, hard switching, integrated driver switching, and surge voltage testing. Additional testing is conducted under dynamic application conditions, which provides better and more confident reliability prediction, as well as a broader system reliability than discrete component evaluation.

Figure 3: Navitas proprietary reliability methods ensure higher quality and more confidence in reliability prediction modelling

Application-Specific Testing One example of Navitas’ application testing is the high-temperature operating life - zero-voltage switching (HTOL-ZVS) test.

This test has been used while targeting the mobile charging market and is relevant for many soft switching applications.

Understanding each use profile at the system - and device - level identifies the key variables stressing the device and which reliability tests and test conditions are the most important.

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Figure 4: Application profiles for an active clamp flyback (ACF) charger with different stresses on the power device

During burst profile (no load), the stresses seen on the GaN FET are relatively low. The operating junction temperature is low, switching frequency is low, and the current is minimal.

However, the blocking voltage is high. From a reliability standpoint, HTRB testing is the key indicator to identify relevant stresses in this condition. During a full-load profile,

the GaN FET exhibits high stresses. The junction temperature is at its highest, switching frequency is at maximum with high and fast transitions of voltage and currents. The HTOLZVS test provides an accurate test bench to study and validate device reliability over time in this condition.

Figure 5: ZVS application profile (FET). ‘Soft switching’ or ZVS (zero voltage Switching) represents an application-relevant stress on the power FET.

Lifetime Modelling Lifetime analysis is conducted at both the device and system level to determine the end-of-life (EOL) estimation based on the studied and expected failure mechanism. Accelerated HTOL-ZVS and HTRB tests are used to simulate system

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operating conditions and match all elements of application profiles. Testing is conducted to statistical sample sizes with test-to-failure data and varied conditions, to develop lifetime and acceleration models.

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Figure 6: Accelerated test-to-failure determines reliability acceleration factors for voltage and temperature.

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𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 (𝐴𝐴𝐹𝐹𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 ) = ( ) 𝑉𝑉𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎

𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 (𝐴𝐴𝐹𝐹𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 ) = 𝐴𝐴𝐹𝐹𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 × 𝐴𝐴𝐹𝐹𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 𝑒𝑒𝑒𝑒𝑒𝑒𝑖𝑖𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 𝑖𝑖𝑖𝑖 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 = 𝐴𝐴𝐹𝐹𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 × 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑡𝑡𝑡𝑡 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑖𝑖𝑖𝑖 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 (𝑇𝑇𝑇𝑇𝐹𝐹𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 )

Figure 7: Lifetime estimation in charger application at full-power profile far exceeds expected 3-5 year lifetime requirement

Production Monitoring Navitas has constantly monitored all its high-volume production over the last four years with both standard test methods and application-specific test methods. This testing covers over 70 different fab lots and over 7000 parts-ontest, resulting in the highest possible confidence in the

consistent reliability of GaNFast ICs. The results demonstrate a failures-in-time (FIT) rate - where 1 FIT equals one device failure in every 1 billion hours - that is six times better than silicon’s typically accepted value, positioning GaNFast ICs as a superior quality to silicon equivalents.

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Figure 8: Reliability monitoring of production material throughout three years of production tests - 7,276 units on high-frequency, soft-switching application-focused stress testing from over 70 fab lots.

Summary Navitas’ commitment to new and innovative methods to validate the reliability of GaNFast ICs has paid off with field performance aligned to internal reliability data. With over 50,000,000 units shipped, 210 billion field hours, and zero GaN-related field failures, GaNFast power ICs are a proven technology in high-volume production.

Navitas’ focus on validating all the building blocks of the technology, ensuring robust design and materials choices

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and choosing an application-specific reliability validation regime have led to an excellent market introduction. A strong commitment to ongoing reliability monitoring in high-volume production provides a closed-loop approach of continuous product and technology improvements that feeds back into the design and development process, as the company continues to work on technology advancements, new technologies and address new, high-power markets to disrupt the power semiconductor world.

Unlocking GaN’s Full Potential ICs simplify designs, improve performance and boost robustness and reliability Tom Ribarich, Sr. Director Strategic Marketing, Navitas Semiconductor

Introduction GaNFastTM Power ICs have enabled 10x higher switching frequencies versus Silicon and achieved unprecedented power densities (1.3 W/cc) due to their integrated and regulated gate drive technology. Discrete GaN FETs continue to have slow adoption due to ruggedness & reliability concerns, plus difficulties with designing robust gate drive circuits. In addition to very low ESD tolerance, the exposed gate of the discrete GaN FET has a high susceptibility to device, package and PCB parasitics. These ‘hidden’ parasitics are the well-known enemy of fast switching and can cause transient ringing, glitching and destruction. Unregulated on- and off-state gate voltage levels are also concerning due to wide voltage variations that can cause poor reliability and drastically reduce lifetime. As a result, discrete GaN FET solutions must add large filter circuits that prevent high frequency operation and prohibit the benefits of GaN. With GaNFastTM Power ICs, the GaN power FET, gate drive circuit and gate voltage regulator are monolithically-integrated on the same IC chip. These circuit blocks provide excellent immunity against switching noise and parasitics, eliminates gate voltage variations, and delivers a rugged and robust solution that is easy-to-use and unlocks high frequency operation for next generation power-supply designs. This article exposes these ‘hidden’ parasitics, explains why they are concerning, and compares the robustness and reliability of exposed gate discrete GaN approaches versus GaNFastTM integrated gate drive solutions during different switching conditions.

Hidden Resonant Parasitic Network For enhancement-mode (eMode, normally off) discrete GaN FETs, a high level of sensitivity exists at the gate due to a low threshold voltage and a narrow gate voltage operating range.

To make things worse, there is a ‘hidden’ resonant network of parasitic resistors, inductors and capacitors around the FET formed by the PCB, GaN FET package, and GaN device itself.

An example of this parasitic resonant network consists of a discrete GaN FET mounted on a standard FR4 PCB (Figure 1a). This ‘deceptively simple’ circuit seems like it will easily

work for generating the necessary square-wave gate voltage.

A more detailed ‘extracted’ circuit including parasitics reveals a much more complex network surrounding the discrete GaN FET. PCB material, PCB copper traces, GaN FET package leadframe and wirebonds, and external component parasitics all form parasitic resistors, inductors and capacitors at the gate, drain and source. The intrinsic capacitors of the GaN FET device itself (CGS, CGD, CDS) also form part of the parasitic network.

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Figure 1(a): Discrete GaN FET on PCB and ‘hidden’ parasitic resonant network with switching current paths

Figure 1(b) Complex filter and Zener gate circuit, and, gate voltage ringing and glitching waveforms

This parasitic resonant network becomes excited during each dV/dt switching transition of the drain voltage causing currents to flow around various parasitic resonant circuit loops. These resonant currents (Figure 1a) will cause excessive voltage spikes and ringing to occur at different parasitic circuit nodes, including the gate of the GaN FET. During turn-on, a negative dV/dt occurs at the drain node causing current to flow into the gate node and through CGD to the drain. During turn-off, a positive dV/dt occurs at the drain node causing current to flow through CGD and out of the gate node. The external gate drive signal itself will also excite the gate and source loop parasitics. All of these switching conditions will cause voltage spikes and ringing (Figure 1b) at the gate that will turn the discrete GaN FET on or off unexpectedly (glitching) and can cause poor reliability, reduced lifetime or destruction of the GaN FET. These constraints make these devices very susceptible to high-frequency and high dv/dt noise from the surrounding switched-mode converter circuit. To mitigate these problems,

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external components are placed at the gate that include a gate capacitor to filter the voltage spikes, a series capacitor and Zener diodes to generate positive and negative gate voltage levels, and additional resistors to help dampen the gate ringing induced by the gate loop inductance (Figure 1b).

Adding external components will not completely eliminate these problems due to component tolerances, temperature variation, and internal package parasitics, so the internal gate of the device can still have spikes and ringing even if the external gate pin waveform looks clean. Also, the gate is still exposed on the PCB making it always susceptible to external voltage surges and transients, or dV/dt occurring elsewhere in the circuit, creating high risk for field failures.

Dealing with all these problems, while trying to increase switching frequency and increase power density, can be a major roadblock to bringing a product out of the lab, into production, and into the field. A simpler and more reliable solution is needed without adding additional design difficulties or robustness concerns.

Integrate the Gate It is well known that GaN offers the ability to integrate additional circuits monolithically on the same IC as the power device, so it makes good sense to include the gate drive circuitry in order to eliminate these external gate drive challenges. GaNFastTM Power ICs integrate the GaN power FET together with the gate driver, the gate voltage regulator, and voltage reference (Figure 2). During turn-on, current flowing through CGD due to the negative dV/ dt at the drain no longer flows through the gate loop as it does with external gate drive circuits and exposed gates. Instead, the current flows from gate drive supply voltage (VDD), through the pull-up transistor of the gate driver, and through CGD to the drain.

During turn-off, current flowing through CGD due to the positive dV/dt at the drain flows through the pull-down transistor of the gate driver and then to the source. The sink and source currents are supplied on-chip directly from the gate drive supply voltage (VDD), not from the external gate driver as with discrete GaN FETs. The integrate gate drive circuit bypasses the external gate drive loop completely and eliminates gate voltage spikes and ringing.

The gate voltage is now decoupled from the parasitic resonant network and has well-controlled on and off voltage levels that are unaffected by PCB and package parasitics, component tolerances, temperature variations, and external surge or burst transient conditions. GaNFastTM Power ICs also include programmable dV/ dt control and a wide-range supply voltage input (VCC) that makes them highly flexible and compatible with many popular power supply controllers on the market.

(a) GaNFastTM technology highlights

b) Switching waveforms (Boost CCM, Fsw = 400kHz) Figure 2: GaNFastTM Power IC with integrated gate, no gate loop parasitics, and no ringing or glitching

Technology The latest Navitas GaNFastTM Power IC product family now includes GaNSenseTM technology. GaNSenseTM technology strengthens immunity against parasitics, voltage spikes and ringing even further by integrating loss-less current sensing. By integrating the current sensing function into the IC (Figure 3), the external current-sensing resistors, typically placed between the discrete GaN FET Source and PGND, are now eliminated. This eliminates the parasitic inductance typically formed by the PCB trace connecting the Source to the external current sensing resistor, and the current sensing resistor itself, that can also cause gate voltage spikes and

ringing with discrete GaN FETs. This gives further decoupling of parasitics from the GaNFastTM Power IC resulting in even more robust and reliable switching performance without the need for additional filter components or bead inductors to suppress ringing and slow down the switching frequency. Removing the external current sensing resistors also increases system efficiency by +0.5% and removes a PCB hotspot (typically > 85C). GaNSenseTM technology also includes additional protection features such as over-current protection and over-temperature protection, making it the most robust, reliable and efficient solution available today.

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(a) GaNSenseTM technology highlights

b) No ringing or glitching and clean current sensing waveforms (Boost CCM, Fsw = 200kHz)

Figure 3: GaNSenseTM technology integrates loss-less current sensing and eliminates source loop parasitics

Avoid the Danger Zones!

The GaN FET gate voltage levels (transient and continuous) during each on and off period are also critical for proper robustness and reliability. During the on-time period, the ‘on’ gate voltage level must stay above a minimum value (6V) to prevent RDSON from increasing, and, must stay below a maximum value (7V) to prevent accelerated lifetime degradation or destruction of the gate. During the off-time period, the ‘off’ gate voltage level (GND) must stay a safe margin away from the gate threshold level (1V) to prevent false turn-on and must not go below a maximum negative voltage rating to prevent destruction (-20V). To avoid these danger zones (Figure 4), the gate voltage levels must be well controlled at all times and should not have excessive

variation over tolerances and temperature. External gate drive components used to control the gate voltage of discrete GaN FETs will still exhibit voltage spikes and will vary with temperature. Both plateau or transient gate voltage levels in the upper danger zone area will have a dramatic effect on reliability and will cause the lifetime of the device to degrade rapidly (as can be seen by the logarithmic scale of the y-axis for time-to-fail, Figure 4). The integrated voltage regulator of the GaNFastTM Power IC ensures that the voltage levels always stay within a safe range (6 to 7V), and the integrated gate driver prevents gate voltage spikes from entering these danger zones resulting in excellent reliability and lifetime.

Figure 4: Gate voltage danger zones and gate votage vs lifetime graph

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Conclusion GaNFastTM Power ICs, with integrated drive, control and protection, enable the design of next generation high-density power converters without the difficulties associated with high-frequency switching environments, ‘hidden’ parasitic networks, and gate drive ringing and glitching. The parasitic gate and source loops have been completely eliminated to prevent gate voltage spikes, and the gate voltage levels are well-controlled in order to achieve excellent reliability and lifetime standards. Integration of loss-less current sensing increases system efficiency and eliminates hot spots, and integrated protection features provide fast and autonomous

immunity against over-current and over-temperature fault conditions. Frequencies are being pushed higher in order to increase power density so there is very little switching time available for slowing down and filtering the gate against voltage spikes. The exposed gate will always have a risk due to transients coupling into the parasitic network through some unforeseen circuit path. ESD can also be a big concern for discrete eMode GaN FETs. 40 million parts shipped without field failure give evidence that it is best to integrate the gate drive, increase robustness and reliability, and go GaNFastTM!

Reference 1) GaNFast NV6123, NV6125, NV6127 datasheets, Navitas Semiconductor, 2019 2) GaNFast NV613x/NV615x Power ICs with GaNSense Technology datasheets, Navitas Semiconductor, 2021

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Who Needs Avalanche?

Power ICs maximize transient voltage ratings and boost circuit ruggedness Tom Ribarich, Sr. Director Strategic Marketing, Navitas Semiconductor

Introduction Traditional Silicon high voltage power MOSFETs have maximum voltage ratings that include maximum allowable avalanche energy levels. Avalanche breakdown limits the robustness and reliability of the power MOSFET due to the rapid and uncontrolled increase in current and the absorption of the transient or surge energy by the switch itself.

GaNFast Power ICs do not have this avalanche breakdown effect so they can withstand higher transient voltage spikes and ride-through transient conditions without absorbing any of the surge energy. This article explains the avalanche effect in silicon, how GaNFast Power ICs high blocking voltage behavior works, and compares VDSmax ratings for Silicon, GaN IC, and discrete GaN technologies for continuous and transient conditions.

Avalanche! Look Out Below!

The Avalanche effect is exactly as it sounds. Just like a small snowslide can trigger a chain reaction of collisions causing massive amounts of snow to flow rapidly down a mountain, avalanche in a MOSFET occurs when the drain voltage exceeds the maximum breakdown voltage limit (BVDSS). The high electric field accelerates carriers in the device that causes a chain reaction of collisions of carriers with atoms. This uncontrolled chain reaction causes the current flowing through the device to multiply suddenly. The resulting high current causes a rapid temperature rise within the silicon and ultimately leads to the destruction of the silicon device. This is a well-known and well-characterized weakness of silicon MOSFETs and has resulted in a maximum avalanche energy rating (typically in millijoules) that the device can withstand when its drain-source voltage exceeds the BVDSS limit. This rating is for a single-event only and it is encouraged by silicon MOSFET manufacturers to avoid this condition completely by using external methods such as snubbers and varistors to limit the voltage below the breakdown limit.

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Figure 1: Silicon MOSFET avalanche breakdown effect

The amount of avalanche energy depends on the amplitude and duration of the voltage spike that is being clamped by the silicon device. When using a switched inductive test circuit (Figure 2), the switch is turned on to charge up the inductor to a desired level (IAS) and then turned off to allow the voltage across the switch to ring up and exceed BVDSS. The MOSFET then enters avalanche, clamps the voltage to the BVDSS level, and the inductor current discharges into the drain. For silicon device with a 700V BVDSS rating, for example, and 100 µsec avalanche duration time with 10 A inductor current, the avalanche energy = 0.5 x (700VDS-50VDD) x 10A x 100us = 325 mJ! Already from this simple example we can see that avalanche breakdown can generate enormous amounts of energy in a very short amount of time. Also, since this time duration is very short, the heat generated from this energy does not have time to flow out of the package

and to the PCB so the device will heat up very quickly to very high temperatures (> 200C)! Also, this example is only for a single avalanche event (at starting Tj = 25C) so the device has time to cool back down before the next event.

For repetitive avalanche events, the device temperature will continue to rise and eventually thermally destruct. The silicon FET also includes a parasitic BJT that can self-turn-on during avalanche causing latch-up failures. Silicon MOSFET manufacturers have gone to great lengths to characterize their devices and provide maximum avalanche ratings in an effort to work-around this inherent device weakness.

But when the device is in the field, the actual surge voltage, current, time duration and no. of events (and resulting avalanche energy and device temperature) are all highly unpredictable. This places the robustness and reliability of the silicon device at high risk.

Figure 2: Silicon MOSFET avalanche unclamped inductive test circuit and waveforms

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No Avalanche, No Problem!

While Si devices have avalanche breakdown which limits their absolute maximum rating, GaNFast Power ICs do not have an intrinsic p-n junction for voltage blocking. As the drain voltage increases, they behave more like an insulator and will continue to increase in leakage well beyond the absolute maximum rating (Figure 3). This intrinsic behavior enables GaNFast Power ICs to continue switching through surge events or during circuit ringing or overshooting instead of avalanching. For a typical IEC61000-4-5 AC line surge condition, a 2 kV voltage spike can occur at the AC mains

input that lasts 50usec (half-value decay time). Some of this surge energy is absorbed by the input EMI filter and DC bus capacitor. The remaining energy can still increase the DC bus capacitor from 400V up to levels around 700V. The switched node of a half-bridge DC/DC circuit, for example, should withstand this voltage and ride-through the surge condition.

For good margin, GaNFast ICs have an 800V VDS(TRAN) peak transient voltage rating, and each IC is tested at higher voltages (up to 1000 V) during production to ensure excellent robustness in the field.

Figure 3: GaNFast Power ICs do not have avalanche breakdown and can ride through voltage surges

Over 3.5 Billion Spikes!

Navitas GaNFast ICs have undergone extensive robustness and reliability testing. For transient voltage spike testing, the maximum drain voltage is pulsed repetitively to a level of 800 V for a duration of 100 µsec (Figure 4). This is repeated every 2 msec for 2000 hours = 3,600,000,000 spikes! After

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testing, the GaN ICs are rescreened and show no change in functionality or any electrical parameters versus pre-test conditions. These results further reinforce the ruggedness of GaNFast ICs and their ability to withstand and ride through high voltage surge conditions.

Figure 4: GaNFast Power ICs voltage spike test circuit and VDS waveform

Continuous Ratings Matter!

In addition to the VDS(TRAN) rating for surge voltage immunity, the maximum VDS continuous rating, VDS(CONT), is also important for blocking repetitive circuit voltage waveforms over all line and load conditions. For the high-frequency quasi-resonant (HFQR) Flyback topology, the switch drain voltage waveform must be carefully inspected and checked to confirm that the absolute maximum ratings are not exceeded (Figure 5).

During the switch off-time, the drain voltage rings up and overshoots to a peak level and then settles at a plateau voltage (VPLATEAU) = VBUS level + VOUT x NP/NS. To guarantee reliability and lifetime requirements, VPLATEAU should not exceed the 80% derated level of 560V. When comparing VDS(CONT) ratings versus other GaN manufacturers (Figure 5),

it can be seen that Navitas GaNFast ICs have the highest VDS(CONT) rating (700V). This is due to the Navitas proprietary GaN IC termination design and the extensive reliability testing performed by Navitas, making it the ideal choice for providing enough drain voltage margin to satisfy reliability and lifetime requirements. Silicon MOSFETs also have a 700V maximum VBDSS breakdown rating, but the VSPIKE overshoot each switching cycle can exceed this level and cause repetitive and uncontrolled avalanche. As mobile charger and adapter power levels and output voltage levels increase, these maximum voltage ratings will become even more critical and necessary in order to meet acceptable reliability standards.

Figure 5: GHFQR flyback drain voltage waveform and VDS(CONT) ratings comparison

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Conclusion In the past, silicon MOSFET manufacturers performed avalanche testing and provided maximum avalanche ratings due to inherent device limitations in order to enable designers to realize their products. Many applications utilized avalanche and a rugged avalanche does give a system designer some comfort about the unforeseen inductive energy spike that might occur. Avalanche can also place circuit limitations on achievable current, voltage and power levels, especially for the QR flyback topology. GaNFast ICs intrinsically block higher voltage levels and this extra voltage margin is used to ride through surges instead of avalanche. This allows circuit topologies to be extended beyond their existing range in both performance and robustness. Combining the highest continuous and transient voltage ratings together with other GaNFast IC integrated features such as gate, drive, protection, and loss-less current sensing, and an industry-first 20-year warranty, we now have a rugged, reliable and proven solution to realize high-frequency, high-density and high-efficiency power supply designs. These ratings are already available today and will only continue to improve in the future.

References 1) GaNFast NV6123, NV6125, NV6127 datasheets, Navitas Semiconductor, 2019 2) GaNFast NV613x/NV615x/NV6169 Power ICs with GaNSense Technology datasheets, Navitas Semiconductor, 2021 3) IPD65R400CE datasheet, Infineon Technologies, 2016 4) Electromagnetic Compatibility, International Standard IEC 61000-4-5, Second Edition, 2011 5) Surge Energy and Overvoltage Robustness of Cascode and Direct-drive GaN HEMTs, Qihao Song, CPES, 2022

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Power ICs Integrate Fast, Autonomous, Precise Protection Circuits for Ultimate System Robustness Tom Ribarich, Sr. Director Strategic Marketing, Navitas Semiconductor

Introduction Power supply designs continue to push the boundaries for higher power, higher frequency, and higher power density. As maximum load requirements increase and size decreases, the current, power and thermal stress also increases for the power switching device. The need to protect against overload conditions becomes paramount. As switching frequency increases, the need for faster fault detection, reaction, and protection times becomes critical to prevent damage or destruction. The latest GaNSense Power IC protection features are specifically designed for ultra-fast detection and protection against various fault conditions. This article explains each fault condition and shows how GaNSense power ICs detect and protect against these overload events.

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Danger! Device Overload!

Every designer’s worst nightmare is a damaged power supply. This can consume endless resources and schedule delays to perform the failure analysis, find a solution, manage resulting product recalls, and minimize customer downtime. If the switching device is damaged, then it was most likely caused by an overload condition. A series of events usually occurs that eventually leads to thermal overload and destruction. Assuming the unit is running under worst-case conditions (low AC line input, 100% load, and the highest ambient temperature), the current ramps up in the device during a normal switching cycle.

The I2R conduction losses increase, causing the junction temperature (TJ) to increase. As the current increases further, the device will start to saturate, and the device’s current and voltage will instantly increase to a very high level before any over-current protection circuit can react. The resulting power loss and TJ increase so high and so fast that the package and heatsinking cannot dissipate the heat in time for the main circuit fuse to open first. The package then cracks or explodes, causing smoke or fire, and the unit stops working. A truly reliable protection solution against device overload requires multiple protection circuits to detect overcurrent, saturation, and over-temperature fault conditions and shut down safely before destruction occurs.

Figure 1: Device overload causes high temperatures and destruction.

Over-Current Protection (OCP) Over-current protection is a safety feature that is designed to prevent damage to a device or circuit by limiting the flow of current. In the case of GaN devices, over-current protection is particularly important due to the high switching speeds and high power density of these devices. If an over-current event occurs, it can cause significant damage to the GaN device and may even result in its failure. An external current sense resistor is usually placed in between the source of the power FET and ground, and a comparator and threshold voltage are used to detect when the voltage across the current sense resistor exceeds a maximum limit (Figure 2). Should the current exceed this maximum limit, the comparator output is then used to disable the power FET gate driver to turn it off safely before any damage can occur. This method typically

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has a long delay time (300 nsec) and is commonly used for Silicon FETs running at low frequencies (<100 kHz) where the OCP circuit has enough time to detect and turn the power FET off before the current can over-shoot and cause damage. This delay time is also needed to blank out any false triggering due to parasitic inductance spikes that can occur due to the external current sensing resistor and PCB traces. At higher switching frequencies, the current ramps much faster each switching cycle, so the speed of detection becomes critical. Due to the minimum blanking delay time needed with external current sensing circuits, this method is inherently limited to lower frequencies. Another solution is needed that can detect and protect much faster and is not susceptible to parasitic noise spikes.

Figure 2: Integrated GaNSense OCP vs external OCP simplified circuits and timing diagrams

To improve the OCP function, GaNSense power ICs integrate autonomous, cycle-by-cycle detection and protection circuitry together with the GaN power FET and gate driver (Figure 2).

This dramatically minimizes the delay time needed to detect the fault and minimizes the delay time to react and shut down the power FET. Also, because the current sensing is also integrated, the parasitic inductances and noise spikes are now eliminated, so the required blanking time is minimized.

The result is an OCP circuit that reacts six times faster than the traditional external method. This real-time, instant solution detects and protects within 50 nsec and reduces the peak current over-shoot to a nearly negligible level. Figure 3 shows the NV6169 GaNSense power IC waveforms during an OCP event. The current ramps up each cycle to a higher peak

level as the internal GaN power FET is turned on and off with the PWM input. When the CS pin output exceeds the internal 1.9 V threshold, the internal gate driver is turned off instantly, and the on-time period is truncated. The cycle-by-cycle OCP circuit will continue to truncate each on-time period when the over-current event occurs to limit the maximum current level and safely protect the device (and external circuit) from damage. The NV6169 also includes a fault output pin (FLTN) that goes low each cycle when the over-current event occurs.

This signal can be fed back to the system controller so it can decide if it should shut the complete unit down on the first pulse or wait until several sequential OCP events have occurred.

Figure 3: NV6169 GaNSense power IC cycle-by-cycle OCP waveforms, IL = green (5 A/div), VDS = yellow (100 V/div), CS = red (0.35 V/div), FLTN = blue (5 V/div), time = 5 µsec/div

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Avoid Saturation! Avoid the Runaway!

Similar to silicon FETs, GaN power FETs also have linear and saturation regions of operation (Figure 4). When the GaN power FET is in the ON state and the VGS voltage is at a fixed level (i.e. 6 V), a current will flow from the external switched-mode power supply circuit, through the drain, and to the source. The IDS current and VDS voltage levels are low enough such that the GaN power FET operates in the linear region where the VDS voltage changes linearly with the IDS current with a slope equal to RDS(ON). The I2R conduction power losses and resulting thermals are at acceptable levels.

Should the IDS current levels start to increase to higher levels due to an overload condition, the device will start to enter the saturation region. The I-V curve starts to flatten, and the VDS voltage starts to increase very rapidly. The resulting conduction losses and device temperature will also increase rapidly. As the device temperature increases, the device will go deeper into saturation, causing higher losses and higher thermals. This “thermal runaway” condition will cause the device to become damaged or self-destruct.

Figure 4: GaN FET linear and saturation operating regions

To protect against saturation, GaNSense power ICs include a short-circuit protection circuit (SCP). This circuit differs from OCP in that it detects the VDS voltage instead of the IDS current. The VDS(ON) voltage is measured during each on-time period of the GaN power FET and compared against an internal SCP threshold voltage. During a short-circuit event, the device will saturate, and the VDS(ON) voltage will increase very rapidly to a high level and exceed the SCP threshold voltage. The internal comparator will detect the high VDS(ON) voltage and shut down the GaN power FET instantly, truncating the on-time before thermal runaway or damage can occur. This SCP detection adds another level of

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robustness and reliability to the GaNSense power IC since it will always detect and protect against saturation, even as the saturation point moves with temperature. Figure 5 shows the NV6169 GaNSense Power IC waveforms during an SCP fault event. As the current increases each switching cycle, the device eventually saturates and the VDS voltage increases rapidly. The integrated cycle-by-cycle SCP protection circuit instantly shuts down the GaN power FET safely to avoid damage. The FLTN output also goes low each cycle during an SCP fault event and can be used by the system controller to decide how the system should react.

Figure 5: NV6169 GaNSense power IC SCP protection waveforms. IL = green (20 A/div), VDS = yellow (100 V/div), VDS_clamped = red (2 V/div), FLTN = blue (5 V/div), time = 10 µsec/div

Over-Temperature Protection (OTP) To further increase reliability and robustness, GaNSense power ICs include integrated over-temperature protection (OTP). Traditional OTP circuits are placed externally on the PCB and located far away from the power switch. These are typically used to detect an over-temperature condition in the ambient air of the power supply unit. The external temperature sensor is very slow and waits until the ambient air heats up and reaches the OTP threshold before shutting down the unit. This could take minutes or longer after the power FET has already experienced an overload condition.

By integrating the OTP circuitry together with the power FET, a more precise and faster detection is achieved that can protect much faster than an external sensor. The internal power FET will heat up very quickly during an overload condition, and the IC package and heatsink will not react

fast enough to remove the heat. The internal OTP circuit will monitor a temperature that is very close to the TJ of the GaN FET so it can turn off the circuit safely before any damage can occur. For a discrete GaN FET during an overload condition without integrated OTP (Figure 6), the GaN FET will not turn off precisely at the TJMAX limit and will continue switching into the thermal danger zone and thermally destruct. The GaNSense power IC with integrated OTP will turn off below the TJMAX limit and restart again at a lower TJ level when the part has cooled down. If the OTP condition persists, the GaNSense power IC will continue to turn on and off at the upper and lower TJ levels, and the average TJ temperature will stay below TJMAX and in the safe thermal area.

Figure 6: GaNSense integrated OTP offers a more precise and faster detection-to-protection response time than an external sensor.

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Conclusion Each of these fault conditions, if left unprotected, can cause thermal overload and damage to the power device. Typical controller over-current or short-circuit protection circuits have inherent delay times that can result in higher maximum current levels than expected. Over-temperature protection circuits typically measure ambient temperatures so it is difficult to correlate to the actual power device junction temperature. By integrating these protection circuits with the power device, the detection-to-protection delay time is greatly reduced to minimize the peak current overshoot, and the maximum junction temperature is more accurately

limited. As switching frequencies continue to increase, all of these delay times become even more critical. This further emphasizes the need for ultra-fast detection-to-protection times, and accurate over-temperature control to ensure high robustness for high-frequency and high-density power converter designs. No power transistor other than Navitas GaNSense power ICs has this level of protection with OCP, OTP, and SCP all built-in. The latest GaNSense power IC product line-up (Figure 7) includes a wide range of packages and RDS(ON), suitable to cover a wide range of applications. For more information, please visit: www.navitassemi.com.

Figure 7: GaNSense Power IC portfolio provides solutions for a wide range of power levels and applications.

References 1) GaNFast NV6123, NV6125, NV6127 datasheets, Navitas Semiconductor, 2019 2) GaNFast NV613x/NV615x/NV6169 Power ICs with GaNSense Technology datasheets, Navitas Semiconductor, 2022 3) Tom Ribarich, “Who Needs Avalanche?”, Technical Article, PSD Magazine, 2022

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