Leading the next wave of innovation in semiconductor manufacturing

Microchips are integral to 21st-century life because they power the smartphones we rely on, the cars we drive and the advanced weaponry that is the backbone of national security. But their mighty computing power builds up a lot of heat.

Manufacturers have always designed packaging — the materials around the chips — to mitigate heat, provide protection and enable electrical current to flow. Over the decades, as the chips became more powerful, the packaging became more sophisticated.

Now, “advanced packaging” is a critical part of the design and manufacture of chips, not only to protect them from heat but also as a way to improve their performance. The newest generation of advanced packaging is integrated with the chips during the manufacturing process to make them work faster and even combine different kinds of chips into one package for super advanced capabilities like artificial intelligence.

In November, the National Institute of Standards and Technology — part of the U.S. Department of Commerce — announced that it plans to award as much as $100 million to Arizona State University and Deca Technologies to drive innovation in the domestic microchip packaging ecosystem.

The SHIELD USA (Substrate-based Heterogeneous Integration Enabling Leadership Demonstration for the United States of America) initiative is the first of several research and development programs to be launched by the CHIPS National Advanced Packaging Manufacturing Program (NAPMP). This first program, focused on organic materials and substrates, will be a vital part of the broader $11 billion CHIPS R&D program administered by the U.S. Department of Commerce.

Even as leading-edge semiconductor foundries have returned to the U.S., packaging remains based in Asia, posing significant risks to national security and supply chain resilience. SHIELD USA’s impact on advanced packaging technologies will enable the reshoring of packaging to reestablish the domestic supply chain.

Deca’s M-Series fan-out wafer-level packaging and Adaptive Patterning technologies have been broadly adopted across multiple device technology nodes in leading smartphones today. SHIELD USA will leverage these proven building blocks to scale down feature sizes and scale out heterogeneous integration of chiplets — both of which are critical for future chips.

To bring substrate manufacturing back to the U.S., we need to change the game. More than incremental progress, we need 10X breakthroughs. This is a fantastic example of a university working in close partnership with industry to drive innovation, and we’re excited to partner so closely with ASU and to collaborate with leading industry players in this effort to reestablish technology leadership.”

— Craig Bishop, chief technology officer, Deca Technologies

At the heart of this initiative is ASU’s MacroTechnology Works, home to the Advanced Electronics and Photonics Core Facility. Drawing on the unmatched capabilities offered by ASU and partners such as Deca, researchers are exploring the commercial viability of 300 mm wafer-level and 600 mm panellevel manufacturing, a technology that does not exist as a commercial capability in the U.S. today.

SHIELD USA’s education, training and workforce development programs will support the human capital necessary to establish interconnected foundries and enable a robust foundation for a sustainable domestic pipeline of packaging substrates and materials research and manufacturing for years to come.

In addition to Deca Technologies, the SHIELD USA team includes participation from several major semiconductor companies, including AMD, IBM, NXP, Synopsys, Saras Micro Devices and Analog Devices. These companies will provide crucial test chips and support for the technology’s design, simulation and testing. Additionally, key domestic packaging manufacturers, such as IBM and SkyWater Technology, will aid in scaling and deploying the technology in U.S.-based facilities.