Solution Manual For Foundations of Computer Engineering, Edition 1 By Marilyn Wolf, Ph.D., Electrica

Solution Manual For Foundations of Computer Engineering, Edition 1 By Marilyn Wolf, Ph.D., Electrical Engineering, Stanford University

1 Part Instructor's Manual 2 Part Instructor's Manual 3 Part Instructor's Manual Chapter 1: Hardware and Software 1. Give an example of a computing service supplied by a data center.

Shopping, credit card transactions, video streaming, banking.

2. Give an example of a computing application that makes use of both a personal computer and a data center.

Bank account access, video streaming, shopping.

3. Give an example of an Internet-of-Things device.

Video doorbell, thermostat.

4. Give an example of an application that makes use of an Internet-of-Things device connected by a network to another computer.

Video doorbell, remote control doorbell.

5. Can the block diagram of a computer system in Figure 1.15 be expanded to include two CPUs? Explain your answer.

Yes, both CPUs can be connected to the bus.

6. Give an example of an I/O device.

Mouse, keyboard, display, storage device.

7. Redraw the block diagram of Figure 1.15 to include a graphics unit and a touchpad.

8. Where does an executable program reside in Figure 1.15?

The executable program resides in memory.

9. Draw a UML object diagram of a two-function calculator that performs addition and subtraction.

Include the keyboard, display, and calculator application.

10. Draw a UML sequence diagram for performing 2 + 3 = 5 on the two-function calculator.

11. Draw a UML state diagram for the two-function calculator application.

12. Give an example of a computer application that exhibits each of these trade-offs: a. Low cost, simple computing.

Garage door opener. b. Moderate cost, general-purpose computing, flexible I/O. Laptop. c. Moderate cost, communication-centric computing, low power consumption.

Smartphone. d. High-performance computing, large memory capacity.

Data center server.

13. Write each of the digits 0 through 7 as a byte.

0: 00000000 1: 00000001

2: 00000010 3: 00000011 4: 00000100 5: 00000101 6: 00000110 7: 00000111 14. Write each of these decimal numbers as a sixteen-bit number: a. 15 0000000000001111 b. 16 0000000000010000 c. 2047 0000011111111111 d. 3333 0000110100000101 e. 10352 0010100001110000 15. How many bits are required to represent the 26 characters of the Roman alphabet? , enough for the 26 characters plus room for several others.

16. What role does an operating system play in the operation of a computer system?

The operating system manages resources including the CPU, memory, storage, and I/O devices.

17. Draw a UML state diagram for a blinking light that blinks three dots (…). Show each operation as a state.

18. Give three utilities provided by an integrated development environment.

Program editor and syntax checker, compiler, linker, loader, debugger.

19. Can an integrated development environment run on the same computer for which the program is being developed?

Yes, integrated development environments have been built to support Windows and Mac development.

20. A program includes a bug caused by testing the wrong variable in an if statement. Describe how you can identify this bug: a. Without using a debugger.

Output statements can be added to indicate when the program executes a certain path.

These statements can help to isolate where the program takes the wrong path. b. Using a debugger.

The debugger will allow breakpoints or single-stepping that allow you to view the program’s execution path as it runs.

Chapter 2: Operating Systems and Applications 1. What capabilities are provided by the operating system on your laptop computer?

Provide user interface, manage file system, provide I/O services, share computer among several applications, manage network communications.

2. What errors could be caused by two applications that directly save data on a storage device without going through an operating system?

The applications could destroy each other’s data.

3. How could two applications share the CPU without going through an operating system? What errors might be introduced?

The two applications could be written to transfer control to the other application. A programming error could cause one application to not transfer control, locking the other application out of the computer.

4. Give an example of a single application running concurrently as two separate processes.

Two instances of an editor, each editing a different file?

5. Why might a program follow two different threads of execution at different times?

Different data values can cause each thread to follow different paths of execution.

6. Can a computer system with a single CPU provide real concurrency? Explain.

A basic CPU can execute only one program at a time. However, some CPUs provide multithreading that allow it to switch between multiple threads. The CPU may also operate concurrently with storage devices or I/O devices.

7. What happens to data stored in memory when the computer is disconnected from power?

Memory is voltatile and will lose its data values when power is removed.

8. What happens to data stored in a solid-state disk when the computer is disconnected from power?

Data stored in an SSD will be retained when power is removed. However, if power is removed while a write operation is in process, that data may be corrupted.

9. Is data stored in memory considered a file?

No, data in memory is not organized in a file system. However, some data read or written to the file system may be temporarily stored in memory.

10. Describe a directory entry for a file foo.c whose data is stored in three separate areas of the chip: the first third of the file starting at storage location 100; the second third of the file starting at location 100,000; the third part of the file starting at location 51,326.

11. Draw a directory three that describes these three files: /a/b/c/foo.c, /a/b/d/foo.c, /x/y/foo.c

12.

What happens to the contents of a user interface window while that window is closed but not deleted?

The state of the user interface is maintained. A typical operating system will allow the application attached to the closed window to continue to run.

13. What happens to an application running in a user interface window when that window is deleted?

The application will be terminated.

14. What is the relationship between a window and an icon in the WIMP model?

An icon may be clicked to start an application that opens a window.

15. What is the relationship between a menu and a window in the WIMP model?

A menu may be used to run an application that opens a window.

16. Draw a UML sequence diagram to show two processes that alternate execution on a single CPU under control of an operating system.

17. Draw a UML sequence diagram to show a process reading data from an input device using a driver.

18. Draw a UML sequence diagram to show a process writing data to an output device using a driver.

19. Draw a UMLstate diagram for a dual-boot sequence.

Chapter 3: Programs and Code a. b. c. d.

1. Which of these is not a data type? int. char. ‘b’. float. c is not a data type. A, b, d, are all data types.

2. Represent each of these numbers as an 8-bit two’s complement number. a. 4 00000100

b. -4 11111100 c. 7 00000111 d. -7 11111001 3. Which of these numbers can be represented as an 8-bit two’s complement number? a. 5 Yes, 00000101 b. -2047 No, too large in negative direction, most negative number is -128. c. 2047 No, too large in positive direction, most positive number is 127.

4. Which of these numbers can be represented as an 8-bit unsigned number? a. 255 Yes, maximum number is 255. b. -127.

No, negative numbers cannot be represented as unsigned.

5. Write each of these decimal numbers as two hex digits. a. 11 0x0b b. 27 0x1b c. 123 0x7b d. 255 0xff 6. Show the contents of each C array as a table with two columns: index and value. a. int a1[3] = [7, 3, 29]; Index 0 1 2

value 7 3 29

b. int a2[4] = [2, 3, 4, 5]; Index 0 1 2 3

value 2 3 4 5

c. int a3[5] = [2, 4, 6, 8, 10]; Index 0 1 2

value 2 4 6

3 4 d. char foo1[3] = [‘f’, ‘o’, 0];

8 10

Index value 0 ‘f’ 1 ‘o’ 2 0 e. char foo1[4] = [‘f’, ‘o’, ‘o’, 0]; Index value 0 ‘f’ 1 ‘o’ 2 ‘o’ 3 0 7. Show the value of foo at each commented line: a. { int foo; foo = 1; /* line a1 */ { int foo; foo = 2; /* line a2 */ } } b. { int foo; foo = 1; /* line b1 */ { int foo; foo = 2; /* line b2 */ { int foo; foo = 3; /* line b3 */ } } c. { int foo, baz; foo = 1; /* line c1 */ { int foo; foo = 2; /* line c2 */ } baz = foo + 1; /* line c3 */ } 8. What value is assigned to each variable? a. int foo1 = 2 + 3; 5 b. int foo2 = 0xa + 3; 0xd c. int foo3 = -1 + 1; 0 d. char foo4 = ‘a’ + 1; ‘b’

e. int foo5 = 0xf & 0x3; 0x3 9. What is the value of foo after executing each code fragment? a. if (3 < 5) { foo = 1; } else { foo = 2; } foo = 1 b. if (3 > 5) { foo = 1; } else { foo = 2; } foo = 2 c. t = 3; foo = 0; while (t < 5) { t = t + 1; foo = foo + 1; } foo = 2 d. for (i = 0, foo = 0; i < 3; i++) { foo = foo + 2; } foo = 6 10. Given these values at these memory locations, what value will be produced by each pointer operation? location value 100 1 101 2 102 3 103 4 a. p1 = 100; (*p1); 1 b. p1 = 101; (*p1); 2 c. p1 = 100; (*(p1+1)); 2 d. p1 = 103; (*(p1-1)); 3 11. You are given this program: int f1(int a) { return foo = a; /* line a */ } int f2(int a) { return foo = f1(2)+a; /* line b */ } int f3(int a) { return foo = f2(4)+a; /* line c */ } int baz = f3(5); Give the value of foo at each commented line. a. 2

b. 6 c. 15 12. Show the progression of the stack for a recursive implementation of the Fibonacci function: . Use .

Stage 1: fibonacci(2); Stage 2: fibonacci(2); fibonacci(1); Stage 3: fibonacci(2); fibonacci(0); Stage 4: fibonacci(2);

13. Show the progression of the heap for each sequence of allocations: a) Allocate a (8 bytes); allocate b (4 bytes); allocate c (8 bytes); deallocate b.

b) Allocate a (8 bytes); allocate b (4 bytes); deallocate b; allocate c (4 bytes).

c) Allocate a (4 bytes); allocate b (4 bytes); deallocate a; allocate c (8 bytes).

Chapter 4: CPUs and Programming Models 1. What happens when a CPU’s program counter is set to the starting address of a C array?

The CPU executes the array contents as if they were instructions.

2. What objects would not be part of a programming model? a. General-purpose register. b. C array. c. Adder.

C array and adder are not part of a programming model. A general-purpose register is a typical part of a programming model.

3. You are given these register and memory values: x2 = 100 location value 100 1 101 2 102 3 103 4 What value is loaded into x1 for each load operation? a. ld x1, 0(x2) 1 b. ld x1, 1(x2) 2 c. ld x1, 2(x2) 3 d. ld x1, 3(x2) 4 4. What distinguishes a jump instruction from a branch instruction?

A jump is conditional, a branch is conditioned on a comparison or data value.

5. You are given these decimal register values: x1 = 200 x2 = 100 x3 = 201 x4 = 101 What operands are used for each RISC-V instruction? a) add x1, x2, x3 rs1 = 100, rs2 = 201 b) addi x1, x2, 5 rs1 = 100, imm = 5 c) add x2, x3, x3 rs1 = 201, rs2 = 201 d) add x4, x3, x2 rs1 = 201, rs2 = 100 6. You are given these hexadecimal register values:

x1 = 0x201 x2 = 0x101 x3 = 0x200 x4 = 0x100 x5 = 0x2 What is the value of x1 after each RISC-V instruction? d) add x1, x2, x3 0x301 e) addi x1, x2, 5 0x106 f) add x1, x3, x3 0x400 g) add x1, x3, x2 0x301 h) xor x1, x1, x2 0x300 i)

xor x1, x2, x3 0x301 j) sll x1, x2, x5 0x404 7. You are given these hexadecimal register values: x1 = 0x100 x2 = 0x10 x3 = 0x14 You are also given these hexadecimal memory values: Address value 0x10 0x1 0x11 0x2 0x12 0x3 0x13 0x4 0x14 0x5 0x15 0x6 0x16 0x7 0x17 0x8 What is the value of x1 after each RISC-V instruction? a. lw x1, x2(0) 0x5432 b. lw x1, x2(1) 0x6543 c. lb x1, x2(0)

0x1 d. lb x1, x3(1) 0x6

Chapter 5: Code and Instructions 1. Show the stack at each indicated line in the program. For each stack frame, indicate the function name, internal variables, and parameter names. int f1(int a) { int foo = a + 1; /* line a */ } int f2(int b) { int baz = f1(b) + 1; /* line b */ } int f3(int c) { int boo = f2(c) + 1; /* line c */ } f3(1); a. [ function f1; internal variable foo; parameter a] [ function f2; internal variable baz; parameter b] [ function f3; internal variable boo; parameter c] b. [ function f2; internal variable baz; parameter b] [ function f3; internal variable boo; parameter c] c. [ function f3; internal variable boo; parameter c] 2. For each set of instructions, give the C language code that the instructions implement. Use variable names a, b, c, d, e. a. lw x1, 44(sp) lw x2, 48(sp) add x3, x1, x2 addi x3, x3, 1 a = b + c + 1; b. addi x2, x2, -1 bge x2, x3, y x: addi x2, x2, 2 j z y: addi x2, x2, -1 z: a = a – 1;

if (a < b) { a = a + 2; } else { a = a – 1; } c. li x1, -5 li x2, 0 x: blt x1, x2, y addi x1, x1, 1 j x y: a = -5; b = 0; while (a < b) { a = a + 1; } d. li x1, 3 li x2, 1 li x3, 0 x: blt x3, x1, y addi x2, x2, 2 addi x1, x1, 1 j x y:

for (a = 0; a < 3; a ++) { b = b + 3; } 3. For each statement, give the RISC-V instructions that implement the statement. a. z = x + y; lw x28, 44(sp) lw x29, 44(sp)

add x3, x28, x29 sw x3, 52(sp) b. z = x[0] + y[1]; lui x10, %hi(x) lddi x10, x10, %lo(x) lui x11, %hi(y) lddi x11, x11, %lo(y) lw x28, 0(x10) lw x29, 4(x11) add x3, x28, x29 sw x3, 52(sp) c. if (z) z = 1; else z = 2; lw x28, 44(sp) li x29, 0 blt x28, x29, else1 if1: li x28, 1 sw x28, 44(sp) else1: li x28, 2 sw x28, 44(sp) endif1: d. z = 2; while (z >= 0) z = z – 1; whiletest: li x28, 2 blt x28, x0, whileexit subi x28, x28, 1 j whiletest: whileexit:

4. For the given memory contents and register values, give the results of each load/sequence of loads.

Memory address (bytes) Value (32-bits) 100 8 104 12 108 5 112 13 116 1 120 2 124 3 128 4 132 136 Register x1 x2 x3 x4

value 108 112 1 2

a) lw x3, 0(x1) x3 = 5 b) lw x4, 4(x1) x4 = 13 c) lw x3, 12(x2) x3 = 3 d) lw x3 0(x1); lw x4, 0(x3) x3 = 108; x4 = 5 5. For each sequence of instruction calls, give the order of activation records in the stack and show the passed parameter values in each activation record. a. p1(2, 3) calls p2(3, 4) calls p3(1). [[ p1; parameters 2, 3 ]] [[ p2; parameters 3, 4 ]] [[ p3; parameters 1 ]] b. r1(3) calls r1(2) calls r1(1). [[ r1; parameters 3 ]] [[ r1; parameters 2 ]] [[ r1; parameters 1 ]]

Chapter 6: Input and Output 1. How does a device handler change a register in its I/O device?

In a memory-mapped I/O system, the handler writes an assigned memory location to change a device register.

2. Why might an output device interrupt?

To indicate to the handler that it has completed the output operation.

3. Draw a UML sequence diagram for a busy-wait read operation. Include the application, handler, and device.

4. Draw a UML sequence diagram for an interrupt-driven read operation. Include the application, handler, and device.

5.

Draw a UML sequence diagram for a vectored, prioritized interrupt. Include the CPU, device, vector table, and handler.

6.

Draw a UML sequence diagram for two simultaneous interrupts by different devices. Device 1 has higher priority than device 2. Include the CPU, device 1, device 2, handler 1, handler 2, and vector table.

Chapter 7: Logic and Circuits 1. Write a truth table for each of these Boolean functions. Include a column for each subexpression enclosed in parentheses as well as the full expression. a. (a && b) || c a b c a&&b (a && b) || c 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 b. 𝑎⨁𝑏⨁𝑐 a 0 0 0 0 1 1 1 1 c.

𝑎⨁𝑏⨁𝑐

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

0 1 0 0 1 0 0 1

a

b

c

b || c’

a’ && (b || c’)

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 1 1 1 0 1 1

1 0 1 1 0 0 0 0

a’ && (b || c’)

d. (abc) || (a’bc) || (ab’c) || (abc’) a

b

c

abc

a’bc

ab’c

abc’

(abc) || (a’bc) || (ab’c) ||

(abc’) 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

0 0 0 1 0 1 1 1

e. (ax’y’) || (bxy’) || (cx’y) || (dxy) a

b

c

d

x

y

ax’y’

bxy’

cx’y

dxy

0 1 -

0 1 -

0 1 -

0 1

0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

0 1 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 1

2. How many Boolean functions can be implemented by a four-input lookup table?

3. Write Boolean AND-OR-NOT expressions for all of the Boolean functions that can be implemented by a three-input lookup table with inputs a, b, c. a’b’c’ a’b’c a’bc’ a’bc ab’c’ ab’c abc’ abc 4. Draw a transistor schematic for a two-input NAND gate.

(ax’y’) || (bxy’) || (cx’y) || (dxy) 0 1 0 1 0 1 0 1

5. Draw a transistor schematic for a two-input NOR gate.

6. Draw a transistor schematic for a three-input NAND gate.

7. Draw a transistor schematic for a three-input NOR gate.

Chapter 8: Register-Transfer and Finite-State Machines 1. Write HDL code for a register with a reset input that sets the register’s internal state to 0 when reset = 1. always @(posedge clk or posedge reset) begin iIf (reset) begin q <= 0; end; else begin q <= d; end; 2. The shift register of Figure 8.23 has an initial state of 00 and is given a sequence of three inputs: 0, 1, 1. Show the state of each register for each clock cycle.

Clock cycle 0: internal state 00, output 0 Clock cycle 1: internal state 00: output 0 Clock cycle 2: internal state 10: output 0 Clock cycle 3: internal state 11: output 1 3. The counter of Figure 8.24 has an initial register state of 11. The machine is given a sequence of three incr inputs: 1, 0, 1. Show the state of each register for each clock cycle.

Clock cycle 0: internal state 11, done 0

Clock cycle 1: internal state 00: done 1 Clock cycle 2: internal state 00: done 0 Clock cycle 3: internal state 01: done 0 4. Draw a transistor schematic for a CMOS dynamic latch with two data inputs D1 and D2. The data input used is controlled by two clock signals clock1 and clock2. The system guarantees that (clock1 && clock2) == 0 at all times.

5. Draw a timing diagram for a data signal to a register that violates the register’s setup time.

6. Draw a timing diagram for a data signal to a register that violates the register’s hold time.

7. Assume that the delay through a gate is proportional to its number of inputs. For each schematic, identify the longest path and give its worst-case delay. a. Longest path is a-z with delay 4.

b. Longest path is a/b-x with delay 4.

c. Longest path is a/b-x with delay 5.

8. Draw a state transition graph for a three-bit counter with reset.

9. Write a state transition table for a three-bit counter with reset. Name the count bits c2 c1 c0.

count 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

c2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

c1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

c2_next 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

10. Draw a logic gate schematic for a two-bit counter with a reset input.

c1_next 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

c0_next 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Chapter 9: Data and Control 1. What outputs from the controller are required for the datapath of Figure 9.4?

Register: rs1, rs2, rd, write ALU: op Temp register: load 2. You are given a datapath without an ALU temporary register---the ALU output goes back directly to the register file. Can you use this datapath to read a register, perform an operation on it, and write back the result to the same register? Explain.

No, the register circuits used in the register file cannot be read and written at the same time. Trying to do so would corrupt the value in the register.

3. Draw a state transition graph for a controller that performs r3 = r1 + r2 on the datapath of Figure 9.4.

4. Draw a state-transition graph for a controller that performs r4 = r1 + r2 + r3 on the datapath of Figure 9.4.

5. Modify the datapath of Figure 9.4 to include an immediate operand input as the op2 ALU input.

Chapter 10: Memory and Storage 1. Why is a CPU cache designed using SRAM rather than DRAM? SRAM is faster than DRAM. A slow cache would delay CPU operations. The cache is relatively small so its higher power consumption is not as important.

2. Draw a UML sequence diagram showing a hit followed by a miss on the instruction cache of Figure 10.5.

3. Draw a UML sequence diagram showing a level 1 data hit, a level 1 miss/level 2 hit, and a level 2 miss on the cache system of Figure 10.9.

4. Why is flash memory not used as main memory in a typical computer system?

Flash memory has longer write times than does DRAM. 5. Write the Boolean logic formulas required to select one of four row lines in a memory. The address lines are a1 a0.

row0 = a0’a1’ row1 = a0 a1’ row2 = a0’a1 row3 = a0 a1

Chapter 11: Instructions and Logic 1. Which of these RISC-V instructions makes use of the memory stage of a five-stage execution model? a. addi b. lw c. blt lw does use the memory stage, addi and blt do not 2. Which of these RISC-V instructions makes use of the writeback stage of a five-stage execution model? a. addi b. lw c. blt addi does use the memory stage, lw and blt do not 3. Draw a RISC-V pipeline diagram for eight cycles of execution of this sequence of instructions in two cases: add x27, x28, x29 lw x26, 0(x30) blt x27, x26, foo li x25, 7 foo: li x24, 8 a) Branch is not taken.

We can use a RISC-V simulator such as Ripes to understand the execution of this instruction sequence.

b) Branch is taken.

Chapter 12: Bus and Device 1. Give the sequence of states traversed by the bus protocol of Figure 12.6 when the I/O device takes two clock cycles to respond. idle x idle, request x idle, request x idle, request x respond, request x finish, done x finish, idle x idle 2. Draw a timing diagram for the bus protocol of Figure 12.6 when the I/O device takes two clock cycles to respond. Show the enq and ack signals.

3.

Draw a UML sequence diagram for the bus protocol of Figure 12.6. The diagram should include the CPU and the I/O device.

4. Draw a UML state diagram for an I/O device that uses the bus protocol of Figure 12.6.

5. Modify the UML sequence diagram of Figure 12.13 to show an interrupt request from device 2 shortly after the CPU initiates the DMA request.

Chapter 13: Interrupts and Drivers 1. Modify the UML sequence diagram of Figure 13.2 to show two devices that interrupt simultaneously with device 1 having higher priority than device 2.

2.

Write a truth table for a Boolean function that arbitrates by priority among four interrupt sources i0, i1, i2, i3 and produces four acknowledgments ack0, ack2, ack3, ack4. Source i0 has the highest priority. i0 1 0 0 0

i1 1 0 0

i2 1 0

i3 1

ack0 1 0 0 0

ack1 0 1 0 0

ack2 0 0 1 0

ack3 0 0 0 1

Chapter 14: Laptops and Servers 1. Why is memory connected to the CPU separately from I/O devices?

Memory access times are a critical factor in CPU performance. A separate memory connection avoids competition between memory and I/O. 2. Why are separate interconnect paths provided for low-speed and high-speed I/O devices?

Bus transactions for low-speed devices occupy the bus for a longer time, increasing the service time for the high-speed devices.

Chapter 15: Sensors and Events 1. Identify the times at which events occur on this signal for each definition of the event condition.

temperature (°C) vs time (minutes) 25 20 15 10 5 0 0

a. b. c. d. e.

5

10

15

20

25

30

rising rising falling falling

2. A Hall effect sensor is attached to a door. Identify open and closed events on this door sensor activity:

Event time and value:

3. Can a Hall effect sensor be used to detect which way a door is opening?

Yes, if the sensor can detect current and applied field movement in both directions.

Chapter 16: Filters and Detectors

1. Write a formula for the average of three successive samples of

.

(

)

2. Write a formula for the difference of two successive samples.

(

)

3. Write a formula for the 2-1 decimation of a time series.

(

)

4. Write a formula for the interpolation of values between two successive values of a time series. (

)

1. Draw the bang-bang controller command for this input sequence and values

temperature (°C) vs time (minutes) 49 48 47 46 45 44 43 42 41 40 39 0

5

10

15

20

25

30

.

Chapter 17: Actuators and Control 1. Draw the bang-bang controller commands for this input sequence and values

temperature (°C) vs time (minutes) 49 48 47 46 45 44 43 42 41 40 39 0

5

10

15

20

25

30

.

command 1.2 1 0.8 0.6 0.4 0.2 0 0

5

11

13

17

21

24

command

Chapter 18: Networks and Distributed Systems 1. Why are different computer systems built with different types of networks?

Computer systems vary widely in the amount of data traffic they use. High-bandwidth networks cost more to install. Networks are matched to their required traffic for cost efficiency.

2. A network uses a frame with data size of 20 bytes. How would a message of 100 bytes be sent?

The message would be sent in five different frame. The frame would be reassembled into the message by the receiver.

3. Draw a UML sequence diagram for a series of MQTT messages in a system. The system has three nodes: A (subscribes to topic2, topic 3), B (subscribes to topic1, topic3), C (subscribes to topic1, topic2). Nodes send these messages in order: node A sends topic3; node B sends topic3; node C sends topic2; node A sends topic2; node C sends topic1; node B sends topic1.