Solution Manual for Computer Organization, Design, and Architecture, 6E By Sajjan G. Shiva_compresse

Chapter 1 INTRODUCTION

1.1.

Hardware: the physical components of a system.

Firmware: low level programs that typically reside in ROM and control the system's hardware.

Software is the collection of programs that enables the system to perform specific tasks.

1.7.

This year the transistor is 1 micron in diameter.

Next year the transistor is ½ micron in diameter.

Two years from today, the transistor is ¼ micron in diameter.

1.8.

There are 2

10

kilobytes in a megabyte of memory.

There are 210 megabytes in a gigabyte of memory.

1 1-1

1.11 Yes, in general. Usually when the program needs a certain amount of memory to run and the available memory is less than that amount; a lot of extra operations are done to use the available memory step by step to the immediate needs and temporarily storing the other runtime-content of the program elsewhere. Once the available memory is more than what is needed for the execution any further increase in the memory size won’t affect the performance.

On the other hand if the available memory is less than a certain critical size then the program may not even execute.

1.12 As the computers began to be mass produced at cheaper cost,they were used for more complex applications than just to interact with a few I/O devices.

This led to the development of complex software. As the length of the programs increased it became too tedious to write them in the low level languages without errors. For this purpose high level languages emerged which had data-structures and programming paradigms which are closer, in principle, to the structure of the solution than the framework of implementation on machines. For example it is nearly impractical to write a complex web-server running a database in a low level language with the regular applications of today's transactions.

Along with the development of complex programming structured software another important evolution of computers are in small, embedded, mobile, remotely operated computers doing some very specialized jobs. These are running on very low power with extreme restrictions on memory and processing power. It is a very significant demand to have extremely optimized programs using each resource minimally to do the job. In these cases, the generic software compiled machine code of a very high-level-language would be wasting a lot of resources. Therefore the low-level-languages have a lot of relevance today in running these devices.

1.13 The high level languages are strongly suitable to 1. Write long and complex programs 2. Write programs which are closely reflect the solution to the problem being solved than the machine implementation of the solution 3. To write programs and debug it using debuggers 4. Write programs which run on different platform with a very little or no changes (portability) 5. Write programs which are safer, so that they won’t crash the whole system if they have a bug

1-2

6. write programs which are suited for security, so that the program access only that memory which it should and wont tress pass into other parts of memory and does not allow other programs to access its memory so on ...

The high level languages have the following disadvantages.

1. The programs when converted into machine code are usually way longer than the optimal length for the task they are doing.

2. The programs will be not using the machine instructions optimally.

3. The programs waste lot of memory and time by taking steps not necessary.

So on...

The low level languages have the following advantages.

1. The programs would be compact in terms of instruction usage.

2. The programs use very less memory 3. The programs are very fast.

4. The programs in general tend to use all the hardware resource available very efficiently.

So on...

The low level languages have the following disadvantages.

1. The programs must be short. As the length increases it becomes hard to keep track of all the things going on.

2. Usually debugging will be difficult.

3. The programs are usually not portable to other platforms.

4. Many advanced programming paradigms are difficult to be used and may not be convenient to implement.

So on …

In the foreseeable future there is a place for both high-level-languages and lowlevel-languages. There is continuous development of new programmable hardware using low level languages and there are very sophisticated and complex software being built over the general computer network environments, which are suitable for programming in high level languages.

1-3

1.14 The listings below are observations about the features as of this writing.

These features change rapidly.

No.

Feature

Tablet PC

Laptop

1.

Hardware support

It is basically made to work on its own. The touchscreen is the primary I/O device.

Others are optional.

Supports fewer devices connecting through non-USB ports. Has electronic memory. Not much upgrade options.

Basically made to work on its own and as a control center.

Screen/Keyboard combo is the primary I/O. Supports more devices with multiple types of ports. Has memory drives.

Upgrade options are prevalent.

2.

Performance

Primarily used as an interface for web application and lightweight audio visual entertainment. Very light weight local computation is the norm.

Primarily used as a computational, software-development and controlling device.

Locally supports medium range computation and heavy duty gaming.

Has larger memory.

3.

Software

Usually has slimmed down OS and applications.

Have full blown version applications with more features.

4.

Platform

Platform for use of software. Not convenient for development of fullfledged software development.

Platform for softwaredevelopment. Runs development environments and wider range of installability of software.

5.

Primary Utility

As a mobile interface for person to the cloud and personal computational space.

As a workhorse for personal computational space and controller of primary presence in the cloud.

1-4

1.15 “Apps” are a colloquial abbreviation for applications. They are usually referred to the applications built for Tablet PCs and smart phones. They run on the specific operating system running on the hardware of smart phones or Tablet PCs for which they are developed. They accomplish specific tasks done on these platforms. Some of them are free to download from their developers while others are available at a cost. Some Apps are even open source, so that users can modify them to suit their own needs.

The Apps use the Application Program Interfaces (API) provided by the operating system running on the hardware of tablet PCs or smart phones underneath them. Since only through these APIs they are able to use the hardware underneath to run, these APPs are tied down to these APIs for functioning. They cannot operate using different APIs to access the hardware.

Thus an App developed for one smart phone may not work on another. They have to reprogram the App to use a different set of APIs. This is called porting an APP.

1-5

Chapter 2 NUMBER SYSTEMS AND CODES

2.1

(1) Bass 3 (a) (245) io 3 3 3

3 3 3

= (?)3

~ Ill 19

~

l!.

0

(b)

~

1153

2

lg

0

3 3

lU

3

l!.

0 2 2 1

~ 0

= (1000 02):s

C? h

(461) io = 3 3 3

(c)

2 0 0 0 0 1

=(122 002):s

(76.S )io = (?)3 3

3 3 3

176 ~

,~ g 0

(d} (46.4 5)io '3 3 3 3

11§.

IJ2 IS

I!.

0

1 1 2 2

r

l

.5 X

3

*repe ats

1.5

=(221 1&1)3

= (?)3 .45

H

X

3

1.35 X

3

1.05 X

3

0.15 X

0.45

3

*repe ats = ( 1201. 1100) 3

2 2-1

(e)

(23 1.7 8)1 0 = (?) s

.78

123 1

3 3

l1.1.

0 2

~

1

~

3

i

.£.• 34 X

3

1.0 2

2 2

0

3

X

X

3

_Q. 06 X

3

0.1 8 =(2 212 0.2 100 . .. )3

(f) (10 23. 25) 10 = (?) 3 3 3 3 3 3 3 3

j

0 2 2

1

.25 X

3

_Q_. 7 5 X

3

ire pe ats

2.2 5

0

1 1

=(1 101 220 .02 )3

(2) Bas e 5 (a) (24 5)i o = (?) s 5 5 5 5

124 5 149

I~ 11 0

(b) (46 l)i o

s s s s

!46 1 ~

U& ~

(76 .5) io 5 5 5

H

=(3 321 )s

= (?) s

(76 115

1

~

0

0

=(1 440 )5

= (?) s

0

(c)

n 3

r l

.5 X

g.s

5

*re pea ts

=(30 1.2 )s

3 2-2

(d)

= (?) s

( 46. 45 )i o 5 5 5

.45

146

Hl

Ii 0

X

5

2.25 X

5

*repe ats

1. 25

=(141 .21)5 ( e)

= (?)s

(231.7 8)10 5 5 5 5

.78

l7ft

X

n

6

·~

0

5

3.90 X

5

.i_. 50 X

5

*repe ats

2.50

=(141 1.342) s

( f)

5 11023 5 1204 5 liQ_ 5 5·

~0

(3) Base 8 (a) (245)i o 8

8 8

t24s 130

@.

0

(b)

= (?) s

(1023 .25)io 3 4 0 3 1

l

.25 X

5

.1- 25

*r epeats

=(130 43.l)s

= (?)a

n n

=(36S) a

(46l)i o = (?)e 8 8 8

1461

fil lI 0

=(715) e

4 2-3

Cc-) _(76 . 5)1 o 8 8 8

~·

4

l!.

1 1

0

(d)

= (?)e

r l

.5 X 8

4.0

=(1 14. 4)a

C46. 45 ho = (?)e 8 8

.45

q

116 ~ 0

X 8

J.6 0 X 8

4.8 X

8

§_. 4 X

8

3.2 X

8

*re pea ts

1.6

=(56 . 346 31 )e (e)

(23 1.78 )10

= (?)s

:~

.78 X

8

§. 24

8~ 0

X

8

1., 92 X

8

1_. 36 X

8

1-_. 88 =(3 47.6 172 ... )s

= (?)s

(f) (10 23.2 5)1 0 8

11023

i1 0

l

7 7 7 1

.25 X

8

2.0 0

=(1 777 .2)s

5 2-4

. ( 4) ,::1 9~ .J6 .( a )" (2 4 5)t" o = (?) u.

16 16

ru lli

5 15

0

(b)

= (? )i 6

(46 1)io 16 16 16

(c)

\461 I?.§.

!.

0

13 = 12 = 1 =

(76 .5)1 0

= (?)1 6

16 16

n

=(F S)i5

=(1 CD) i6

l7§. ~ 0

(d)

1

= 5 • =F

.5

l

12 =C r 4 = 4

X

16

8.0

=( 4C. B)i 6

(46 .4S ho = (?h 6 16 16

146

~ 0

14 = 2 =

q l

.45 X

16

7.2 X

16

*re pea ts

3.2

=( 2E. 73 )i 5

= (?)1 5

(e) . (23 1.78 )10 16 !231 ll_i 16 0

7 - 7 14 : E

.78

II

16

X

(C= ) 12.4 8

16

X

(7= )

1_.6 8

16

X

(A= ) 10.8 8 =(E 7.C 7A ... )u

(f)

(10 23.2 5)1 0

= (?)1 ,

l

.25 X

16

4.00

=(3 FF. 4)1 s

6 2-5

2.2

2.3

Base

7

10,

0, 1 , 2 , 3, 4 , 5 , 6, Base 9 0, 1 ' 2 , 3 , 4 , 5, 6,

7'

Current Odometer reading is

12,

l l ,

8,

13,

15, 16,

13,

12,

11,

10,

14,

14 ,

20

15

(24516) 8

= 2 X 84 + 4 X83 + 5 X 82 + 1 X 81+ 6 X 8° = 2 X 4096 + 4 X 512 + 5 X 64 + 8 + 6 = (10574) 10

Since (23) 10 = (27)8

8 \23 8 \2_. 7 l_Q_ 2

the new reading will be: (24516) 8 + (27)8 = (24545)8

2.4

(24516)& = (?)16 Added bit Expanding each digit in to 3 bits:

=

J

~~

2

9

4

E

In 5 digits the reading is: 0294E. Since (23) 10 = ( 17) 16 ,

the new reading is (0294E) 16 + (17) 16 = (02965\6

7 2-6

2.5

( 1) on e)s com ple me nt 011 01 (a) 100 10 001 101 -> --(b) 110 010 11 01 01 0 > --(c) 001 010 1 01 00 1.1 01 0 > --(d) 10 11 0.0 10 1 00 10 .00 11 > --(e) 11 01 .11 00 > 00 01 01 . 110 0 (f) 11 10 10 . 001 1 ----- > 01 10 .11 10 (g) 10 01 .00 01 00 10 11 .10 11 (h) 11 01 00 .01 00 --- > ,, --01 01 00 1.0 00 ( i) 10 10 11 0.1 11 ----,"',

( 2) (a)

tw o's com ple me nt 100 10 --- > 011 0.L ~

(b) (c) (d)

(e) ( f) (g)

(h) (i )

2.6

l

t <- -- com ple me nt eac h bi LSB t.he <- -- add l to

01 11 0 :: 001 110 --- > 001 101 + l 010 110 -: 110 101 1 --- > 11 01 01 0 + 1 001 010 1 : 01 00 1.1 01 1 --- > 010 01. lOJ .O + 1 101 10. 01. 01 10 .01 00 --- > 00 10 .00 11 + 1 = 00 11 01 .11 00 01 1. 110 0 + 1 = 00 01 01 .11 11 10 10 .00 11 --- > 000 1.0 11 10 .11 --- > 01 10 .11 10 + 1 = 01 10 01 .00 01 t) 0 l O 1 l ..!. 1 0 C• 1 = + 11 .10 00 10 11 11 01 00 .01 00 0 .l O C, l . 0 0 1 > 01 01 00 1.0 00 + 1 = 0 1 10 10 11 0.1 11 - - - ~ ---:')

ni ne 's com ple me nt (a) 46 5

53~ (46 5)9 = 10 3 -(4 65 )10 -l= (b) 098 67_ 0-1 ~9 01 32 09 86 7)9 = 10 5-( 09 86 7)1 (c) 42 67 8 0-1 =5 73 21 (42 67 8)3 = 10 5-( 42 67 8)1 (d) 89 76 -1~ 10 23 (89 76 )9 :: 10 4-( 89 7b )to (e) 42 3.7 6 6)1 0-0 .01 =5 76 .23 (42 3.7 6)9 = 10 3-( 42 3.7 (f) 56 1.8 76 76 )10 -0. 00 1= 43 8.1 23 (Sb l.8 76 )9 = 10 3-( 56 1.8 (g) 46 3.9 0 0)1 0-0 .01 =5 36 .09 (46 3.9 0)9 = 10 3-( 46 3.9 (h) 17 86 .96 7 2 4 6.9 67 )10 -o. 00 1~ s21 3_ 03 (17 86 .96 7)9 = 10 -(1 7B (i) l23 56 .07 8 21 5 56 .07 8)1 0-0 . .00 1= 87 64 3.9 (12 35 6.0 78 )9 = 10 -(1 23

8 2-7

Ten's complemen t (a)(465)10 =103-(465 )10=535 (b)(09867) 10=105-(0 9867)10=9 0133 (c)(42678) 10=1QS-(4 2678)10=5 7322 (d)(B976)1 0=10 4 -(8976)10= 1024 (e)(423.76 )10=103-( 423.76)1 0 =576.24 (f)(561.87 6)10=103- (561.876)1 0=438.124 (g)(463.90 )10=10j-(4 63.90)10= 536.10 (h)(l786.9 67)10=10 4 -(1786.967 )10=8213. 033 (i)(l2356.0 78)10=10S -(12356.07 8)10=8764 3.922

2.7

(a)

x+y

xxy

x-y

1101010 + 10111 10000001

1101010 10111 1010011

1101010 10111 1101010 1101010 11010.10 0000000 1101010 100110000 110 X

x/y

(b)

11010 ;> 10111 qi =1 ;subtract 1101010 -10111 00111 < 10111 qz=0;do not suh t, ·act 00111 - 10111 01110 < 10111 · 93 =0; do r,o t subtract 01110 10111 1110 ~ remainder 100 ~ quotient 101101 x-y 101101 x+y 1111 + 1111 11110 111100

xxy X

101101 1111 101101

101101 101101

101101 .

1010100011

x/y

1011 < 1111 q1=0;do not subtract 101101 -1111 10110 > 1111 q2=l;subt ract 10110 - 1111 1111 > 1111 q3=l;subt ract 1111 1111 0 ~ remainder 011 4-- quotient

9 2-8

{o)

x+y

1001 xlll l 1001 1001 1001 1001 10000 111

xxy

x/y

( d)

x+y

1001 -1111 0110 ~-> -QllO (x <y)

x-y

·1001 +1111 1100 0

1001 < 1111 1001 -1111 1001 ~ rema inder 0 ~ quot ient x-y

110.1 1 + 10.11 1001 .10

x*y

q1=0 ;do not subt ract

110.1 1 10.11 100.0 0

110.1 1 10.11 110 11 1101 1 00000 11011 10010 .10 01

X

x/y

.

-

1101 > 1011 q1 = 1; subt ract 110 11 101 1 0101 < 1011 q2 =O; do not subt ract 01 01 10 11 " 1010 < 1011 q1 =O; 1 010 1 .011 10100 > 1011 q, =1; subt ract 1 0100 1011 1001 0.100 1 ~rem aind er ~ quot ient 10.01

10 2-9

( e)

x+y

x-y

1110.101 + 1011. 100 11010.001

1110.101 - 1011.100 0011.001

1110.101 1011.100

X

0000 000 00000 00 111010 1 1110101 1110101 0000000 1110101 10 1 0 0 11 o.o O1 10 0 x/y

-

•

1110 101 1011 100 011 0010 iOl 1100 11 00100 10 11100 0 010000

> 1011100

q1=l; subtract

0110010 < 1011100

q:z =O; do not subtract q3 = 1; subtract

1110101

1100100

> 1011100

0010000

< 1011100

q, =O; do not subtract

0 .010 ~ remainder 1. 010 ~ quotient ( f)

x+y

+

x-y

1011.00 1100.00 10111.00

1100.00 - 1011.00 0001. 00 =-0001.00(X<Y)

1011.00 1100.00 10110000 00 101100 10000100.00 00 X

x/y

-

101100 < 110000 1011 • 00 1100 00 1011000 > 110000 1011 000 110 000 1010000 > 110000 101 0000 11 0000 10 0000 10.00 4 - remainder 0.11 4--- quotient

q1=0; do not subtract subtract qz =1; q3 =1;

II

11 2-10

2.8

(a )

x* y

53 3 x2 34 25 54 ~ 20 21 12 66 15 15 64 .+- -pr od uc t

x/ y

(b )

x+ y

53 3 -2 34 27 7

x- y

53 3 +2 34 76 7

x+ y

sc ra tc h ea d (1 4) e 3x 4= 3x 4= (1 4) s Sx 4= (2 42 e 25 54 (l l) a 3x 3= 3x 3= (l l) s 5x 3= {1 72 e 20 21 ( 6) 8 3x 2= ( 6 )s 3x 2= 5x 2= {1 22 a 12 66

2

23 4

53 3 147 0 43 46 53 7 + 23 4 46 77 3

x- y

►

sc ra tc h pa d

46 53 7

(3 4) a 7x 4= (1 4) a = 23 25 74 "- -- -- -3 x4 (2 4) e 4= 5x 16 40 35 6x 4= (3 0) a 11 52 76 s_ _ 4 X 4 = (_2_0...,)__ 13 62 27 44 ~p ro du ct -- -2 32 57 4 (25 )_a 7x 3= (l l) s 3x 3= (1 7) a 5x 3= 2) e (2 3= 6x s_ _ 4_)_ (_1_ = 3 4x 35 40 16 6) a (1 2= 7x )e (6 2= 3x )a 12 ( Sx 2= 6x 2= (1 4) a 4x 2= (1 0) a 17 3 -- -- 11 52 76 23 4 46 53 7 23 4 23 13 22 04 10 77 72 4 15 3 X

x/ y

46 53 7 23 4 46 30 3

23 4

12 2-11

(c)

533

x-y

26

x+y

-

+533 561

26

505 --).- SOS (x<y )

scra tch pad

. 26

6><3= (22) a 2x3= (6) 8

x533 102 102 156

' " 1672 2 +,-p rodu ct

"-----102

6x5= {36 )a 2x5 =(12 ) 8

----156

0

x/y

~

533

26 ;

( d)

x+y

123 .2 + 234 .0 357 .2

x-y

234 .0 - 123 .2 110 .6 =-11 0.6( X<Y )

scra tch :Qad 123 .2 2x4 = .0 X 234 3x4 = 000 0 '""< ---- -. 2x4 = 515 0 lx4 = 3716 2464 .

2x3 = 3127 3.0 0 3x3 = 2x3 = lx3 =

x/y 234

Oct al 10 14 10 4 5150 6

11 6

3 3716

0.4 123 .2 234 123 .2 116 .0 5.2

13 2-12

( e)

x+y

234.6 - 156.7

x-y

234.6 + 156.7 413.5

Q55e7

Octal scratch pad 52 6x7 34 = ~<----- . 4x7 25 3x7 = ~1~6____ 2x7 = 1 L..----- --21112

234.6 X 156.7 2111 2 16544 14176 2346

=

44

6X 6 :

4 1 7 4 3.5 . 2

= = = 6x5 = 4x5 = 3x5 = 2x5 =

30 22 14 16544

4x6 3x6 2x6

156.7

(a)

12

14176

1.3 234.6 156 .-1 55.70 51.45 4.23

x/y

2.9

36

24 17

!CF

x-y

11 -E:-- carry lCF

x+y

-

86 119

+ 86 285

scratch pad

lCF

x*y

X 86 ADA

+-<-----,

13E5

(SA)i5 Fx6= Cx6= ( 48) 16 lx6=__{_§l15 ADA

1492A

(AS)i 6 Fx8= Cx8= (84 h 6 lx8=__{,tl15

.__ _ _ _ _ _ 13ES F

x/y 86

(b)

x+y

+- quotient

ficF l!fil. lA ~ remainder x-y

1859A + C23 lClBD

1859A - C23 1A977

14 2-13

1BS9A X C23 S20C E <--P l 3683 4 <--P 2 <--P 3 1483 38 14BFOCOE

x*y

scra tch ead Ax3= 9x3= Sx3= 8x3= lx3= Ax2= 9x2= Sx2= Bx2= lx2=

hex adec ima l lE 18 F 21 3 520 CE( Pl) 14 12 A

16 2

36B 34(P 2) 78 6C 3C 84 C 148 33B (P3)

AxC= 9xC= SxC= 8xC= lxC=

x/y C23

(c)

24 1BS9A 1846 313A 308C AE

x+y

86 +lCF 285

X*Y

86 xlCF AAA 888 86 1492 A

lCF -86 119 --> -119 (x< y) scra tch ead 6xF= 8xF= 6xC= 8xC= 6xl= Bxl= 0

x/y !CF

hex ade cim al SA AS AAA( Pl).

48 84 888 (P2) 6 B

86(P 3)

<-- - quo tien t

~ B6 <-- - rem aind er

15

2-14

( d)

x+y

x*y

4321 - 2ECD 1454 =-1454 (X<Y)

x-y

2ECD + 4321 71EE 2ECD X 4321

2ECD

7D9A (Pl) (P2) 8C67 (P3) BB34 C47AF6D

scratch :ead Dx2 = Cx2 = Ex2 = 2x3 = Dx3 Cx3 Ex3 2x3 Dx4 Cx4 Ex4 2x4

= = = = = = = =

Hexadecimal

lA 18 lC 6

7D9A

(Pl)

27 24

2A 6 8C67 34 30 38

(P2)

8

BB34

(P3)

0

x/y

4321

um 1

2ECD

16 2-15

( e) x+y

x*y

234F .16 x 456E .00 0000 00 0000 0 0 1EE5 334 D3DA84 B08B6E 8D3C 58 8C37 CE97 4 00

.

456E .00 - 234F .16 221E .EA =-22 1E.E A(X <Y)

x-y

234F .16 + 456: E.00 68BD ol6

(Pl) (P2) (P3) (P4)

scra tch :Qad 6xE = lxE = FxE = 4xE = 3xE = 2xE = 6x6 = lx6 = Fx6 = 4x6 = 3x6 = 2x6 = 6x5 lx5 Fx5 4x5 3x5 2x5

= = = = = =

6x4 = lx4 = Fx4 = 4x4 = 3x4 = 2x4 =

x/y

456E

hexa deci mal 54 E D2 38

2A lC 1EE5 334 24 6 SA 18 12 C D3DA84 lE 5 4B 14 F

(Pl)

(P2)

A

B08B 6E 18 4 3C 10

(P3)

C

8

8D3C 58

(P4)

0.82 234F .16 456£ .

234F .1 22B 7.0 98.1 6 BA.DC D.3A

17 2-16

2.10

a)

2 2

1234 1117

2

~ ~

2 2 2

0

1

0 1 0

114

II I~ l!.

2 2

1 1

=(111 0101 0)2

1

0

(b)co nver t to base 10 (3345 ) 6 =3x63 +3x62 +4x61 +5x60 =648+ 1O8+ 24+5 =(785 )10 conv ert to base 2 2

pas

2 2

~92 1196

2 2 2 2

9 4 12

2

2

1

H 0 0 0

1

1

0 0 0 1

0

1

,3

=(110 0010 001)2

(c) conv ert to base 10 (875) 9 =8x9 2+7x 9l+Sx 90=6 48+6 3+5 =(71 6)io conv ert to base 11 11 17,16 1 65 11 11

~

1~

i I

=(5 10 l)i1

(d)(O .3212 ) 4 =3x4 -1+2x 4-2+l x4-3+ 2x4-4 =3 -4 + -162 + -641 + 2562 =230 =(115 ) 12810 256

(e) conv ert to base 10 (87.3 5)9= 8x9l+ 7x90 +3x9 -l+5x 9-2 =72 +7 +3/9 +5/81

=( 79 3 2 / 8 l )i O

18

2-17

con ver t to bas e 11 11 11

~J_

.39 5

n

0

11

X

4.3 45 11 X 3.7 95 11

X

~.7 45 11

X

7.9 95 11

X

10. 945 11

X

10. 395 11 X 4.3 45

*re pea ts

=(7 2.4 387 10 10 )i l ..

2.12

11 01 00 .00 10 10 10 (a) 2 2 0 0 1 2 3 =(2 310 .02 2)4 (b)

( c)

3 4 011 0 00 000 1 01 1 011 10 010 - -0 - 3 0 5 3 5 2 =(2 530 503 )e _

1

8

A

7

4

3 . _2 _ _

E

5

4 --1 01 00

100 9

010 0 11 10 0 111 4

.

7

4

=(4 E7 .94 )i6 (d)

0 101 1 11 10 . 010 0 000 1 100

1 -- -000E 8 1

4

1

8

=(1 BE .41 Bh 6

2.11

t 2 ber is first expanded in to 2 digits; the righ Since 9 = 3 , each digit of the base-9 num Hence, left most digit will have a weight of 3. most digit will have a weight of I and the = ( 02 12 2 1 11 )3 C2 5 7 4 h

19

2-18

2.13

( 130 )x =( 28 )lo l*x2+ 3*x +O*xo = --> x2+3x-28=0 -->(x-4)(x-7) =0 x=4 or x=-7 since xis positive.

We pick up x= 4

2.14

(a)

(c)

(d)

(b)

11101 + 1111 101100 + 1011 110111

11001101 -101 010 -101 101 -101 001 -101 010 -101 101 -101 0 101001

111000 -10101 100011

110>101

q1=l;subtrac t

010<101

q2=0;do not subtract

101>101

q3=l

001<101

q4=0 ·

010<101

qs=O

101<101

q5=l

<--remainder <--quotient

11010 xllOOl 11010 00000 00000 11010 + 11010 1010001010

20 2-19

2.15

(a) two's complement 1011010 - 10101

2 1 s complement 1011010 1101011 11000101 : 1000101

10101 -1011010

0010101 +0100110 0111011

=-(1000101)

(b) one's complement 1011010 - 10101

10101 -1011010

l's complement 1011010 +1101010 11000100 1 + =(1000101) 1000101 0010101 +0100101 0111010

=-(1000101)

21 2-20

2.16

(a) nine's complemen t 1875 -924

924 -1875

9's comelemen t 1875 +9075 10950 + 1 =951 0951 0924 +8124 9048

=-(951)

(b) ten's complemen t

1875 -924 924 -1875 2.17

(a)

(b)

(c)

(d)

(e)

2.18

(a)

l0"s comelemen t i875 +9076 10951 =951 0924 +8125 9049

=-(951)

113 -87

0 1110001 +1 0101001 10 0011010

=+ C0011010 h

87 -113

0 1010111 +1 0001111 1 1100110

=-(0011010 ):2

43 +26

0 0101011 +0 0011010 0 1000101

=+(1000101 )2

96 -22

0,1100000 +1 1101010 10 1001010

=+ ( 1001010)2

0 0101110 +1 0110011 1 1100001

=-(0011111 )2

46 -77 7256 23 X 26012 <--Pl 16534 <--P2 213352

scratch ead octal 22 6x3= 17 5x3= 6 2x3= 25 7x3= 26012 <-- Pl 14 6x2= 12 5x2= 4 2x2= 16 7x2= 16534 <--P2

22

2-21

57) e (b) (AF )15 =(1 010 111 1)2 =(2 56 x25 7 502 ~ P l 346 ~P 2 ~P 3 134 )a 562 (17

scr atc h pad 6x7 = Sx7 =

oc tal 52 43 502 ~ P l

6x5 = 5x5 =

31

6x2 = 5x2 =

14 12 134 t-- P3

36 346 -(-- -P2

(17 562 )a= (00 111 110 111 001 0)2 =(1 331 302 )4 2.19

10) x25 (a) (ll Ol 0.0 10 )2 = (0. 110 100 sig n bit = o 0) exp one nt =5+ 127 =(1 000 010 fra cti on =lO lO 010 0 ... 0 31 8 9 0 1 . . . . .

00 001 101 j 00 lo j 100 001

ol

(b) 2 2 2 2 2 2 2 2 2

432 216 108 54 27 13 6 3 1 0

0 0 0 0 1 1 0 1 1

.26 2 0.5 2 X 2 1.0 4 X 2 0.0 8 X 2 0. 16 X 2 0.3 2 X 2 0.6 4 X 2 1. 28 X 2 0.5 6 X

010 100 011 1)2 (43 2.2 6)1 0=( 110 110 000 .01 000 l)x 29 =(0 .11 011 000 001 000 010 100 011 sig n bi t= O 00) 2 exp one nt =9+ 127 =13 6=( 100 010 011 1)2 100 010 000 001 fra cti on =(1 011 000 31 0 1

8 9

010 101 100 010 001 101 100 000 100 001

23

001 11

I

2-22

(c)-(10100111 .1001) 2 = -(0.10100111 100l)x2 8 sign bit =l exponent= 8+127=135=(1 0000111)2 fraction =(01001111001 0 ... 0)2 31 8 9 0 1 o I ...

1111000011110 10011110010 (d)-(236.77)10 =-(11101100. 110001010001 1110)2 =-(0.11101100 110001010001 1110)x2 8 sign bit =1 exponent=8+1 27=135=(1000 0111)2 fraction=(ll01 10011000101 00011110)2 31 8 9 0 1 11 110000111 j 110110011000 10l00011110 I 2.20

( 1) The entry in row two column two is in error. ( 2). 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1

2.21

0

1 2 3 4

5 6 7 8 9

2.22

0 1 2 3 4

5

6 3 -1 0 0 . 1 0 0 0 0 1 1 0 1 1 0 1 0 1 1 0 l 0 0 1 0 0 1 1 1 1 1 0 3 0 0 0 1 1 1

1

1

0 1 l 0 0 l 0 0

2 -1 1

0 0 1 0 1 1

1 0 0 1 1 0

<--weighted

1

<--weighted

1 1 0 1 0 0

2.23

(a)(OlOO 1001 0101 Olll)bcd=(4 9 5 7)bcd (b)(OlOO 1001 0101 0111)2 :(18772)10 (c)Excess-3 = (1 6 2 4) (d)ASCII Code=) 7

2.24

(a)(356)io =(101100100)2 =(0000 0001 0110 0100) in 16-bit register (b)(356)bcd=( 0011 0101 OllO)bcd =(0000 0011 0101 0110) in 16-bit register (c)(AI)ASC!r= (1010 0001 0101 OOOl)ASCII =(1010 0001 0101 0001) in 16-bit register

24

2-23

2.25

(a)(7 46)io =(Ol ll 0100 OllO) sco (b)(74 6)10= (1011 10101 0)2

(c)(74 6)10= (0101 0111 01010 100 01010 110)A SCII

2.26

( a ) Sign bi t =0 Expon ent=1 00000 10=(1 30)10 =127+ 3 Binar y=(l.1 000 OOlO )x23 =(110 0.000 1)2 (b)Si gn bit=l Expon ent=O l1110 00=(1 20)10 =127+ (-7) Binar y=(l.O l0001 10)x2 -7 =(0.0 00000 10100 011)2

2.27

Corre ction facto r (i) -0011 if sum~ 9 0011 0 Ex. + 0100 + 1 0111 1 - 0011 0100 (ii) 0011 if sum > 9 0110 3 Ex. + 1100 + 9 1 0010 12 0011 0011 0100 0101

25

<--- minus 3

<--- add 3

2-24

2.28 a. Fixed point: Implementation dependent. But usually with one bit used as a sign, we get -263 to 264.

Floating point: sign(1)exponent(11)mantissa(52) is the bit distribution for representation.

So, the range is 4.9 * 10-307 to 1.8 * 10+308 b. Floating point has the larger range. c. When the values are confirmedly integers, fixed point representation gives faster operations

2.29 a. sign(1)exponent(5)fraction(10) is the format.

0 0 0 10 1110110011 b. 3. 69921875 c. We can see that in both cases, a rational number in one system is also a rational system (a number with a terminating or repetitive fractional part) in another. But the representation varies in precision depending on the base for a given number of places. d. Since 3.7 is a representable by just one number after the radix point in base 10 number system, it takes non terminating repetitive set of numbers (0011) after radix point in base 2 system.

2-25

Chapter 3 COMBINATIONAL LOGIC

3.1

A= 0, B= 1, C= 1, and D=0.

F= AC'+B ' a. = 0·0 + 0 =0+0 =0 b.

F = A'D + B'C' + BC'+D = 1·0 + 0·0 + 1·0 + 0 =0+0 +0+0 =0

c.

F= BD'(A' + B+ CD)+ C'D = 1·1(1 + 1 + 1·0) + 0·0 = 1(1 + 1 + 0) + 0 = 1(1) + 0 = 1

d.

F = (AB(C+D)')'(A '+B)( C'+BD) = (0· 1(1 + 0)')'(1 + 0)(0 + 1•1) = (1 (1 )')'(1) (0 + 1) = (1 ·0)'(1) (1) =1 ·1 ·1 =1

e.

F = (D +((A+ B)C)') AB'+ C'D (D + A(A'B + CD)) = (0 + ((0 + 1)1)')0·0 + 0·0(0 + 0 (1·1 + 1·1)) = (0 + ((1)1)')0 + 0(0 + 0 (1 + 1)) = (0 + (1 )')0 + 0 (0 + 0 (1 )) = (0 + 0)0 + 0(0 + 0) = 0·0 + 0·0 = 0

a.

Q =X'Z + Y'Z' + XYZ

3.2

X

y

z

xz

Y'Z'

XYZ

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 1 0 0 0 0

1 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1

26 3-1

b.

Q

- tx - Y\tX - Z)\X'- Y'-Z)' A

Y

0

0

0

0

x+I'' X+Z I

0

(X'+Y'+ZT

0

1

0

0

0

0

0

0

I

0

0

0

0

0

0

1

I

0

1

0

0

0

0

1

0

0

0

1

1

0

0

1

0

1

0

0

I

I

I

1

Q: AC',D', + D',(A + C) (A',+ B) n/1

B

C'

D

AC'D'

.4+C

0

0

0

0

0

0

0

0

0

0

0

0

0

0

d

I

0

0

A,+B

D',(A+C)@',+B)

a

0

0

0

0

0

0

0

0 0

I I

0

0

0

0

0

0

0

0

0

0

I

0

1

0

0

1

I

0

0

1

I

0

1

I

1

0

0

0

0

0

0

0

0

I

0

0

I

0

0

0

0

0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

I

0

0

0

0

0

I

1

0

0

0

I

Q: ABC'D t A'+ B' + D'+ BCD A

B

C

D

ABCD

BCD

0

0

0

0

0

0

1

0

0

0

I

0

0

1

a

0

U

I

0

0

0

I

0

t)

I

I

0

0

1

0

0

0

0

0

1

0

0

0

0

0

0

I I

0

0

3-L

1 1

1 1 1

e.

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

0 0 1 0 0

0 0 0 0 1

~w::.·}~t?:

Q = M(N+P)(N'+P)

M

N

p

N+P'

N'+P

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

3.3

a.

TRUE Let L = (X + Y +Z) (X + Y + Z) and R = X + Y Boolean Algebra: L = (X + Y +Z) (X + Y + Z) =XX+ XY + XZ' + XY + YY + YZ' + XZ + YZ + ZZ' = X + XY + XZ + XZ' + Y + YZ' + YZ = X( 1+ Y) + X(Z + Z) + Y ( 1 +Z' + Z) = X(1)+ X(O)+ Y(1) = X + Y = R

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

Z

X+Y+Z

X+Y+Z'

0 1 0 1 0 1 0 1

0 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1

TRUE b.

Let L = A'BC' +ABC'+ BC'D +BC+ B' Boolean Algebra: L = A'BC' +ABC'+ BC'D + BC+ B' = BC'(A I+ A + D) + BC + B' = BC'(1) +BC+ B' = B(C' + C) + B' = 8(1) + B' = B + B' = 1

28 3-3

Truth Table:

A

B

C

D

A'BC'

ABC'

BC'D

BC

<'< ,:;,,,/?}~ '):.;_:;)

0 0 0 0 0 0 0 0

0 0 0

0 0

0

0 0

0 0 0 0 0 0 0

0 0

0 0 0 0 0 0

/.::;\? " ,.-... :

1 1 1 1 1 1 1 1

0 0 0 0

0 0

1 1 1 1

0 0

0 1 1 1 1

1 1

0 0 1 1

1 1

1 1

1

0 1 0 1 0 1 0 1 0 1

0 1 0 1

0 0 1 1 0 0 0 0 0 0 0 0 0 0

0

0 0 1

0 0 0

0

0 0 0

0 0

·o 1 1

0 0 1 0

0 0

'C,;'\':'it•t •••

1

' .•

;,:; :;. ".':

. ,,·,:{' ;,

:ct\:d ·<

'·:;

,. .

i/_. .; ii'/'.:

J'.'."

f;·:·:.. ;;-:

:,,,,:• ..\" " "I; >t,\:; ·.,• ·:x:-;

p_;··•·•'-t:: t

··., !:\

1 1

(}}}',: ,;i ;, }(:: ·•·

0 0 0 0 0 0

'/ '!,'('' 1·,:// ;;

1 1

0

i :,t;, ,,.•·,

'''t> '"• ... :;:; ·.·· Jil'°'-.',:-.·• ..,·,, ... ,.,..

' ./.., 1·•··'.,i\/: <.:,i:'::" :... ,. : .: , e;,,:, ii'\ ...

1, ·,

.,. r,.:.,,,;,·'

.,

.,_

;/ _.·;•·:·

'.'},):> j,L,,::?i

'i</t.

_::: ..,•.,,,· .".·

·/ '·"

}, ,··•.

.•.,.. : ,:,, ·•'•!.'>,. ':,

,i. •:,;_,:

FALSE c.

Let L =A'C+ ABC'+ A'B + AB' and R = B'C+ A'BC

A

B

C

A'C

ABC'

A'B

AB'

0 0 0 0 1 1 1 1

0

0 1 0 1 0 1 0 1

0

0

1 0 1

0

0 0

0 0 0 0

0 1 1 0 0

1 1

0 0 0

0

0 0 0 0 1 0

1 1

1 1

0 0 0 0

0 0

II J:Jf:\'./ ~(qQ:ti I@} t: It \

:+

':'.{ < /.,:: /

1~

~~:s; r,i

B'C

A'BC

0

0

1

0 0

:;{;ti/\

1

Jl1Xt;

0 0 0 1

;t{1?f 0 tY;l l::f? 0

0 0 0 0

:tf0,1i_: :;

ro<P

1£:04

1

...

FALSE Let L =PR'+ Q'R' +PR+ Q'R and M = P + Q + R

d.

p

Q

R

0

0 0

0 1

1 1 0

0

0 1

1

0

1 1

1 1

0

0

1 0 1 0 1

Q'R'

PR

Q'R

0

1

0 0 0

0 0

0 0

0 1 0 0 0

PR'

1

0 1

0

0 1 0

0 0

0 0 0 1

0 1

1

0 0

29 3-4

TRUE e.

Let L = ((P + Q')(P'+Q))' and R = P ffi Q Boolean Algebra: L = ((P + Q')(P~Q))' = (P + QJ + (P' + Q) = (P'Q) + (PQJ = P ffi Q = R I

I

Truth Table:

p

Q

P+Q'

P'+Q

0 0 1 1

0 1 0 1

1 0 1 1

1 1 0 1

3.4 a. b.

C.

d. e. f. g.

TRUE FALSE FALSE TRUE TRUE FALSE TRUE

3.5

d. e. f. g. h.

canonical SOP normal POS canonical POS none normal SOP none normal SOP canonical SOP

a.

F(P, Q, R) = PQR' + P'R' + Q' R'

a. b.

C.

3.6

p

Q

R

PQR'

P'R'

Q'R'

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1

0 0 0 0 0 0 1 0

1 1 0 0 0 0 0 0

1 0 0 0 1 0 0 0

0

1

30 3-5

Canonical $Op: F(l Canonical pOS: F(p, 8 + O'+ R) ^e,:[;Y:;

i

^3f,;i8:';,l4: n,+ R,xp

, B, C, D) -- A'B'(C + D) + C'(A + B'C) A

B

0

0 0 0 0

U

0 0

lJ

D

A'B' 1

0

0

1

1

1

1

1

1

1

1

1

0

1

1

0 0 0 0 0 0

0 0 0 0 0 0

1

1

a

1 1

1

0

1

1

1

0 0

0 0

0

0

1

1

0 0 n

1

0

0 0 0 0 0 0 0

0 0 I I

1

1 1

1

1

1

1

I

1

1

0

0

0

0

1

0

1

0

0

0 0

U

1

0

'l

I

I

1

,|

1

C'(A+B'C)

0

0 0

I

A+B'C'

U

1

I

A'B D)

0 1

0 0

D

1

1

1

'l

1 1 1

0 1 1

't

0 0 0 0 0 0 0 0 0 U

4

1

U

l

1

1

1

{I

0 0

1

'l

1

1

1

1

U

0

1

0

I

.'0

0 1

tu"ooi"ulibs.rrz , B, c, D): (A + B' + c'+ D)(A + B' + c +D')(A+

B'+ C'+ D)(A+ B'+ C',+D')(A'+ B + C',+ D)(A'+ B +',C +D')(4',+ B' + C'+D)(A' r B'+ C'+ D')

3-6

,B,q=(AB+ABC

d

A

B

C

D

AB

ABC'

AB+ABC'

(BD)'

0

0 0 0 0

0

0

U

0

U

I

n

1

U

0

1

0

1

0

0

1

o

1

1

n

0

0

0 0 0

1

0

1

0

0

0

0

t-

1

1

0

0 0 0 0 0 0

0

0

1

1

1

1

0

0

U

0

0 0 0

0 0

0 0

1

U

'1

0 0 0 0

'l

1

0 0 0 0

1

0

1

1

1

1

1

.1,:

0

n 0 0 0 0 0 1 1 1

1

1

1

{I

1

1

0

1

0

1

0 0

1

0 0 0 0

0 0

0

1

1

I

1

0

a

o

1

0

J

1

1

0

1

0

TJ

I

1

1

1

I

I

1

I

n

I

Canonical SOP: , B, C) = ABC'D'+ A,BCD' Canonical POS: F(A, B, C, D): (A + ' + C + D)(A +B + '+ D')(, + B + c' + D)(A',+ B + C', + D')(', + B' + C+ D)(A + B', + C + D')(A+ B' + C', + D)(A+ B'+ C '+D'XA'+ B+ C+ D)(A'+ B+C+D')(A'+ B+ C'+ D)(A' + B + C',+D',)(A', + B', + C +D')(A', + B' + C', + D')

37

X,Y,Z=X(Y'+Z\+ X

Y

Z

(Y'+Z')

0 0 0 0

0

0

1

U

{I

1

1

0

1

I

I

0

xff ')

1

0 0 0

0

U

I

,' 0 n 0 1

1

0 0

1

1

I

1

n

1

1

0 0 0

1

1

0

0

1

1

1

Y,

I

1

1

4 = Im(3, 4, 5, 6,7)

0 0

t

1

d.

F{A, B, c: = (AB+ ABC'1(BD)

1

A

B

C

D

AB

ABC'

AB+ABC'

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

1

1

1 0 0

1

(BO)' l'.{';}fi:fi!

1 1 1 1 1 0

1 0 1 1 1 1 1 0 1 0

1 1

Canonical SOP: F(A, B, C) = ABC'D' + ABCD' + B' Canonical POS: F(A, B, C, D) = (A'+ B' + C' + D)(A' +B' + C' + D)(A' C+ B+ D)(A'+ C'+ B+ + C+ D)(A'+ B'+ C+ D)(A'+ B+ C'+ D)(A'+ D)(A I+ B + C + D)(A+ B' + C' + D)(A + B' + C' + D)(A + B' + C + D)(A + B' + C + D)(A + B + C' + D)(A + B + C + D)

3.7

a.

F/X Y Z) = X(Y' + Z1 + YZ ' ' y z (Y'+Z') X 0 0 0 0

1 1 1 1

0 0 1 1 0 0

1 1

0

1

1

1 1 0 1 1 1 0

0 1 0 1 0 1

X(Y'+Z')

YZ

I;;(:, RL\

0 0 0 0 1 1 1 0

0 0 0

'' ... : .. , -.,

•·:.·•··\···

':>'

·;.t':

1

--c,,

,: ·:,

,.

.,,:,

ti

,,

'!<'

0 0 0

11

1

~

~

!>

~

~

1.:fi.;; IS\ ,:'·i' '

F(X, Y, Z) = Lm(3, 4, 5, 6, 7)

33 3-8

F(A, B, C, D) = (B' + C)(A + B + 0)(8' + C' + D) B'+C'+ D' A 8 C D B'+C A+B+D'

b.

0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0

0 0

0

1 1

0

1 1 1 1

0 0

0

1 1

0

1 1 1 1

1 1

0 0

0

1 1

0

0 0

0

1 1

0

1 1 1 1 1 1

1 1 1 1 1 1 1

1

1 1 1 1

0 1

0 1 1 1 1 1 1 1 1 1 1 1 1

0 0 1 1 1 1 1 1

0 0 1 1

0

/ ;(;1 ~ ')·>

:'i

·\ f !~t\ ;() :,;'f

i

::,

',•;

\:,,,:,.,;>'

;: ,; .

., ,,,::,

,,·,., .•.

:::

l' y ,,,

< ·- :;:,.,

'' ,/Ji,' ,,' ·':t. ; ,,,.,::,; •iii

,. "' Id/i1:!

':

.\ h

:?,

,.,· -~

1 1 1 1 1 1 1

.,.

0

.'., '_:'

.

x,~s

,','}'

\/;l tt \:'".~1;,_/:;/. :/,1~J/, ,., ·;

i ',.,,-

'\'"'; ,.

·. ·,;

·.:,?,'"• · ,1Q;/ ,,.. \i ,,.,,.,. ,"::';,,

\'• •tf:\

F(A, 8, C, D) = Lm(O, 2, 6, 8, 9, 10, 11, 14)

c.

F(A, 8, C, D) = nM(3, 5, 6, 12, 14, 15) F(A, 8, C, D) = Lm(1, 2, 4, 7, 8, 9, 10, 11, 13)

d.

F: P, Q, R = PO + R' + P'R P

Q

R

PO'

P'R

0

0

0

0

0

1

0

1

0

0 1 0

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

0 0 0 0 1

0 0

I H:',':<'i!,l:s-:Di"?.:I■

0 0 0 0

F(P, Q, R) = Lm(O, 1, 2, 3, 4, 5, 6) e.

F(X, Y, Z) = nM(3, 5, 6) F(X, Y, Z) = Lm(O, 1, 2, 4, 7)

34 3-9

3.8

F/P Q R) = P'R' + Q(P + R) ' ' D P+R P'R' R Q

a.

I

0 0 0 0 1 1

1 1

0 0

0

1

0

1

0

1

1

0

1

1 0 0 1 1

1

0 0 0 0 0

0 1 1 1

0 1 0 1

1

1

Q(P+R)

\'{~(!/ ;\;

0 0 0 1 0 0 1 1

~ .,

~ ~ 77,

.::,:::,

\'.'.,

ii• ..

'\;·.-

.i:, :.;/:; :;, /;':; ., \~tf

:;;:,:11:\~,/f.i'

F(P, Q, R) = nM(1, 4, 5) b.

F(A, B, C, 0) = AB(C+ 0' + A'C'0 + B'C0 A'C'D A B C 0 C+0' AB(C+0')

0 0 0 0 0 0 0 0 1 1 1 1 1

1 1 1

0 0 0 0 1 1 1

0 0 1 1

0 0 1

1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

0 1 0 1 0 1

0 1

0 1 0 1 0 1 0 1

1

0 1 1 1

0 1 1 1 0 1

1 1 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1

B'C0

0 1

0 0 0 1

0 0 0 0 0 0 0 0 0 0

··':>i

:;'\\ Q',:/Q

0 0 0

:t:\:i DfY

1

,,,

0 0 0 0 0 0 0 1 0 0 0 0

· ,.

,···

'

~'16 '/1

..

;;•. •''J ,:.,.;: :_;,:;; ;/ i·<-"'' .. .~ ...... :..••·

.

.c:

/:.C'~ 1,:y

·.,,,.,. '-'i',:.

~~ <~

l~j

?:!)

.•

F(A, B, C, 0) = nM(0, 2, 4, 6, 7, 8, 9, 10, 13)

c.

F(W, X, Y, Z) = rm(0 , 7, 8, 9, 13) F(W, X, Y, Z) = nM(1 , 2, 3, 4, 5, 6, 10, 11, 12, 14, 15)

35 3-10

d.

F P, Q, R = PO + R' + P'R PQ' R Q P 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 0 0

P'R 0 1 0 1 0 0 0 0

F(P, Q, R) = nM(7)

e.

F(A, B, C, D) = Lm(10, 12, 13, 14, 15) F(A, B, C, D) = nM(O, 1 ,2, 3, 4, 5, 6 ,7, 8, 9, 11)

a.

(X + Y +Z) (X + Y + Z) = X + Y Let L = X + Y +Z X + Y + Z and R = X + Y

3.9

X

Y

Z

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

X+Y+Z 0 1 1 1 1 1 1 1

X+Y+Z' 1 0 1 1 1 1 1 1

L = Lm(2, 3, 4, 5, 6, 7) = nM(O, 1) R= X + Y + ZZ'= Lm(2, 3, 4, 5, 6, 7) = nM(O, 1) Both functions have the same minterms and maxterms.

TRUE

36 3-11

b.

A 'BC'+ ABC '+ BC'D + BC+ B'= 1 A'BC' ABC' D C B A

BC'D

BC

,

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1

-:}ii.;;[} '-' •• ,. :'.:,'

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 .1 0 1

0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0

>

l~·,,:-:-.,-·.t, .

,:'.:;f\-,.,

I ,/>,.•,.'.'\:-

rlif•.::S~l::1i,:i~

~~ ,..

.... .,··:.}

.:\ <( ',.'·./:'' '/ \''··''"

,,,.t'c:.:1t:'.:\t :c Tt/ ··fr1tt.:: }

·,i..:.'"',., "' '. :'.' ,...it /.,,,,:c:,:; .,•_,) ti l\i:\ , ; ic1 .... (il.?(U., ~ l}!;,g·•:i; ,,.,.,,,,,.

m ·1 1 :.

j

.,•,'

...

,..,.

''.',-, //c..~I'!';··, :.:-;:· ,'.:_'' :,

>:/f'' f ;) ,,,:;'. }:_:'.'>•

:.:/\•:S :!i_i,

., ·'

EH:;,,:,:

t:1\\::X:

6, 7) = nMO A 'BC'+ ABC '+ BC'D + BC+ B' = Lm(O, 1, 2, 3, 4, 5, 1 = Lm( 0, 1, 2, 3, 4, 5, 6, 7) = n M() .

Both functions have the same minterms and maxterms TRUE C.

A'C+ ABC '+A'B +AB '= B'C+ A'BC Let L = A'C+ ABC '+ A'B + AB'a nd R= B'C + A'BC AB' A'B ABC' A'C C B A 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1

B'C

A'BC

0 1 0 0 0 1 0 0

0 0 0 1 0 0 0 0

, 7) A'C +AB C'+ A'B +AB '= Lm(1, 2, 3, 4 ,5 ,6) =) = nM(O B'C + A 'BC= Lm(1, 3, 5) = nM(O, 2, 4, 6, 7) maxt erms.

The two functions do not have the same minterms and FALSE

37 3-12

d.

PR'+ Q'R'+ PR+ Q'R = P+ Q +R Let L = PR'+ Q' R' + PR+ Q' Rand M = P + Q + R ,cc•·» Q'R ...,.,..,,. j ;/\· ;:;;:rlt :c: i PR p Q'R' PR' Q R ;',;:y·,;: /t? ",':·_r,· f<,(, 0 0 1 0 0 0 ..

0 ,:. . ...,, :,•/ .. \af:'. ·."r·/ :·: ..,:, ·:,. :,,,, 1 0 0 0 1 0 0 .... ":_•;[ ; :: I 0 0 0 0 0 1 0 ~ 0 0 0 -~ 0 1 1 0 ·( ,,{;-;,_n!

0 0 1 1 0 0 1 1 l I < }/,;, 1 0 0 1 0 1 (\ii ,-;}j'-1 , ::;:/ ; ' c.t! : \' / 0 0 0 1 0 1 ,, ..

1 · " );i?t ,'·{.: ) / ' ;.' ,(: 0 ' ·.: t· 1 0 0 1 1 1 ·.;

,, •

'

..

AC'+ B'C' +AC + B'C = = Lm(O, 1, 4, 5, 6 ,7) = nM(2 , 3) P + Q + R = = Lm( 1, 2, 3, 4, 5, ,6, 7) = M(O) rms.

The two functions do not have the same minterms and maxte FALSE

n

e.

((P +_Q')(P+Q))' = P EB Q Let L = ((P + Q')(P'+Q))' and R = P EB Q P'+Q l k'c::t:r·.~ ,,,i:./Il\l;:i{,;ff!,{.j/ P+Q' Q P 0 0 1 1

0 1 0 1

1 0 1 1

1 1 0 1

((P + Q')(P'+Q))' = Lm(1 , 2) = nM(O, 3) P EB Q = Lm(1, 2) = nM(O, 3) Both functions have the same minterms and maxterms.

TRUE

38 3-13

3.10

u

R.aploi::B e-vBry g~le 1,ith ,ils NOR equtvalf!11t

A

B

C

b ~llmiM~ .i;k:I.Jl:)I~

im1ersfom;.

is more efficient than Even though they use the same number of gates, the new circuit that can be (NOR) kind same the of the given circuit because it uses three gates implemented from one IC chip (TTL7428).

39 3-14

3.11

(AB+C)(A+C)

A+G

Q = (AB+ C)(A + C) + B = AB+ ABC+ AC+ C + B = AB(1 + C) + C(A + 1) = AB+ C+ B = B(A+1) + C =B+C 3.12 a. P 1 = Im(0, 3, 5) +d(1) b. P1 = nM(2, 4, 6, 7) + d(1) c. P 1 • P 2 = [Im(0, 3, 5) + d(1 )Him(0, 2) + d(3, 7)] = Im(0) +d(3) d. P 1 + P 2 = [Im(0, 3, 5) + d(1 )]+[Im(0, 2) + d(3, 7)] = Z:m(O, 2, 3, 5) +d(1, 7) 3.13

The output is always 1 regardless of the value of A.

3.14

Q{A, B, C, 0) = Im(3, 6, 9, 12, 15) A

B

C

D

0 0

0 0 0 0 1 1 1 1 0 0

0 0

0

0 0

1 1

1 1 1 1

0 0

0

1 1

0

0 0 0

0 0 0 1 1 1 1 1 1 1 1

1 1

1 0 1

0 0

0

1 1

0

0 0

1 1 0 1 0 1 1 1

Q(A, B, C, 0) = A 'B'CD + A 'BCD'+ AB'C'D + ABC'D' + ABCD

40 3-15

3.15

P(A, B, C, D) = Lm(O, 3, 5, 6, 9, 10, 12, 15) A

B

C

D

0 0 0

0 0 0

0 0 1

0 1 0

0

0

1

1

0

1

0

0

0 0 0

1 1 1

0 1 1

1 0 1

1

0

0

0

1 1 1 1 1 1 1

0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

P(A, B, C, D) = A 'B'C'D' + A 'B'CD + A 'BC'D + A 'BCD' +AB'C'D + AB'CD' + ABC'D' +ABCD P(A, B, C, D) =A 'B'(C'D' + CD) + AB(C'D ' + CD)+ A 'B(C'D + CD; + AB'(C'D + CD; P(A, B, C, D) =(A 'B' + AB){C'D ' + CD) + (A 'B + AB;(C'D + CD; P(A, B, C, D) =(A EBB)' (CEB D)' + (A EB B)(CEB D) P(A, B, C, D) = ((A EB 8) EB (C EB D))'

41 3-16

p C., , , ., , , .~ -44'

o-- - The number of 1's in the four inputs is checked with the same circuit designed in problem 1.15. If the output does not match the priority bit P from the parity bit generator, ERROR is true; if the match ERROR is false.

3.16

a = ((A EB s) EB (c EB o)),

P

0

0

: ,/c/tJt~.gBf; ~,

0 0

1 ERROR= Q'P' + QP = QEB P

c._ __

44;

ERROR

o..,,= = ~

-----·--•

p _ _ _ _ _ _ _ _ _ __ _ _..,....

3.17 Excess-3

A

B

C

D

01

02

03

04

05

06

01

--

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

d d d 1 0 1 1 0 1 0 1 1 1 d d d

d d d 1 0 0 0 1 1 1 0 1 1 d d d

d d d 1 1 1 1 1 0 0 1 1 1 d d d

d d d 0 0 1 1 1 1 1 0 1 1 d d d

d d d 1 0 1 0 0 0 1 0 1 0 d d d

d d d 1 1 0 1 1 1 1 1 1 1 d d d

d d d 1 0 1 1 0 1 1 0 1 0 d d d

--3 4 5 6 7 8 9

10 11 12

---

--

42 3-17

07

44 3-18

AB co

"'\.AS

Cl:}

01

f1

10

H

10

AEl CD

CD'\ _ OD

01

00

d

0

Olli

0,1

d

0

01

00

-01 _-1.

d

/-1

d

/~ -1

10

-·

1

0

1

~j

a,

11

1

d

1

\.d

1

1,

1-1

{)

d

0

10

ii d.,/

1

02:=.AC'+CD

A8

co

~)

01

AB. Oti CD

()t

11

rn

d

D

0

I)

---- ---- d

"AB CD

0

d

0

d

01

0

·10

0

43 3-19

3.18

Half-Ad der Truth Table:

a

b

0 0 1 1

0 1 0 1

SHA(a, b) = a'b + ab'

= a EB b CHA(a, b) = ab

Full-Add er Truth Table a

b

c

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1

0 1 0 1

SFA = a'b'c + a'bc' + ab'c' + abc

= (a'b + ab')c' +(a'b' + ab)c = (a EB b)c' + (a EB b)'c = (a EB b) EB c = SHA(a,b) EB C

= SHA(SHA(a, bl, c) CFA = a'bc + ab'c + abc' + abc

= ab + (a'b + ab')c = ab +(a EB b)c = CHA(a, b) + SHA(a,b)C -C HA(a, b)+ C HA(SHA(a,b),c) -

45 3-20

b

b

a

HA

HA

IHA

a

b

a

S . - .... . ~-· ········. .C

b

a

HA

HA C

$

S

Ca

C1

So

3.19

the 2's Since a - b = a+ (-b), subtraction can be done by adding minuend (a) to by d achieve is 8 of ment complement of the subtrahend (b). The 2's comple this how shows circuit inverting each bit and adding 1 to the LSB. The following can be implemented.

b

a

c

b

c FA

FA

FA C

a

s

s

C

C

Sa

46 3-21

3.20

Three 7483 chips are needed to add two 12-bit numbers.

12-bit .addend

>\1 Az. ,A.3 A,1 "-1 A2 A3 A~ A1 A2 AJ. "-~ 4°bit Para~ Add~ Acldllt' Para&ol -hblt 4-ttl f>arallol Adder 7483 q~ +--- Ca:A: 74B3 C:,. ,._..___. C\ct 74.83s~ s 1 s~ Ss 81 B2 e .J 84 S1 S;z Ss

s.,

t~H}it addend

12~bit sum

3.21

The circuit is composed of three parts: S1S2S S4 and the carry The first part adds the two BCD digits to produce the sum - 3

C.

BCD digit 2

9CDdilgl11

4-r,,it P~rallel Adder

0

748:3

when the sum of the The second part checks if the correction factor is needed is greater than 1001 two digits is greater than 9. This happens if either S1S2SsS4 when the sum is (the sum is between 10 and 15) or if there is an overflow (C=1 when Q is true between 16 and 18). Therefore, the correction factor is added where /S4 + S1S2SsS4 + C Q = S1S/SsS/ + S1S/SsS4 + S1S2Ss'S/ + S1S2SsS/ + S1S2S

47 3-22

Sf1

S/ i

11.C·

[]op

I}

11

I}

ii)

c,

tH

,0

Q = S1S2 + S183 + C = S1(82 + 83)+ C c _ _ _ _ _ _ __

The third part adds the correction factor to the first adder sum. So the first addend A1A2A~4 = S1S2S3S4 while the second addend is 81828384 = OQQO. If the correction factor is needed then Q is 1 and 81828384 = 0110. Otherwise 81828384 = 0000.

0 Q

~bit Paiallal Adder

7483

0

G,rni

s t S2 SA_ ,s£

BCD ,surn

Following is the complete BCD Adder circuit.

48 3-23

BCDdigit 2

'BCD digit 1

4-'bit P.at~Jlel Mdeef 7483 S1 S 2 ~ S~ Q

0 ' A1 A,._ A3 A;.

0

B1 13?. 8~ 8 4

4--blt Parallel .11..dder

BCD sum

3.22 ENJ\BLE

A

lB

G

49 3-24

3.23

Q = ABC'+ A 'BD + C'D' + AB'+ B'C

a.

AB CO DD

11

OD

C

1'1:

..I

. .J

to

o

o

o

t

'-'

b.

A

B

C

D

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

50 3-25

1 .,,,,..,.,...,..,...,,.,..,=-,-,,,.,.==,,...,.....,,...,....,..~=r....,.,....,...,,,....,....,,~~~.....,,,,.,.,..,,,,,..,,.,,..

0 --i,---,,--..,,.. ......,,-+--1--. .,.........-4---- -,.----,--......- -e----,.----.

At.J, Av. A2 A3 A4 A5 Ae A-, Aa Ag.~ o~ tAi2 A,~ 1&input M:ultiplexer E Au 741!50 A;s Q S1 S2 S3 S4

3.24

The main advantage is that multiplexers implement logic functions directly from the truth table without the need for simplification.

3.25

Q =AB'C + A'C' + BC'

A

B

C

AB'C

A'C'

BC' \i:;,Qr:·::

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 1 0 0

1 0 1 0 0 0 0 0

0 0 1 0 0 0 1 0

,·:-: ·.,

icd/' I:?, ·cc,,,;

cc

'/<' .'c_,I I

JIB ;::-;:

f:1

'.it.

"·

"I,;, \,;:'

~

Q = Z:m(O, 2, 5, 6)

3-to-BD~ 7413.B

51 3-26

3.26 A1

A2

81

82

0 0 0 0 0 0 0 0

0 0 0 0

0 0

0 1

1 1

0

1 1 1 1

0 0

0

1 1

0

1 1 1 1 1 1 1 1

0 0 0 0

0 0 1 1

0

1 1 1 1

0 0

0

1 1

0

1 1 1 0 1 1 1 1

0'2

!:!q +oiq,;4-oiio,s

~-"llw'l~~--------"11'

Rt:;;011

°'i) 0-i. o,. o~ b"' o5 o" 0 1 Oi:s Ci 11 O,c,Qr~2 .f~16lDe totlar

O,:ii

~'-~·~

MtM

('.\59,,,=.;...,.,,,,,,,,f:;::,;.,,"""""""

$1 s,, $3 $4 .

.

Al,A~ ~ ~

3.27

er Draw the truth table and Design an Octal to Binary (8-to-3) encod

d d d d d d d d

0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 0 0 1 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 1

52 3-27

An ,i!i.1

A, .-·,,-,,..,,,,,,.,,.,.,,,.,..,.,,,,.,.,i----, A3

=-•-- -,,.._

A; _ _,__ A!.

Aa - - 1 ~....., i ~...."'"""

Ar -..-.!·1!¥1'1 .--r'-----

3.28

When two inputs are simultaneously active incorrect output might occur. For example, if both A1, and A4 are active, A1 activate 03 while A4 activates 01 so the encoder will output 101 which is incorrect. One way to solve this problem is to add logic to the encoder so that when more than one input is active, the output code will correspond to the largest input. So if both A1, and A4 are active, the encoder will output 4 (100). This modified encoder is called priority encoder.

3.29 ~

A;~........,.,...--➔ s"

3.30

B •-~·

Si

C•'

~E

...,p_ _ _

:$,i

............ ,, ....___-==11

82

,2,,.t:o4 D.@ccde.r

.ail)

:01 Oz '., . . ----- Q:z

01

~

t01

~·-·--• Q4 2404 Decader

011---: ;Qr;

(\

;:Q,s

~

;Q,

A .......J,,t•••J ••··•·····t.... .J •••••• ~ •.. 1,...... ,J...•...•... , ... L...Ji... ,.,.,i ....~.

.•

B

w:1ft-"t:lflt•f••:1 lt:1rl"jj•'f••fi,,t1 "1·)"''•tti11:1-•ll •""l·•"-"l••••-fiw

Q:

........l.1.,,u r,, ..·t•••l•~·•··· ••P••l•"·!l

I

ff:1)1t•'flr>!lr,'1 "·tr.J1,, ... ,., . . . . ,., ... ,., • .,,..,,,_,,r_"'"f!'

. 1 . t , u l ~ • · • ..••li• .. l••··•., ..t••·l........a... ..

53 3-28

Chapter 4 SYNCH RONOUS SEQUENTIAL CI RCUITS

4.1

T

a

T

0 0

o

1

0

'l

1

o

i

r!

1

1

o

D=T

1

fi Exo t€tldn€

b.

JK O

o0

G1

f1

10

r-I

t

1

1

i

o

1

a o

oo

o1

11

10

o

o

1

I b=ov+GK'

1

1

1

o

o

1

D E*E tEUons

c.

SR r+{

0

o0

o1

't 1

10

o

0

d

1

a o

do

ol

-t.t

o

o

d

-f

o I

D=f,'8+(|tT 1

0

d

gt€lB TEbl€

1

1

I

o

d

I

o Ex6ltEflond

4-1

4.2

State table: 11

01

1'0

0

0 00+1r} = :S + QR'

State Table

Characteristic Table: Qt

SR

0 0 0 0 1 1 1 1

00 01 10 11 00 01 10 11

Qt

Q t+1

0 0 1 1

0 1 0 1

Excitation Table:

4.3

000

101

100

011

010

00.1

000

55 4-2

4.4

T = (XEBY1)' D =Y1 Z = X + Y2 Excitation Tables: Next State

Present State A B C D

Y1

Y2

~r

D

X=O Y1 t+1

0 0 1 1

0 1 0 1

1 1 0 0

0 0 1 1

1 1 1 1

State Table:

I I

!

Y2t+1

T

0 0 1 1

0 0 1 1

I

D

X=1 Y1 t+1

Y2t+1

0 0 1 1

0 0 0 0

0 0 1 1

X=O

X=1

C/0 C/1 B/0 B/1

A/1 A/1 8/1 8/1

m 4.5 a.

56 4-3

T= X D=Y1EBY2 Z= XY 2 Excitation Tables:

b.

Next State

Present State ·•••••·

D C

[~::

X= 0 Y1 t+1

Y1

Y2

T

D

0 0 1

0

0

1

0

0

1

1

0 0

0 1 1

C.

State Table:

0

0 1 1

0

Y2t+1

T

D

0 1 1 0

1 1 1 1

0 1

X=1 Y1 t+1

Y2t+1

0

1 1 0 0

1 0

1 1

0

-1 --- -t- ~~ --- -1 --- ~- i-~ D/1

B/0

-

4.6 0

1

0

0

1

1

1'

0

0

1

0

0

1

1

0

1

Nex t Stat e

Z = J == K = X Ei;)Q

Assuming the starting state is

0

1

0

0/0

111

1

Ol1

1/0

Stat e Tabla,

0,

Output sequence matches. Sta

rting state is O.

57 4-4

47

b.

c

d.

1l0

010

01'0 or 1/1

4.8

a.

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1 d d

d d d d d d d d 1 1

0 0 1 0 d d d d 0 1

d d d d 0 1 1 1 d d

0 1 d d 1 0 d d 0 0

d d 1 0 d d 1 1 d d

0 0 0

0 0 0 0 0 0 1

59 4-6

After minimizing: J1 = 020 s X K1 = 1 J2 = Q3X' + 01 X K2 =Os + X J3 = 01' 02' X + 02 X' K3 = X' + 02• Z =01 X

'2 -q.,,..,,,.,.,.,.~.

1e,,,--,-------1

X

J

x~~

9- ·

---1·

X-- ---' ·

9i

q_ --- l!

X Q' ······· ·1 ~"------I

x~ ~'

q_.............-X'

Qj

CL OC Kc --- --- ~

60 4-7

4.10

C = 0: B+-1 C= 1:B =A B; = A;C ' + A;C ' + A;C = C' + A;C = A; + C'

C

A;

0 0 1 1

0 1 0 1

serial

a.

B

A

Q

________ J

J

q

K

Q'

J

Q

K

Q'

J·

Q

3

3

Q'

Q 2

2

Q'

O ·

1

1:

K

a·

j

Q

~<

a·

0

=>- ---- --i

K

----l

J

:>---,--,,----

Q'

0

C

b.

parallel

crock

A

3

2

{)

K

,.I

k

.)

K

J

K

·O'

0

□'

0

•D'

0

o·

J

K

K

J

I<

C

61 4-8

4.10

C=0:

1

C=1:B=A Bi= ArC'+ AiC'+ AiC

=C'+AiC=Ai +C'

a. paraflef

4-8

4.13

hed to the C a clock comes along, 0 is latc and O at are s nal sig trol con d with the If both C register, C's output is ANDe the of g arin cle the t ven pre be built register. To input. For this to work, C must C's the to k bac fed and R' NANO' and XO out of master-slave flip flops.

C D

Q

O'

D

Q Q!

NANO

XOR

63 4-10

Data Selectors): Using TTL 74153 (Dual 4 to 1 Line

4.14

· ·~:\i~p} ~:~~-~;:;:

So 0 0 1 1

...~,~;-' /.-. ,-...·.\?:

C " - - - - - - 1,

1u2

Y1

; TA:i

TTL 741 53 1

. ; lbu .. - - - - - ' t ' - - 1! IM

Y2

-...... .....r1 1-• Jb 2 ltj]

NAND

XOR

Clock

4.15

ter-Slave flip-flops Register B must be built out of Mas

11 ..

A D

, ..........,"""""'"""~"1 ...... ..1 Qr"

_,,,.___ ,,,.__

--- --- 0

__.Ji,,

l,i l.~l

Y1

Q

Q' Q

' " ' 1 - - ~...... ~;

.....

, -- - - ~ } ,

~

:\i::i

31'.l'

s,

~

G Clock

64 4-11

4.16

C

~

~1,.,..t

,0£,c,:oO:lr

BUSO 8LlS1

c ccc l, ;? 1 ll

D

D

A Q'

B

Q

Q'

Q

Q'

°' [)_

65 4-12

4.17

BUS1 1

GVC VC~ t

j

o· o ,a· Q o· o:o· O 'O' o A

D

D

D

D

D

Q' Q' Q:" Q Q' Q Q' Q Q' Q

B D;

C

D

0

D

0

o; o:o· o o· o o· o tr o D:

0

D

D

D

vc7 cvc 2 r,

Ul!J •

:>----~

C

'.1

Q' Q ,Q' Q Q' 0 Q' Q ,Q' Q

D

D

O

D

D

~1"?----.

TR.~Nf,F~R ~::=~f""1;"'---~=-....,....,,1.,,,,,,,,,,, 3,,iJH Counlei;

s.2 sl s0

AN!}

OR ADD

th , 2 , 3) are shown Only the detail of the i bit (i = 1 wide bit Each of the three busses, is 5 TRANSFER = Co V C5 AN D= C4 V C1 OR =C1 V C5 AD D= C2 V C3

4.18

s of input to th s of input to BUS1 i and 4 source For the i bit, there are 3 source each bit, and a ut and one 4 input OR gates for BUS2j. Thus, we need one 3 inp bus structure. total of 1O gates for the complete

66 4-13

4.19

('J

R

CL OC K C"" >-- --_ __. .,___

Q

Q 1

0

a·

a·

~

_,,P----==--"r~

R

0 ~

a·

R

:'s

a·

~~--i,,...___~~

RE SE T , ~ ... . . .. . . . . . ..

4.20 0 Q

CLOCK c·" >---- --1"' .:lio RE SE T

c:r--~

u

Q

4

Q a

Q

Q 2

1

Q o

TTL 741 74

O O3 t.JZ Dl 0 0 P! ' i 4-

4.21 I I

~-- =-·r.r--J~ t~ .9i~.. ~ ~ ~ ~ ~o.~q~ '~ ~ .,~ ,~ ~l1= I 1-.~?M~~o~q q 9.. o; 9,, 9 ~ ¢1,

,....._>

TTL 7417 4

TTL N17 4

06

~

Ir{

Di

D1

Di}

--- •1 r1i .___

67 4-14

4.22

registers when loading the input to the Both SO and S1 are set to 1 SL: Shift Left Input SR: Shift Right Input

0 .B .., _- --- •:: -,

- ..........--iA ---a

....,,..,,,,,f

C

- - - ~ - - - 1.

0

t------•·194 OD .,,,,,,,..,.,.,..,.,,,,=,.....,..,...=•QC

-------10

-;;-. ~ ~-=-

t-- --- --- ::: -

QA

-SR

TTL 74

.~1 ---- ---1 .~:- -::i. •CL Cl.K ,c

so

0

Si:

1!

OC K

4.23 QA ~= -m -=. ...- •

'== =-= 1,. SR

---►•,--

.• QB t - - - - - - " ' r .,p --;;; ....,,;...,_ ......... ~ m~ -=QC 1---

,A

_ _.,..,.,.........,..+B - -- ~---- r

t::

·· + - - -•:; TTL 741 94 Qp 1 - - - - -

OC K CLK<::_<~.,_.._ _----r_7-, CL

- -- ; . --1, D

·· == sot == =+

1

S1

0

4.24 LS,B

MSB

B

A '

-> I a

b

I

c,

FA

->

Q'

I D C

> LSB

MSB

68 4-15

4.25

MSB

LSB

CLO CK c,.. -,

69 4-16

Chapter 5 ING A SIMPLE COMPUTER: ORGANIZATION AND PROGRAMM 5.1.

Memory System Capacity

Number of bits in MAR

Number of bits in MBR

64KX 8

16

8

64K X 32

16

32

32K X 16

15

16

32K X 32

15

32

128K X 64

17

64

Memory System Capacity

Number of bits in MAR

Number of bits in MBR

64KX 8

16

8

64K X 32

18

32

32K X 16

16

16

32K X 32

17

32

128K X 64

20

64

5.2.

5.3.

Number of words = 16K Number of bits in MAR = log216K = 14 1. 48 -+ 00000000110000 2. 341 -+ 00000101010101

3. 0 8191

-+ 00000000000000 -+01111111111111

0-8191-+ 0ddddddddd

(d = don't care)

70

5-1

4. 8192

-+ 10000000000000

16383

-+ 11111111111111

8192-16383-+ 1ddddddddddddd

5. 2

-+ 0000000000001 0

4

-+ 000000000001 00

6

-+ 0000000000011 0

8

-+ 00000000001 000

16380-+ 11111111111100 16382-+ 11111111111110 -+ ddddddddddddd0

6. 48 -+ 0000000011 0000 49-+ 00000000110001 50 -+ 0000000011 001 0 51 -+ 00000000110011 52 -+ 0000000011 01 00 53 -+ 00000000110101 54-+ 00000000110110 55-+ 00000000110111 -+ 00000000dddddd

5.4

Instr uctio n

Effe ctive Addr ess #HlO #HlO + 5 = #Hl5 z cont ains 25, i.e. effe ctiv e addr ess= 25 = #Hl9

STA STA STA*

,3

STA*

,3 (Pre- Inde x)

10 + 5 = #Hl5 Memo ry loca tion 15H cont ains 77 = #H4D i.e. effe ctiv e addr ess= #H4D

STA*

,3 (Pos t-Ind ex)

Zcon tains 25(i .e. #Hl9) i.e. effe ctiv e addr ess= #H19 + 5 = #HlE 71

5-2

5.5

15

c2 5 > 1 0 = lo

-

- - - o o o o

5.6

0

o o 1l

1 1

50 30 ( 1111 1111 1110 0111 ) 2

=5

28

=#H3

12

The cont ents of the Ace

Inst ruct ion SHL ADD TCA ADD SHR

-

-

The cont ents of the ACC

Inst ruct ion SHL ADD TCA ADD SHR

-

8 7

50 55 (111 1111 1110 0100 1) 2 (111 1111 1110 0110 0) 2 (111 1111 1111 0011 0) 2

=5 =#H3

5.8.

Memory Address 00GB 0OC9

Content

OOCA

z M

0OCB

0003

oocc

FFFD 0005

OOCD 0OCE

OOCF

.____O_OE•.6_~ '

L..-1- - - - ~

72 5-3

5.9.

Conten1.

O.:X:El

Cve9

OOCA

0003

z

FFFD

DOCC

M

tlDCD

0,12c

0120

144 ~□ 5.10.

_I i. . .- 1~~I

(a) (1)

LOA X X

BSC

5

OR (2)

LOI

=5

LOI =5 instruction executes faster. with constant operands The immediate addressing mode makes operations of the instruction, where as faster because data is available in the operand field in (1) a memory fetch is required in order to get data.

73

5-4

(b) 2 15-1).

The range of the data value that can be loaded by first method is(± 7 d is(± 2 -1 ).

The range of the data value that can be loaded by second metho alignment, to occupy a 5.11. NOPs are used for timing purposes, to force memory instructions later branch delay slot, or as a "place-holder" to be replaced by active space of the the up takes ion, on in program development. NOP, or no operat state other sor proces the in smallest possible instruction and causes no change es. chang than an advancement of the program counter and any time related

5.12. (a) (b)

(c)

5.13

it assembles When an assembler encounters BRU + 5 or BRU -5 instruction, LC+S or LC-5 respectively in the operand field.

7 The range of relative jump addresses possible in ASC is(± 2 -1). address The advantages of PC-relative addressing mode are faster target can be loaded calculation and position independent code (i.e., this instruction without any tly correc ted anywhere else in the memory and can be execu to only(± change to code). The disadvantage of this mode is that it can jump 27-1) addresses from the current address (only short jump).

Symb ol BEGIN TEMPl LOOP TEMP2 OUT SUM A

B C

Addr ess ilfil 200 205 207 20B 20D 20F 210 211 212

74

5-5

5.14

Program

Location Jjfil_

ORG 64 RWD A STA TEMPl BIP TEMPl BIN OUT BRU B,1 LDX =0,2 LDX C, 2 LDA SUM ADD SUM STA TEMP2,2 TIX OUT,1 TDX LOOP BRU HLT

BEGIN

64 65 66 67 68 69 6A 6B 6C 6D 6E

TEMPl

6F

TEMP2

70 71

OUT

LOOP

ORG BSC BSS BSC BSS END

SUM A

B C

5.15

See problem

128 0 1 4 4

BEGIN

4.13

75 5-6

CJ1

_..,

O')

*

0001

0002

* *

000:3

0004

-.._J

(J)

1006

BE13IN

0005

0000

0006 0007 0008

0001

4000

0002 000:3

0009

0004

3007 2008 9000

OOOA OOOB

0005 0006

0000

oooc

A

0007

0010 0000

B

oooc OOOD OOOE

'( A)

OOOE:

SOURCE PPOGRAM A SUBTRACTION ROUTINE OF~l3

0

LDA TCA ADD STA

A 8 C

l,.Jl.iJD

HLT C

B~;C 8S1:: E·•C·C· ·-''-' Et··.~D

12 16

1

BEGit··.J

.GET MINUEND IN TO ACC ~GET TWO'S COMPL OF THE MINUEND .SUBTRACT . STORE THE DIFFERENCE INC . PRINT THE DIFFERENCE . RESERVE LOCATION FOR A

5-7

\.~

➔.

0001

0002 000:3 0004 0005

*

C10E

0007

0000 0001 0002 0003

000:3

0004

5008

0009

0005

210'?

0008

000,:::,

E10F

OOOD

0007 0008

5001 0000

OOOE

000'7'

0000

OOOF

OOOA

0010 0011 0012 0013

0008

0000 0000 0000 0000

0006

OOOA

oooc

---..J ---..J

0014

0015

( 8)

oooc OOOD OOOE OOOF

8000 7005 6005

0000

0000

BEGIN LOOP

SA',)E

*

.,OUT ,._

SOURCE F'ROGRAtv1 DRG LD:x:

0

ZERO~ 1

Rl,JD

BIN BIP BRU '.3TA TI>< BRU HLT

SA 1v'E f;AVE OUT

.INTEGER O ENCOUNTERED .STORE THE NUMBER IN A LOCATION Z, 1 .POINTED BY Z + I t·-..IDE>< REG. 1 DUMMY., 1 .INCREMENTING INDEX REG. BY 1 LOOP

B ,::-,:·

·-•.._,J

i= ,_,

ZERO

BSC

0

DUMM-...✓•

8S:::;

END

.CLEAR INDEX REGISTER 1 TD ZERO . READ At-~ I t·-.ff EGER

1

BEGIN

.RESERVE SPACE FOR STORING INTEGERS

5-8

*

000 2 000 3 000 4

000 5

000 0 0001

000 6

000 2

000 7 000 :3 0 0 0 "1'

000 3 000 4 000 5

OOOA

---..J

CX>

000 8

0 (11) t,

oooc

000 7

000 D

OOOE

000 8 000 9

OOOF

OOOA

001 0

000 8

0 0 11

001 2 001 3 001 4 001 5

( C)

*

000 1

oooc

000D OOOE OOOF

ClOE :300 0 700 1 600 5 500 8 210 9

E10F 500 1 000 0 000 0 000 0 000 0 000 0 000 0

000 0 000 0

BEGlt'~ LOOP

SAl..)E

* OUT

SOURCE PROGRAM ORG LDX Rl..~JD

BIN

0

ZERO" 1

.CLEAR INDEX REG. 1 TO ZERO ~:EAD At·-~ INTEGER I

LOOP

BI F'

SAl.)E

BRU STA

OUT POS, 1

.INTEGER O ENCOUNTERED .STORE THE NUMBER IN A LOCATION .POINTED BY POS + It-.JDE)< REG 1 1 DUMMY, 1 . INCREMENTING INDEX REG. BY LOOP I

TIX BRU

HLT

PDS

BSS

5

ZERO DUMMY

BSC

0

E:SS

Et,~D

1

E:EGIH

.RESERVE SPACE FOR POS. INTEGERS

5-9

0002 0003

0

ZERO" 1 ZER0 ,2

0000

C:117

BEGIN

0005 000 .~.

0007 0008

0001 0002 0003 0004 0005 0006

C:217 8000 7006

LOOP

Rl,,JD BH~

500C 2112

oooc 000D

OOOE OOOF

0007 0008

0009

E118 5002 220D

0010

0018

001C 001D 001E

001F 0020 0021

SA v Et··-~ 1 1

BRU STA

*

:::;Al)EN SAlJEP OUT t-..JEG ~ 1

t;A 1)EF·

TI>< BRU

DUMM \', 1

STA

P0:3,2

*

0011

0012 001 :3 0014 0015 001-6 0017 0018 001 '7' 001A

BIP

*

0008

c.o

IJRG

0004

600'7'

P~'.CIGRAt·,1

::;OUF~CE

LD>< LD><

ooo·,:, o o·oA

-...J

, ( D)

* *

0001

0008

E218 5002

OOOD

0000 0000

OOOA

oooc OOOE OOOF 0010 0 0 11 0012 0013 0014

0000 0000 0000 0000 0000

0017

001 c:

(IO (I (I

001 c_,

OUT

TI>< BRU HLT

POS

_,._, E..,c-c·

NEG

,,-.,-.

E,."::).::)

Z EF.'.0 DUMM\.

E:sc ~.-..

E..

Et"-ID '•=l~I

.INTEGER O ENCOUNTERED .STORE THE NEG. NUMBER IN A .LOCATION POINTED BY .NEG + INDEX REG. 1 .INCREMENTING INDEX REG. 1 ff'( 1

.STORE THE POS. NUMBER IN A

.LOCATION POINTED BY r:, . POS + INDEX REG . "DUMM'/, 2 .INCREMENTING INDEX REG. 2 LOOP

ff'(

1

C'

.RESERVE SPACE FOR POS. INTEGERt;

C'

.RESERVE SPACE FOR NEG. I t,ff EGER\3

-J

.J

0000

0000 0000 0000 0000

0015

*

LOOP

.CLEAR INDEX REGISTER 1 TO ZERO .CLEAR INDEX REGISTER 2 TO ZERO . READ AN I t··ffEGER

I)

1 8E(3 IN

5-10

0001 0002 000:3 0004 0005

( E)

* *

OOOt,

'.:::OURCE PROGRAM FOLLOWING ROUTINE PICKS OUT THE MAXIMUM AND MINIMUM VALUES FROM A COLLECTION OF INTEGERS STORED AT LOCATIONS STARTING AT TABLE. OFW

0

#H50

TABLE TABLE COUNT

OOOB

0000 0001

1050

0009

0002

145A

OOOA

0003

2059

LDA STA LDA* :::;TA

0004

C159

LD:>(

COLNT , 1

0005

LDA STA

TABLE , 1

000,6

115A 2057

0007

F109

0008

501F

TD>< BRU

COMPARE,!

MINN

0007

E:EGIN

205A

000B

oooc 000D

OOOE OOOF

MA><

0010

co

0

0011 0012 0013 0014

LOOP

*

0015

5-11

0022 0023 0024

.STORE THE NUMBER OF ENTRIES . IN LOCATION COUNT .INITI ALIZE INDEX REG.1 TO THE .NUMBER OF ENTRIES .GET THE LAST ENTRY IN THE TABLE .ASSUME FOR THE TIME BEING THAT .IT IS MAX OF THE INTEGERS .DECREMENT INDEX REG. 1 BY 1 .COMPARISON FOR MAX IS .COMPLETED

PICK OUT MAX NUMBER

001.~.

0017 0018 0019 001A 0018 001C 001D 001E 001F 0020 0021

THE ADDRESS OF THE TABLE .STORE THE ADDRESS OF THE TABLE

.GET

0009

1057

000A

?00F

0008 OOOC

6013 115A

000D

7007

OOOE OOOF 0010 0011

601D 115A 601D 7017

0012

501D

COMPARE

LDA

MAX

BH,J

NEG POS

BIP LDA

* NEG

BI t·,~ E:IP LDA BIP E: I t··.J

* *

E:RU

TABLE~ 1 LOOF' STMA:::< TABLE ~ 1

STMA>< NEGPOS

< 0

. IF MA><

. IF MAX ;:, 0 .IF MAX= 0 , THEN FETCH NEXT . ENTRY. . NEkl 1.)ALUE < MA>< GO TO STO~:E MA>< ROUT I ~~E .FETCH NEXT ENTRY If

I

II

. NEl,1.J 1,)ALUE < 0, GO TD II COMPARE . NEGAT I l.)E AND P0:3 IT I 1,)E F.:OUT I NE .VALUE IS ZERO AND GO TO STORE MAX ROUTH,lE" • II

11

0025 002t , 0027 0028 002'?

002A

115A

0013 0014 0015

7007

0016 0017

5007 4000

001:3

:3057

001 '?

001A 0018 001C 001D 001E

6007

CX> ~

uu:.::

00:3A

BRIJ TCA

LOOP

~--JEGF'OS

*

ADD

MA><

*

BIP

LOOP GET LOCJP TABL E~ 1 MAX LOOP

*

E:IN E:RU

701C

5007 115A

2057

GET ::ffMA><

5007

LDA BIN BIP LDA

NEG l P0~31 TABL E, 1

*

BIN

STMit··.J

*

BI F'

NEG 1

E:RU LDA

LCIOPl LOOF 'l TABL E ff 1 r·-JEGPDS1

* MINN

LD>(

0020 0021

2058

115A

*

LDA STA

.,_

0047 5-12

0048 004'7 ' 004A -

0025 0026 0027

7028

002::::,

703'7 '

0 0 2'?

002A 0028 002C

.~.022 5022 115A 7033

**********

e~b

C:159

105::::

. ~;At)E THE NE~J MA><

. INIT IAL! ZE I NDE>< REG. 1 : l~T T¥~E t,J~~ ~fRE f~tRf NT~ I t~E TABL E TAB LE,! .AS~;UME IT IS MIN FOR THE MIN .TIM E BEIN G 1 1 , 1 'ARE 58~F YgE~ o~~e ~T~D BY

001F

0024

.FET CH t··.JE~-<T Et-ff RY .HEl,.J ',)ALLIE (. MA)< .t---JEl,,.J l..JALUE ) 0 ' GO TO "COM PARE 1 .NEG ATit) E AND POS ITI ,)E ROUT I t··.JE II .t--JEl;J 1-..JALUE = 0 . OBT AIN Tl,,I0 / S COt1PL . FOF.: . SUBTF.:ACT I m-.J . SUBTF~ACT FROM MA><, TO SEE IF .NEk l l..JALUE IS BIGG ER OR HOT .NEt~.I l)ALU E < MA>< .NEk l '-....'ALLIE ) MA>< .NEl,.J t)ALI JE = MA)<

F' IC~< OUT MIN t--J Ut·,18 ER

***********

0038 * 1 --8~~,._, §b~g LOOP BB]6 H 003E 003F 0040 0041 0042 004~ : 0044 0045 004,5

LDA STA BRU

*

00:36

00:37 00:3~-,

TAB LE, 1 LOOP NEGPOS

6017

0028 002[ : 002[ ) 002E 002F 0030 0031 0032 0033 0034 00~.::5

LDA BIN SIP

PO:::;

*COMF'Af;:E1

,S02F 115A

BIN

*

COU NT, 1

:e~~~~~~~EN

MIN

. IF MIN . IF MIN . I F MIN

<0 .}

(I

= 0

THEN FETC H NE><T ' .ENT RY .NEl•.J l,,.JALUE < 0 ~ GO TO Mit··.J ROU TINE " • II ~;T[IF:E .NEk l l)ALU E > 0 .NEk l 1-)ALU E = 0 .FET CH t~~E><T ENT~:y· .NEl}.J 1-...-'ALUE ·=~ 0 • GO TO II COMPARE ~NEGAT I l)E AND POS I.TIV E ROU TINE "

004 8

002 D

602 2

004 C 004 D

002 E 002 F

502 2

004 E

003 0

703 9

115 A

004 F

005 0 005 1 005 2

005 3 005 4

00

(\)

003 1 00:3 2

603 3 50 3'7'

POSl

*

*

* NEGPOS1 * *

400 0

005 5 005 t, 005 7

00:3 4

:305 8

005 8 005 9

003 5 003 6

005 A

003 7

603 8 702 2 502 2

005 8

00:3 8

115 A

005 C 005 D

0Ci:3 9

205 8

GET! STMit··.J

0 0 :::A 00:3 8

502 2 000 0

OUT

005 0 005 1 005 2

005 1 000 5 001 2

006 0 006 1

006 2 006 3 00-5 4

005 :3

(11),:::,5

005 5 005 6 005 7

006 6 006 7

005 4

000 6

0 (1,:::,9

00,:~.A

005A

000 0

oo.~.B

~,~EGP0:31

B~:U

STMIN

l)ALUE > 0 . NEL'-1 VALUE = 0

. l'.!EliJ

.NEW VALUE< MIN, GO TO STORE MIN FWUTINE . NEl..J ~)ALUE > 0 , GO TO "COMPARE . NEGAT l l.)E AND POSIT I l)E ROUT H·-JE . NEl. .1 lJALUE ( = 0) < MI t··., ~ GO TO ST [IRE MH~ R[I UT IN E .OBTAIN Two ~s COMPL. FOR .SUBTRACTION .SUBTRACT FROM MIN, TO SEE IF .NEW VALUE IS SMALL OR NOT . NEl\J ~)ALUE < MIN . NEl.-..1 l...JALUE > MI I'-~ .t··JEl-'-' l.,JALUE = MIN 11

•

TCA ADD

MIN

BIP BIN BRU LDA

GET1 LOOP! LOOP! TABLE~ 1 MI r,.J LOOP!

:::TA

BRU HLT ORG BSC BSC BSC

000 0

005 8 005 '?

006 8

BIP

BSC

FFFD FFFE 000 0 000 0 000 0

LOOPl LOOPl TABLE~ 1 STMIN

•

003 :3

005 E 005 F

BIP BRU LDA BIN

MA>< Mlt,.i

COUNT TABLE

II

II

II

.SAVE THE NEW MIN

#H50 #H51 5 18

.TABLE STARTS HERE

-·-=·......

BSC

-2

E:SC

0

BSC

.s

C-C:

B-.J....J

,-.,-.

8 -=· ~

BE;::;;

·B:3S END

1

1 1 E:E(3 I r--.J

.THE ADDRESS OF THE TABLE

II

5-13

000 1

*

000 2

*

EN SET OF NUMBERS THIS PROGRAM ARRANGES THEOF GIV THEIR MAGNITUDE. IN THE INCREASING ORDER .

WE USE BUBBLE SORTING TECHNIQUE (I

BEGIN

DRG LD>< LD><

FLA13, 3

000 3 000 4 000 5

* * *

000 6

000 7 000 8 000 9

000 0

C12A

000 1

C32 4

OOOA 000 8

oooc

F32 1

00Cf4

500 0

000 5 000 6 000 7 000 8 000 9

112 5 601 4

OOOA

700 C

000 8

500 2

OOOC

1:::-::2:3

001 8

OOOD

001 C

OOOE

112 4 202 2

001 D

OOOF 001 0 001 1 001 2 001 :3

OOOE OOOF co

w

F10 5

000 2 000 3

000 D 001 0

001 1 001 2 001 3 001 4

001 5 001 6 001 7

001 8 001 9

001A

001 E

OO lF 002 0 5-14

002 1

002 2

,( F)

* * * *LOOP

COUNT, 1

.STORE THE NO. OF ENTRIES IN .TH E TABLE IN INDEX REG. 1 G .INDEX REG. 3 IS USED FOR FLA .SIGNAL INDICATING WHETHER Sl.,.JAF' OCCURRED •

II

II

TD>( TD;<

DUMMY, 1

*

BRIJ

BEGIN

. DECREMENTING INDEX REG. 1 .SORTING IS COMPLETE IF INDEX .REG. 3 IS NOT ZERO .THROUGH ONE PASS

*DUt···lt·'fY

LDA

TABLE,1

.LOAD THE ENTRY INTO ACC . REG .

701 D 112 4

BIP

POS

BIN

BRU

NEG TABLE-1,1 .ENTRY K = 0 .ENTRY K-1 > ENTRY K LOOP .ENTRY K-1 < ENTRY K SWAP .ENTRY K-1 = ENTRY K <= 0) LOOP

LD><

~NE ,3

LDA STA LDA

TAB LE- 1 , 1

LDA BIP

600 2

8 I~,~

*Sl,.JAP

112 5 212 4

:::TA

102 2 212 5 500 2

LDA

'.::TA

BRU

*

IJUT~3

TEMP TAB LEw l

TABLE-1,1 TEMP TABLE, 1 LOOF'

.MARKING THE FLAG

.SWAP ROUTINE

O:>

~

PIJS

002 3

001 4

112 4

002 4 002 5

001 5 001 6

700 C

002.~ .

002 7

001 7

002 8 002 9

001 8 001 9

002A

001A

312 5 600C

002 B

001 B

700 2

002 C 002D

00lC

500 2

002 E 002 F 003 0 00:31

001D 00lE

112 4 600 2

001 F

701 8

002 0

500 2

003 2 003 3 003 4

002 1

000 0

002 2

000 0

003 5

002 3

00:3 6

002 4

000 1 000 0

* TEMP ONE FLAG

000 5

* LE TAB

601 8 500 C 400 0

00:3 7

003 8 0 0 :3S:' 00:3 A

003 8 00:3 C 00:3D

00J E 003 F

002 5 002 6 002 7 002 8

000 4 000 0

002' 7'

000 3

002 A

000 5

*CCIMPAF.'.E

* NEG

LDA BIN BIP BRU

:3IJ.JAP

. ENTRY f<-1 < ENTPY r(

COMPARE Sl.i.JAP

. ENTR\.. r(-1

0)

< ENTRY. I<

. COMPA~:E ROUT I NE T~BLE~l SIAIAP LOCIP LOOP

LDA BIP BIN

TAE:LE-1, 1 . Et--ff R\.. f< - 1 > ENTRY I< LOOP COMPARE . Et-,JT RY ~( -1 ( = 0 ) > ENTR/ K LOOP

. ENTRY r<-1 < Et-.ffRY r< . ENTRY K-1 > ENTRY k'. .ENTRY K-1 = ENTRY K

HLT ,c·c· E•--•w

BSC

1 1

B::::c

(I

8:3C BSC

5

E:~:K

.TH IS FLAG IS USED TO CHECK IF . ANY SWAPPING OCCURRED IN A PASS .FIV E ENTRIES IN THIS TABLE

4 0 .'"j L..

COUNT

Bt:C BSC BSC

*

END

BEGIN

000 2

(=

TCA ADD BIP BIN B~'.U

BFW

OUT

TABLE-1 ~ 1

•:, ...... c:-

,_I

.POINTING TO THE LAST ENTRY . IN THE TABLE

5-15

0001

0002 0003 0004

0005 0006 0007 0008 0009

(Jl

0000

0001

0002 0003

lOOF 6004 7004 500D

BE13 IN

SOURCE PROGRAM IJRG

0

LDA BIP

A

E:IN

BRU

MULT MULT OUT

.MULTIPLIER IS ZERO

LDX

B, 1

ZERO

SUM

LDA ADD TD>< STA l.1Jl,.JD

1010 ,~OOB

BIN

7008

0007

SOOD

OOOD OOOE OOOF

0008

C11 0

000'7'

1012

0010

OOOA

:300F

0 0 11 0012 0013 0014 0015 0016 0017 0018 001'7'

000B

FlOA

MTPLI E~'.

* MULT *

oooc

2011

000D

'?000 0000

OUT

0014 0005 0000

A B C

0000

ZE~:O

OOOE OOOF 0010

0011 0012

MTPLI ER MTPLIER OUT

.MULTIPLICAND IS ZERO .READ THE MULTIPLIER

0005 0006

.READ THE MULTIPLICAND

8

0004

0008

001A

( G)

BRU LDA BIP

OOOA

oooc

00

* *

A

~:UM, 1 C

.8 TIMES UNTIL INDEX REG. 1 = 0 .STORE THE RESULT INC l....JP I TE RE~:IJL T I

HLT

*

.ENTER MULTIPLIER IN INDEX .REG. 1 FOR COUNTING . CLEAR ACC. REG .

SSC

20

BSC BSS BSC Et,~D

5

1 0

BEGH·~

5-16

0001

*

0002 0003 0004

0000

ClOE

0005 0006

0001

C20D-

0007 0008

0002

120F

0009

0003

6007

OOOA

0004

0008

0005 0006 0007

7006 5007

oooc 000D

OOOF 0010 ro

0)

0011

0009

OOOA 0008

0012

oooc

0013 0014

000D

0015

0016

0017 0018 0019 001A 0018

(H)

*

OOOE OOOF 0010 0011 0012

4000

2215

*

LOOP

COMP SAVE

ORG LDX

0

LDX

CLR, 2

LDA BIP BIN BRU TCA STA TIX

A,2 SAVE COMP SAVE

TDX

COUNT~l

B,2 DUMMY~2

LOOP,1

HLT

0000

DUMMY CLR COUNT

BSS

1

BSC

0

BSC

6

A

SSC BSC

':l·J

0000

BSC

0

FFFE

BSC BSC

20

0000

000 0 0006

0020 FFFD 0014

0014

FFFB 0000

001C 001D

0016

001E 001F 0020 0021

0018 0019

0000 0000 0000 0000

001A

0000

0017

*

E20C F102

0013 0015

BEGIN

SOURCE PROGRAM

B

~~

-3 -~ ~

BSC BSS

-5

END

BEGIN

ul

.INIT IALI ZE INDEX REG. 1 TO THE .NUMBER OF ENTRIES .CLEAR INDEX REG. 2 WHICH WILL .BE USED AS INDEX IN THE TABLE .GET AN ELEMENT .THE VALUE OF THE ELEMENT IS 0 .STORE THE NUMBER IN A LOCATION .INCREMENTING INDEX REG. 1 BY 1

5-17

0001

* * *

0002 0003 0004

*

0005 0006 0007 0008 0 0 0 '7' 000A 0008

00

....._j

*

ClOD

000D -OOOE

0006

500C

OOOF 0010

0007 0008 0009

:300E

0011 0013 0014 0015 0016 0017

000B

oooc

8000 6007

ZERO, 1 ZERO SUM

LOOP

F~l._lD

7007

CUt·-1MUL

200E

ElOF 5003 0000

SIP BIN BRU ADD STA TIX E:RU

OUT

HLT

* * * * *

001A

OOlE

0

LD:X: LDA STA

200E

0019

001D

ORG

BEGH-~

100D

0018

0018 001C

SOURCE PROGRAM WE ARE ASSUMING THE SUM OF INPUT INTEGERS IS SMALL ENOUGH AND CAN BE REPRESENTED IN ACC. REG.

* 0000 0001 0002 0003 0004 0005

oooc

(I)

000D

OOOE OOOF

0000 0000 0000

CUMMUL CUMMUL OUT

. CLEAR :3UM .READ AN INTEGER .0

I :3 READ It·,~.

SUM SUM

.STORE THE PARTIAL SUM DUMMY, 1 .COUNTING THE NUMBER OF INPUT LOOP .AT THIS POINT THE DIVIDEND IS .IN LOCATION SUM, AND DIVISIOR . I N I ND EX REG . 1 . l•J E CAN NQl.,.J .USE THE DIVISION ALGORITHM .SHOWN IN FIGURE 4.6 ca □□ K) TO .IMPLEMENT THE AVERAGING.

* ZE~:O

BSC

SUM

BSt;

1

DUMt·-rt

BS:3

1 BEGIN

END

.CLEAR INDEX REG. 1 TO ZERO.

(I

The problem. in averaging comes from the lack of floating point number representation. If we want to know the average

to the nearest tenth, we may multiply(by shifting) times ten

5-18

before we divide the sum by the number of input entries.

5.17

Forwar d referen cing is not possib le . That is, a label must have been declar ed before it can be referen ced in the operan d field.

5.18

(1) A new psuedo instru ction to store double words is needed .

(2) All the sixteen bits of the second word (least signif icant word) are treated as magnit ude bits .

(3) A CARRY flag(C) is needed to save the CARRY genera ted during ADD .

(4) A new instruc tion add with Carry (ADC) is needed , i.e .

ADC

MEM

implie s

ACC --- -

M [MEM ] +

ACC + C.

Then, to add two double words located at X and Y and to store the result at z: LOA ADD STA LOA ADC STA

X y

+ 1 + 1

Z+ 1 X

y

z Addres s

Opcode

5.19

Field

N

SHR

Assemb ler must transl ate the above instru ction into N SHR instruc tions .

SHR SHR •

N - instru ctions

SHR

88 5-19

5.20.

BEGIN LOOP

A B C SUB1

5.21.

BEGIN LOOP

A B C MACRO

5.22.

ORG 0 LOX =9,1 RWD STA A RWD STA B JSR SUB1 LOA C WWD TDX LOOP, 1 HLT BSS 1 BSS 1 BSS 1 END BEGIN LOA B TCA ADD A STA C RET END BEGIN ORG 0 LOX =9,1 RWD STA A RWD STA B MAC1 (A, B, C) LOA C WWD TDX LOOP, 1 HLT BSS 1 BSS 1 BSS 1 END BEGIN MAC1 (A, B, C) LOA B TCA ADD A STA C ENDM

If we compare above solutions of problems 5.20, 5.21 in terms of memory and speed, the solution using macro executes faster because jump, return overhead is not there. Both solutions take same amount of memory because macro is called only once in loop.

89

5-20

5.23. a.

ORG 0 BEGIN LDA A STA C LDA B STA A LDA C STA B HLT A BSC 5 B BSC 8 C BSC 0 END BEGIN ...............................................................................

ORG 0 BEGIN LDA A ADD B STA A LDA B TCA ADD A STA B TCA ADD A STA A HLT A BSC 5 B BSC 8 END BEGIN b. We can see here that that first program takes 6 steps to do the swap, while the second takes 10 steps. But the first uses the extra memory. We can make a rough assumption that each of the steps take similar time, to get the estimate in terms of execution time.

This shows that while using extra memory we are able to save some steps/execution time.

5-21

5.24.

PI = 22/7 Let us assume two new instructions: MPY A Acc*A ->Acc PRODUCT GOES TO ACCUMULATOR DIV A Quotient -> Index1, Reminder -> ACC ORG 0 NUM BSC 22 DEN BSC 7 RESULT BSS 5 PLACE FOR 5 DIGITS IN 3.1417 EXCLUDING DECIMAL POINT BEGINLDX =1, 2 POINTER TO RESULT DIGITS LDX =4, 3 LOOP COUNTER LDA NUM DIV DEN STX RESULT,1 STORE THE FIRST DIDGIT OF RESULT LOOP MPY =10 DIV DEN STX TEMP, 1 NEXT DIGIT OF RESULT IS STORED AT TEMP STA TEMP2 SAVE AACCUMULATOR LDA TEMP MOVE TEMP TO RESULT INDEXED STA RESULT,2 LDA TEMP2 RESAVE THE ACCUMULATOR TIX NEXT,2 INCREMENT POINTER NEXT TDX LOOP,3 HLT END BEGIN

5-22

Chapter 6 A SIMPLE COMPUTER: HARDWARE DESIGN

6.1

Microop erations during CP 1 , CP 2 and CP 3 remain the same.

During CP~, the branch conditio n is tested and the address computa tion is inhibite d, if the conditio n is not satisfie d. As an example , the followin g changes are needed for BIN: Fetch

IF ACC 1 5 = 0 then <,.;_ __ IF IR1.s = 0 then MAR IR1-o + INDEX. IF IR1 o = 1 then STATE <-- D else STATE <-- E.

CP 4

PC <--- MAR, STATE <--- F.

Execute CP 4

For BIP, the changes are same as above except for the first conditio n in Fetch - CP 4 •

6.2

SHR . __.__ _ _ _ _ _ _--,-_ _ _ Shift Count (4 bits) --JI

a. A counter is needed. We can configu re the least signific ant four bits of IR, as a down counter or use a separate count microop eration sequence for SHR is E.

Fetch

CP 4

STATE

Execute

CP 1 CP2 CP3 CP4

ACC <--- SHR(ACC ).

SC <--- SC - 1.

<----

IF SC=0 then STATE <--- F.

b. The above sequence is impleme nted as a micropro gram.

One of the control memory words could be used as a counter instead of a hardwar e counter .

6.3

SUB

MEM

Fetch and Defer sequenc es are similar to those of LDA.

90 6-1

Fetch and Defer sequen ces are simila r to those of LDA. Execut e

CP 1 CP 2

Execut el CP 1 CP 2 CP 3 CP 4 LDI

ACC <-- ACC I .

ACC <-- ACC + 1.

ACC <-- ACC + SR. STATE <-- F.

DATA

Execut e

CP 1 CP 2 CP 3 CP 4

6.4

READ. SR <-- ACC.(A ssuming we have a regist er called SR which is attache d to the BUS2 AND BUS3) MBR. ACC <-STATE <-- El.

ACC <-- (MBR) io-o or ACC <-- (IR) io-o· STATE <-- F.

JSR: Fetch and Defer sequen ces are simila r to those of LDA. Execut e

CP 1 CP 2 CP 3 CP 4

MBR <-- PC. MAR<- - o, (Assum ing we have a regist er which holds a consta nt zero.)

WRITE. PC<-- (IR) 7 _ 0 , STATE <-- F.

RET: Execut e

6.5

MPY

CP 1 CP 2 CP 3 CP 4

MAR<- - O, READ. PC<-- MBR. STATE <-- F.

MEM

The Fetch and Defer sequen ces are simila r to those of LDA. Execut e

CP 1 CP 2

READ. IF PSRz = 1 then STATE <-- F ELSE SR<-- ACC.

CP 3 CP 4

STATE <-- El.

91 6-2

Exec utel CP 1 CP 2 CP 3 CP 4

ACC <-- ACC + MBR. SR <-- SR - 1.

IF SR=

0

then STATE <-- F ELSE STATE <-- El.

We use two execu tion cycl es time to imple ment the mult iplic ation . This facil ity is assum ed to be provi ded in the syste m. We also use SR regis ter as in probl em 5.3.

6.6

SUB

READ. SR<- - ACC.

MEM

(Assu ming we have a regis ter calle d SR which is attec hed to the BUS2 and BUS3)

ACC <-- MBR. ACC <-- ACC'.

ACC <-- ACC + 1.

ACC <-- ACC + SR. GO TO FETCH. LDI

ACC <-- (MBR) io-o· GO TO FETCH.

JSR

MBR <-- PC. MAR <-- O, WRITE. WAIT. PC <-- (IR) 7 _ 0 • GO TO FETCH.

RET

MAR <-- O, READ. WAIT. PC <-- MBR. GO TO FETCH.

MPY

MEM MB

READ. IF PSRz = 1 then GO TO FETCH. SR <-- ACC. ACC <-- ACC + MBR. SR <-- SR - 1.

IF SR= 0 then GO TO MS. GO TO FETCH.

92 6-3

6.7.

FETCH

MAR~ PC READ MEMORY PC~ PC+ 1 IR~M BR INDEX1 ~ ACC - 1 GO TO EXECUTE

EXECUTE

MAR~ IR7_4 + INDEX1 READ MEMORY WAIT MAR~ IR3_0 + INDEX1 WRITE INDEX1 ~ INDEX1 - 1 If INDEX1 = -1 THEN GO TO FETCH Else GO TO EXECUTE

Machine Cycle FETCH

Minor Cycle CP1

6.8.

CP2 CP3 CP4

EXECUTE

CP1 CP2 CP3 CP4

Operations MAR~ PC READ MEMORY PC~ PC+ 1 IR~M BR INDEX1 ~ ACC - 1 STAT E~ E MAR~ IR 7-4 + INDEX1 READ MEMORY WAIT MAR~ IR3-0 + INDEX1 WRITE INDEX1 ~ INDEX1 - 1 If INDEX1 < 0 THEN STAT E~ F

93 6-4

6.9.

Machine Cycle FETCH

Minor Cycle CP1 CP2 CP3 CP4

EXECUTE1

CP1 CP2 CP3 CP4

EXECUTE2

CP1 CP2 CP3 CP4

Operations MAR~ PC READ MEMOR Y PC~ PC+ 1 IR~MB R INDEX1 ~ ACC - 1 STATE ~ E1 ACC ~ IR7_0 MAR~ PC READ MEMOR Y WAIT IR~MB R STATE ~ E2 MAR~ ACC + INDEX1 READ MEMOR Y WAIT MAR~ IR7_o + INDEX1 WRITE INDEX1 ~ INDEX1 - 1 If INDEX1 < 0 THEN STATE ~ F

Note that the content of the accumu lator is changed as a side effect of this instruction.

94 6-5

6.10

RWD or WWD n-bit device address (to accorood ate 2 n devices) ACC 0

0

I

X

X

15

I

X

I

X

I

X

I

X

. . - 11

HLT

1·

The device interfac e decodes the address on DSL and activate s the device, if it is addresse d.

Al terna ti vely, a n to 2 n decoder can be connecte d to DSL. Only one device will be selected , based on then-b it address on DSL.

Device selectio n lines (DSL)

DOL

DIL 6.11

0

Output device Input device Interfac e

10 9 8

. - . 0

I t It I JSR Bit

RET Bit

HLT

IF IR 1 0 =. 1 THEN GO TO JSR. IF IR 9 = 1 THEN GO TO RET.

JSR RET

(See problem 5. 6) .

(See problem 5. 6) .

95 6-6

Connec t all ASC compon ents to one bus. TRAl and TRA2 operat ions throug h the ALU will not be needed . A BUFFER ' registe r is needed , as part of the ALU to hold the operand during COMP, SHL and SHR operat ions. An additio nal BUFFER regist er is needed to hold the second operan d during ADD. During ALU operat ions, the op,e rand(s) is(are) first gated into the BUFFE R(s), ALU operat ions are perform ed and the resul~- is gated to the destin ation regist ers. Becaus e of t1.<:se additio nal transf ers, the single bus structu re will be slower than the multip le bus struct ure.

6.12

LDA Locatio n

6.13

Locatio n

2§_

.....UOPCODE 1 010 Branch if IR 10 = o 0101001 uADDRESS for M

AIOPCOD E 0 011 (IR)adr s to BUSl 001 INDEX to BUS2 100 BUS3 to MAR 011 ADD 00 NONE 00 NONE 00 NONE 00 NONE

Not used.

Locatio n

Locatio n 0

000 000 000 000 00 00 00 01

0

22

.,UOPCODE 0 000 NONE 000 NONE 000 NONE 000 NONE 00 NONE 00 NONE 00 NONE 00 NONE.

.AlOPCODE NONE NONE NONE NONE NONE NONE NONE READ.

Locatio n

TI

Locatio n

40

41

Same as locatio n 38.

AlOPCODE

000 NONE

010 MBR 100 MAR 010 TRA2 00 NONE NONE 00 00 NONE 00 NONE.

96 6-7

Location

tl

Same as location 39.

Location

li

JUOPCODE 0 000 NONE 010 MBR 001 ACC 010 TRA.2 00 NONE 00 NONE 00 NONE 00 NONE.

Location 1

ti

AlOPCODE

ooo Uncoditional branch

0100000

uADDRESS.

TIX

Location

107

Location

..uOPCODE 0 101 1 to BUSl 001 INDEX to BUS2 010 BUS3 to INDEX 011 ADD 00 NONE 00 NONE 00 NONE 00 NONE.

1

Location

Location

-UOPCODE 0 011 (IR)ADRS to BUSl 000 NONE 100 BUS3 to MAR 001 TRAl 00 NONE 00 NONE 00 NONE 00 NONE.

...uOPCODE 010 Condition code 1110010 uADDRESS for M7 Not used.

Location

Location

111

.-uOPCODE ERO-INDEX= l 0100000 uADDRESS Not used.

110

110

1

112

Same as location 39.

Same as location 38.

97 6-8

Location

113

Location

..uOPCODE 0 000 None 010 MBR to BUS2 110 BUS3 to PC 010 TRA2 00 NONE 00 NONE 00 NONE 00 NONE.

Same as location 40.

Location

114

115

Same as location 44.

6.14

At each indirect level, test the ;vis B bit of the effective address location. If it is non-zero, continue the indirection; if it is zero, effective address is found; stop address computation. A loop is needed within the microprogram for 'DEFER' to accomplish this computation.

98 6-9

6.15

15 14 13 12 11 10

I

I

OPCODE

9 8 7

i

INDIRECT TINDEX No indirect Pre-Indexed Post-Indexed Not allowed.

00 01 10 11

FETCH

MAR <-- PC, READ. <-- PC + 1.

PC <-- MBR. IR GO TO* OPCODE.

LDA

IF IR 10 _ 9 IF IR 10 _ 9

IND EXE

PRE

0

= 00 then GO TO IND. No indirected.

= 01 then GO TO IND. Pre-Indexed.

Post-Indexed.

READ. WAIT. <-- MBR. IR MAR <--IR+ INDEX. GO TO EXE. MAR <-- IR 6 _ 0 + INDEX. IF IR 10 _ 9 = 01 then GO TO PRE. Execute READ. WAIT. ACC <-- MBR. GO TO FETCH. READ. WAIT. MAR <-- MBR. GO TO EXE.

The other instructions have similiar changes as that of LDA. 6.16

Instead of PC <-- PC + 1 operation, we need a single control signal to increment PC (INC PC). This operation will not use the bus, thereby freeing the bus for other operations. This change will not effect any microinstrcution sequence of ASC.

6.17

JSR Execution

CP 1 CP 2 CP 3 CP 4

SP <-- SP + 1.

MBR <-- PC. MAR<-- SP, WRITE. PC <-- IR 7 _ 0 , GO TO FETCH.

CP 1 CP 2

MAR<-- SP, READ. WAIT.

RET Execution

99 6-10

CP 3 CP 4

PC SP

<-- MBR. <-- SP - 1, GO TO FETCH~

8 bits Address

6.18

2

b

to 4 Decoder 2

16-bit Address

10-bit segment registers _ _ _ _ _ ____,,ID

Segment Select

, - - - - - - - (0

6.19

Indirect and Indexed address computation remain the same, except the address now is 16 bits long, rather than 8 bits.

6.20

We will fetch the first instrtiction word during Fetch cycle and transfer to the appropriate microprogram , based on the opcode. The second word (if needed) is fetched in the microprogram for that instruction.

Fetch

MAR<-- PC, READ. PC <-- PC + 1.

IR 1 5 _ 8 <-- MBR. GO TO *OPCODE.

TCA

ACC <-- ACC' ACC <-- ACC + 1.

GO TO FETCH. LDA

MAR<-- PC, READ. PC <-- PC + 1.

IR 7 _ 0 <-- MBR. MAR<-- INDEX+ IR 7 _o• IF IR 10 = 0 then GO TOM. (Indirect) READ. WAIT. MAR<-- MBR. READ.

100 6-11

WAIT. ACC <-- MBR. GO TO FETCH. The other instructions are similarily changed.

6.21

New registers are R i , i=l, 2, 3, 4.

New instruction set All accumulator oriented instructions now would contain a register designator.

LDA STA ADD TCA SHL SHR

Ri,MEM Ri,MEM Ri,MEM Ri Ri Ri

BIP BIN

Ri,MEM Ri,MEM

RWD WWD

Ri Ri

Indexing LDA

Ri,MEM(Rj), i,j=l,2,3,4. and i = j.

Index manipulation TDX

TIX

Ri,MEM

Ri,MEM

LDX and STX are not needed.

BRU and HLT are not affected.

Instruction format 15

14

13

12

11

10

9

0

OPCODE

t

Indirect

f rndexj Register i

ooo

No Indexing.

The instruction format has accommodated two operand fields. Instead of restricting the second operand field to a memory address, a second register can be allowed as an operand. Although the design gets complex, such register to register operation would be faster.

101 6-12

6.22. We might discard the following instructions: BRU BIP RWD WWD SHL SHR TIX TDX mming the new Discarding these instructions will increase the difficulty of progra of the discarded machine since extra steps are needed to accomplish the effect a negative ing assign by ented instructions. For example, BRU can be implem ility of the capab the nally, value to the accumulator followed by a BIN. Additio do not can it new machine will be more limited than ASC. For example multiplication or division because does not have SHL and SHR. ions and can The other instructions are essential to the microcontroller operat not be eliminated.

6.23. An invalid (unknown) opcode should cause an interrupt to transfers the ·control to a trap handling routine.

102

occur which

6-13

6.26. ASC uses MAR to store the address of the memory location that is accessed. Since MAR has 16 bits, 216 address locations can be addressed. Now each location contains 16 bits of data. If each of the bytes is to be accessed separately then there will be twice as many locations to be accessed. That is, 2 times 216. Thus to address 217 locations MAR must have 17 bits, with 16 bits used to access a memory word and the remaining bit to select one of the bytes.

6.27. In ASC we have {TCA, HLT, SHL, SHR} as the set of zero address instructions. After fetching a byte, ASC should check the opcode to correspond to one of these instructions. If it does, then the instruction is fetched completely; the next instruction begins at the following byte. If not, the next byte needs to be fetched to complete the current instruction.

6.28. The instructions are to fit into 32 bits maximum.

32bits The addresses are 12 bit long.

There are 8 registers, which is 23. So, 3 bits can access them uniquely.

The present requirement is as below.

1. 8 instructions with 2 memory locations and a register reference.

12 bits each are needed for identifying memory locations and 3 bits for register reference, thus using up 27 bits. The remaining 5 bits can be used for opcode, thus allowing 32 instructions of this type.

Opcode Mem1

Mem2

Reg

Since there are only 8 instructions of this type, we can have a provision for 23 additional ones for the future and use the bit pattern of 11111 to indicate that other bits in the word need to be decoded to recognize other type of instructions.

Let us use two bits in Mem1 field above to indicate other instruction types: 00 – Type 2 below 01 – Type 3 below 10 and 11 for future types

6-14

Type 2: 50 instructions with 1 memory location & 1 register reference 25 < 50 < 26. At least 6 bits needed to identify each of 50 instructions uniquely; we have used two bits in Mem1 field already; we can use the remaining 10 bits to indicate up to 1024 of this type of instructions. 12 bits are used for the memory location and 3 bits for the register reference.

11111

00OPCODE Mem1

Reg

Type 3: 50 instructions with no memory locations or register reference.

Since 25<50<26, at least 6-bits needed to identify each instruction.

11111

01OPCODE

Only 13 bits are used; the unused 19 bits can be used to configure other types of instructions.

6.29 The Instruction Decoder circuit of ASC now needs to be expanded to decode the patterns shown above.

Leftmost 5 bits are decoded to recognize type 1 instructions.

If the output 31 of this decoder is active, next two bits are decoded into 4 patterns. Output 0 implies type 2, and output 1 implies type 3; others are for extension.

For Type 1, Memory1, memory2 and Register fields are activated.

For Type 2, only Memory2 and Register fields are activated.

For Type 3, only Register designation is activated.

6-15

Chapter 7 INPUT/OUTPUT (1/0)

11 10 9 8 7

7.1

I

I I

0

Ad dr es s

e oc cu pi es 8 bi ts in th ld fie s es dr ad e th e an d Si nc in de x fi el d tw o bi ts 11 (2 04 8) in st ru ct io n fo rm at, 2 um xim ma y ha ve ma in di re ct on e bi t,w e ac ed to AS C. rf te of I/ 0 de vi ce s in 7.2

15 14 . . . 7

I

I

.

.

.

3 2

Ad dr es s

l

0

I

4 to 16

"----J- de co de r

-- -> Io -- -> I1 -- -> I2 -- -> I3 -- -> I4 -- -> Oo -- -> 01

-- -> 06

--->'(

"- -- -- ~ -- -> ] No t us

ed

l si gn al s.

In pu t de vi ce s co nt ro l si gn al s. ou tp ut de vi ce s co nt ro en ab le th e I/ 0 de vi ce s. s Th es e co nt ro l si gn al -~ ,._A_c_c_u_m_u_l_a_t_o-.. <- D I~ ~16

~

-- • -- • -

• --

~

DOL

- ~ -s----_--_--_--- ~

103

7-1

7.3

00 00 00 01

se d in He xa Ad dr es se s ar e ex pr es = 4 di gi ts ). ts de ci m al fo rm (l6 biis fro m 00 00 to e ac ROM ad dr es s sp 0F FF . is: Th e er ro r ci rc ui tr y o Ad dr es s di gi t is 12 ') (i .e . A1 s'A 14 'A 13 'A

ROM

0FFF 1 - - - - - - - t 10 00 RAM

4

w ri te

FFFF Er ro r A 0 , ar e th e wh er e, A 15 th ro ug h in g th e m os t ad dr es s bi ts , A 15 be si gn if ic an t bi t.

7.4

I7 Io I1 I2 I3 I4 Is I6 1 d d d d d d d 0 d d 1 d d d d d 1 0 0 d d d d d d d d 1

d d d 1

02 01

= =

0

d d 1 0 0

d

1

1 0 0 0

0 0

0 0

0 0 0 0 0

0

0 0

0 0

0 0 0 0 0

02 01

Oo

1 1 0 0 1 1 0 0

1 0 1 0 1 0 l 0

1

1 1 1 0 0 0 0

ill be lo w. ar e lo w, th e ou tp ut w ts pu in l al If : te No

Oo

+ Is + I6 + I7 I + I6 + I7 I2 I4 'Is ' + I3 I4 'I s 6' + Is I6 + I7 ' = I1 I2 'I4 'I6 ' + I3 I4 'I I4

I4~

H = = = j- /

0~

104

7-2

-I2--l

I 4I I 5 , II I

/

I:3 I 4'

Is •- -.. .._ _- -

I5---I7-----

7. 5

15 14 . l:,.. ____

... 6 __

_

5

3

4

_ __ .__ _

__ _.__

0

1

2

__ ._ _- -__ ._ __ _. .~

-- J

e m ay ha ve se le ct ch ip s, w to ed us be n B it s 15 to 6 ca be r o f I/ 0 p o rt s.

2 10 m ax im um nu m

7. 6

In pu t

BCD) ,--------•( D-----

----4.1

cs

4

( OV)

R Sl - RSS DT AC K

R/W

DT AC K

3

Do - D7

R/W Do -

PB 4 -B 7

Lf-

D7

M C6 82 30

M C6 80 00

7- se gm en t d is p la y

105

7-3

(C on tin ue d) In it ia li ze

PGCR PADDR PBDDR PACR PBCR PADR PBDR TABLE

EQU EQU EQU EQU EQU EQU EQU EQU

$1 00 00 1 $1 00 00 3 $1 00 00 7 $1 00 00 D $1 00 00 F $1 00 01 1 $1 00 01 3 $6 00 0

on al ;S el ec t un id ir ec ti ;8 -b it mo de mo de ;B it in pu t/ ou tp ut MOVE.B #$ FF ,P AC R ;f or po rt A MOVE.B #$ FF ,P BC R ;A ll bi ts of A ar e in pu t MOVE.B #$ 00 ,P AD DR ;A ll bi ts of B ar e ou tp ut MOVE.B #$ FF ,P BD DR ta bl e ;AO - po in te r to MOVEA.L TABLE,AO ;S av e po in te r.

11 MOVEA.L AO ,A l ov e 11 01 11 01 11 to Al ;M O ,D 77 #$ by MOVEQ ;l oc at io n po in te d MOVE.B DO, (A l)+ #$ 24 ,D O MOVEQ MOVE.B DO, (A l)+ ;L oa d th e 7- se gm en t ta bl e #$ 5D ,D O Se e MOVEQ ;i nt o th e m em or y( ot e th at l)+ (A I DO E.B MOV ;p ro bl em 1. 15 ). N #$ 6D ,D O MOVEQ ;0 7 is th e MSB. MOVE.B DO, (A l)+ #$ 2E ,D O MOVEQ MOVE.B DO, (A l)+ #$ 6B ,D O MOVEQ MOVE.B DO, (A l)+ #$ 7A ,D O MOVEQ MOVE.B DO, (A l)+ #$ 25 ,D O MOVEQ MOVE.B DO, (A l)+ #$ 7F ,D O MOVEQ MOVE.B DO, (A l)+ #$ 2F ,D O MOVEQ MOVE.B DO, (A l)+

MOVE.B #$ 00 ,P GC R

START

CL R. L MOVE.B

Dl PA DR ,D l

;i np ut fr om A in to er Dl ;p ro ce ss or re gi st

MOVE.L ADDA.L MOVE.B

D l,A l AO ,A l A l,D l

MOVE.B JMP

Dl ,P BD R START

s ;E ff ec ti ve ad dr es tt er n pa ;R ea d ?- se gm en t ;i nt o re gi st er Dl ;O ut pu t to B ;R ep ea t

106

7-4

dr es s EN SP <- - St ac k Ad .

TH 1 = TF IN IF AD T1 : ELSE M AR <- - PC, RE 1. + C THEN PC <- -P T 2: IF INTF = 1 THEN PC <- - 6 ELSE IR <- - MBR. T3 : IF IN TF = 1 THEN ST AT E< -- F, DISABLE IN T, DGE T ii: IF INTF = 1 RESET IN T, ACKNOWLE ELSE (a s be fo re ) ca tio n 7) in e (S ta rt in g at lo ut Ro e ic rv Se t up In te rr

7.7

PUSH PUSH PUSH PUSH PUSH PUSH ENABLE

PC ACC 1 2 3

PSR INTERRUPT

POLL SERVICE DISABLE INTERRUPT PSR POP 3 POP 2 POP 1 POP ACC POP ENABLE INTERRUPT PC POP 7.8

or ed to ac co mm od ate ve ct m 6. 7. , ed ir qu re ge an ch le pr ob Th e on ly e po lli ng ro ut in e of in te rr up ts is to the is re pl ac ed by : Th e po lli ng ro ut in ACKNOWLEDGE, IN T. Re ad V ec to r.

PC <- - M [V ec to r]. in g to th e l~ ca tio n co rr es po nde in te rr up t ry mo me e th at th of th As su me nt ai ns th e ad dr es s de vi ce ad dr es s, co th at de vi ce . se rv ic e ro ut in e fo r

107

7-5

7.9

(a)

OUTPUT DEVICE

CPU

OUTPUT and DSL = Ad dre ss: Dat a Bu ffe r<- - DOL, IN T< -- 1.

WWD: DSL <-- Ad dre ss, DOL <-- Dat a, OU TPU T<- - 1.

INT : Sav e STATUS. RECOGNI E INT .

OU TPU T<- - 0. (b)

OMA

CPU AR <-- Ad dre ss.

WCR <-- Cou nt.

TRA NSM IT< -- 1.

INT : Sav e STATUS. RECOGNI E INT .

TRA NSM IT< -- 0.

TRANSMIT and DSL = Ad dre ss: IF WCR = 0 THEN MBR <-- Dat a, MA R<- - AR, WRITE, WCR <-- WCR - 1, AR <-- AR · + 1.

WCR = 0: IN T< -- 1.

108

7-6

7.10

Mu ltip lex er Cha nne l Cha nne l Buf fer

INPUT

DEVICE 1

Rea d/ Wri te

Tra nsf er

C

p

u I M E

M 0

erro r

OUTPUT DEVICE 1

B

u

f

Mu ltip lex Con trol Sca n

E R

R y

~ AOORESS/

Cha nne l DR: DA:

I

I I

I

Dat a Rea dy Dat a Acc epte d

a/tr ans fer s dat a from or to, Dat a Sel ect/ che ck: Rec eive s dat the sca n con trol sig nal ; the dev ice buf fer, sele cte d by sfe r to/f rom cha nne l buf fer.

Tra nsf er con trol s the dat a tran DR and DA:

ice. ind ica te the sta tus of the dev

read y to tran smi t/re cei ve dat a, For eac h sca n, if the dev ice is blo ck cou nt are read , dat a cor resp ond ing memory add ress and and blo ck cou nt are upd ated . gat her ed, tran sfe rred and add ress as plet e inte rru pt 1s gen era ted , Err or inte rru pt or tran sfe r com app rop riat e.

109

7-7

7.11

iti on s. ; ge ne rat es err or co nd Ch eck s da ta for va lid ity ns fer red to CB co lle cte d in DCB and tra Du rin g inp ut, da ta are en DCB 1s fu ll . for CPU tra ns mi tta l, wh

Ch eck :

I

t

DCB. CB are tra ns fer red int o Du rin g ou tpu t, da ta fro m

I

Ch eck

D

C

C

B

p

D

Re cei ve

Ch eck

E

V

Transmit

C

u

B

Tra nsf er Read/Write

I C

E

s

Cllannel C:Ontrol COUNT De vic e -No. DCB CB:

Da ta Co lle cti on Bu ffe r Ch ann el Bu ffe r

AR

TOM<\R

110

7-8

7.1 2

ch We wi ll ass um e tha t the L. DO sig nif ica nt 8 bit s of

on the lea st ara cte r to be pri nte d is

Ad dre ss De cod er

C

PRINTER SELECT

p

u BUSY

Q

s BUSY R DOL

PRINTING COMPLETE

PRINT A rnARAL7ER

PRINT MECHANISM

8

(1) (2) (3) (4) (5)

Q'

Ad dre ss sen t on DSL.

Y sta tus .

BUSY. CPU rec eiv es BUSY/NOT BUS PUT lin e, when pr int er NOT SY. OUT ts se and A DAT ds sen BU CPU nts ch ara cte r and goe s NOT PRINTER goe s to BUSY, pri rem ove s da ta.

CPU res ets OUTPUT lin e and

111

7-9

7.1 3 DSL OUTPUT

Ad dre ss Dec ode r C

BUSY NOT FULL

p

u DT

8

I

PR,INI' BUFFER PRJNr:t-mIANm!

ple tin g the NOT BUSY sig nal , aft er com Pri nt Me cha nism set s the in PRINT BUFFER. pri nti ng of 80 cha rac ter s o Pri nt Bu ffe r are tra nsf err ed int I 80 cha rac ter s fro m Da ta m is NOT BUSY. Bu ffe r, when pri nt me cha nis s the rac ter s from CPU and upd ate I DATA BUFFER rec eiv es cha COUNTER. y gen era tin g n Cou nt rea che s 80; the reb I FULL fli p flo p is set whe a bus y sig nal for CPU. 1s 0 .

DATA Bu ffe r onl y when BUSY o int a dat its nsm tra CPU I

I

112

7-10

7.1 4

MEMORY

DG

IBUSY

u

CG

.~

CONTROLLER _CK

- DR

'JI'

I

lo

~ I,

.~

BUS

1 DMA

CPU

I

I

BUS REQUEST LINES (CR,DR) BUS GRANT LINES (CG,DG) BUS BUSY fli pfl op (BUSY) Tr an sfe r Co mp lete (TC)

th thr ee te seq ue nti al cir cu it, wi The co ntr oll er is a two sta ou tpu ts (CG, DG). inp uts (TC, CR, DR) and two (CR,DR/CG,DG) 00/ 00

113

7-11

7.15

ROM

Ad dre ss

BC

I E

8 WORDS, de vic e ad dre sse s

L---------

are sto red in ROM 1n pr ior ity ord er.

I, ,

' ,,

3 to 8

.

1

dec od er • • •

INT. SIGNAL fro m Dev. 0

•

•

•

As in

Fig . 6. 11-

INT. Sig na l fro m Dev. 7

114

7-12

7.16 RWD

Ad dre ss 1

wwrif TYPE

1A ddr ess 2

' - -_ _ _ _ _

I

I

_ _ _- _ _ _ _ _ _..____

__.__

i,,1,,1J

t Bu sy) Read DMA Sta tus (Bu sy/ No

J

l

tra ns fer Command DMA to ini tia te t.

TYPE= inp ut or ou tpu (on e bit fie ld)

Tra nsf er Memory Bu ffe r add to AR.

Address 3 ] Address 4

res s

Tra nsf er COUNT to WCR.

.

Ad dre ss of the DMA dev ice

Ad dre ss 1 : Ad dre ss 2 :

Ad dre ss of AR.

Ad dre ss 3 :

Memory Bu ffe r Ad dre ss.

Ad dre ss 4 :

Ad dre ss of WCR.

ed by eac h DMA dev Th ree add res ses are con sum (Ad dre ss 1 2 and 4 ).

'

7.17

End of Tap e

BUSY

BUSY

DSL DATA CPU

ice

CASSETTE INTERFACE

READ

CASSETTE

WRITE Err ors PROTOCOL SIMILAR TO PROGRAMMED I/0

Ge ner ate s ap pro pri ate Re ad/ Wr ite for ma ttin g.

to rec eiv e the dat a ou t se ria lly and ift sh to ded nee is r ve A dri ch ara cte r, lin e; to tra nsm it end of l ria se the on a dat ut the inp che ck for e typ e of co ntr ols and to end of rec ord , end of fil err ors .

115

7-13

7.18

Pro 0 ramme d I/0 Mode are neede d; A Minim um of two major cycle s (fetch , execu te) the numbe r of and slow is e devic the addit ional cycle s neede d, if . speed e devic addit ional cycle s depen ds on the Inter rupt Mode I/0 A typic al inter rupt servi ce routin e follow s: Cycle s

Routi ne

1 2 2 2 2 2 1 l 2 .2

Disab le Inter rupt STAT STX T+l,l STX T+2, 2.

STX T+3,3 Store PC Enabl e Inter rupt Ackno wledg e Inter rupt Read Vecto r Read Dat.a Disa~ ie Inter rupt

1

2 2 2 2

LOA T LOX T+1,l LDX T+2,2 LDX T

,3

1

enabl e Inter rupt JMP* PC

2

TOTAL

29

s much more than This overh ead for I/0, may not be justif ied unles a unit of data is trans ferre d.

7.19

BEGIN

LOOP

TEMP

ORG STA LDA SHR LDA LDX SHR TDX LDA SHR SHR HLT BSS END

0

TEMP =O TEMP =16, 1 LOOP ,l =3

.save Data .outp ut "Sta rt" bit .outp ut dtat bits .outp ut "Stop " bits

1

BEGIN

t regi ster.

Accu mula tor shou ld be conf igure d as a shif

116 7-14

7.22 . Suppose a processor receives multiple interrupt requests at about the same time, it should service all of them before returning control to the interrupted program. For holding these multiple requests, we can use stack or queue or one stack per interrupt. In stack mechanism, all the multiple interrupt requests which occurred at the same time are stored in the stack. Then processor processes multiple interrupt requests in Last In First Out fashion. Similarly in the queue mechanism, they are stored and processed in First In First Out fashion . As all the interrupts occurred at the same time and we are storing them in one data structure, we are not able preserve the order of arriving of interrupts. The ideal mechanism for holding these interrupts is to use one stack per interrupt. As shown in the below figure, there will be one stack per interrupt.

Stacks Interrupt 1

I I

Interrupt 2

I I

Interrupt 3

I I One stack per interrupt

7.23

Number of instructions executed by processor per second is 1000 K Each instruction requires an average eight bytes of information.

1000 K instructions requires 8 MB of information transfer (8 X 1000 K = 8MB) As given in the problem, Bandwidth of the bus system is 5 MB per second. So, the bus system itself is too busy. There is no bandwidth available for OMA Controller. We need to find an alternative (like another bus ) for OMA Controller.

7.24

Each byte of 1/0 requires two instructions.

Each instruction requires eight bytes of information (as given in previous problem) So, for each byte of 1/0, it needs to transfer 16 bytes of information (2X 8 = 16 bytes) Bandwidth of the bus system is 5 MB per second. So, number of bytes of 1/0 can be transferred are 312500 (SM / 16 = 312500) bytes

117

7-15

7.29 The GPU has a series of registers that the operating system maps. These permit the CPU to access GPU's memory and instruct the GPU to perform operations. The CPU plugs values into those registers to map some of GPU's memory so that the CPU can access it. Then it loads instructions into that memory writes a value to a register that tells the GPU to execute the instructions the CPU has loaded into its memory.

The information consists of the software that the GPU needs to run. This software is bundled with the driver and then the driver handles the responsibility split between the CPU and the GPU (by running portions of its code on both devices). The driver then manages a series of "windows" into GPU memory that the CPU can read from and write to. Generally, the access pattern involves the CPU writing instructions or information into mapped GPU memory and then instructing the GPU, through a register, to execute those instructions or process that information. The information includes shader logic, textures, and so on.

7.30 The general procedure is for the tablet PC to sense the signal from the wireless router and then communicate with it to get authentication to use the bandwidth for communication. The set of standards for implementing the wireless connection is specified by the IEEE 802.11. The communication is in 2.4, 3.6, 5 and 60 Hz frequency bands. The standards are created and maintained by the standards committee for IEEE LAN/MAN. The commonly used versions are 802.11a, 802.11b, 802.11g & 802.11n.

Here we shall give a brief account of 802.11.

Current 802.11 standards define "frame" types for use in transmission of data as well as management and control of wireless links.

Frames are divided into standard sections. Each frame consists of an MAC header and frame check sequence (FCS) and sometimes a payload. The first two bytes of the MAC header form a frame control field specifying the form and function of the frame. The frame control field is further subdivided into the following sub-fields:

7-16



Protocol Version: Two bits representing the protocol version.

Currently used protocol version is zero. Other values are reserved for future use.



Type: Two bits identifying the type of WLAN frame. Control, Data and Management are various frame types defined in IEEE 802.11.



Sub Type: Four bits providing additional discrimination between frames. Type and Sub type together to identify the exact frame.



ToDS and FromDS: Each is one bit in size. They indicate whether a data frame is headed for a distribution system.

Control and management frames set these values to zero. All the data frames will have one of these bits set. However communication within an IBSS network always set these bits to zero.



More Fragments: The More Fragments bit is set when a packet is divided into multiple frames for transmission. Every frame except the last frame of a packet will have this bit set.



Retry: Sometimes frames require retransmission, and for this there is a Retry bit which is set to one when a frame is resent. This aids in the elimination of duplicate frames.



Power Management: This bit indicates the power management state of the sender after the completion of a frame exchange. Access points are required to manage the connection and will never set the power saver bit.



More Data: The More Data bit is used to buffer frames received in a distributed system. The access point uses this bit to facilitate stations in power saver mode. It indicates that at least one frame is available and addresses all stations connected.



WEP: The WEP bit is modified after processing a frame. It is toggled to one after a frame has been decrypted or if no encryption is set it will have already been one.



Order: This bit is only set when the "strict ordering" delivery method is employed. Frames and fragments are not always sent in order as it causes a transmission performance penalty.

7-17

The current 802.11n builds on the previous 802.11 standards by adding multiple-input multiple-output (MIMO) and 40 MHz channels to the PHY (Physical layer) , and frame aggregation to the MAC layer.

7.31 The printers can be made accessible over a network in two ways. One way is to connect a printer to a computer which will share this printer with other computers on the network. Another way is for the printer to have its own MAC id and itself connect directly to the network with either Ethernet or wireless connection. This way it is no different from any other networked device and communicates over the network with the usual network protocols for data transfer. These printers usually have considerable buffer and on device memory to collect the data before it starts printing.

The dedicated printers are those which are connected directly to a computer and are not shared. They receive data in many different ways, such as from USB, memory cards, optical disks, internal memories and even Bluetooth transmission.

7-18

Chapter 8 PROCESSOR AND INSTRUCTION SET ARCHITECTURES

8.2

We assume that this machine is a two's complement system.

[ _____________ l_c_l_z ]_o_l_P_I_N_ I PSR (a)

A B

+l -1

0 000 0001

± 1. 111 1111 1 0 000 0000

11 1 0 0 0 (b)

A B

12 -6

PSR

0 000 1100

± 1_ 111 1010 1 0 000 0110 11 0 0 1 0

( C)

A B

31 31

PSR

0 001 1111

±Q 001 1111 0 011 1110 ., 0 0 0 l

( d)

A B

12 -13

0

0 000 1100

± 1. 111 0011 l

111 1111

10 0 0 0 11

(e)

A B

PSR

96

0 110 0000

97

±Q 110 0001

PSR

1 100 0001

[

lo 0 l

1

1

fSR

118 8-1

8.3

IBM 46.24

X

10- 3 = (0.0000 1011 1101 0110

011 1111

0

16 places of accura cy

• ) 2

. . ) X 16-l

= (0.1011 1101 0110

Sin Expone nt

.

Fractio n 1011 1101 0110

64-1=63 2.46

10 2

X

= 246 =(1111 0110) 2

=(0.11 11 0110)

sign Ex~one nt

X

16 2

fka~tiQD

ol

I o I 100 0010 I 1111 0110 0000 64+2=6 6

IEEE Standa rd Format 46.24

X

10- 3 = (~1011 1101 0110

Sign Expone nt 1

o

2. 4 6

1 0111

1011

t 127-4= 123

X

Fractio n

o 11 1101 0110 . . . I

10 2 = (0.1111 0110)

X

2g

Fractio n

Si

111 0110 0000

0

.

.

.

0

127+&= 135

119 8-2

8.4

in the low In the little endien mode, the least significant byte of the data is stored s. The location sed addres higher in addressed byte followed by remaining bytes big endien .mode does the opposite.

The hexadecimal equivalents of 31 and 241 are 1F and F1 respectively.

Byte Address

Little Endien

Big Endien

0

1F

1F

1

F1

F1

If the two endien formats of storage are as shown above, then (a) the value in the 16-bit word made up of the two bytes O and 1 in big mode is 1FF1. The decimal equivalent of 1FF1 is 8177.

endien

(b) the value in the 16-bit word made up of the two bytes O and 1 in little mode is F11 F. The decimal equivalent of 1FF1 is 61727.

8.5

endien

Micro operations for ADD instruction for Big Endien format( assuming opcode 4 bits, 6 bits for each addresses of A, B ) are as follows:

Machine Cycle FETCH

Operations

EXECUTE 1

MAR~ IR9-4 READ MEMORY WAIT ACC ~ MBR

EXECUTE2

MAR~ IR3--0 READ MEMORY WAIT ACC ~ ACC + MBR

EXECUTE3

MAR~ (IR 9-4) + 1 READ MEMORY WAIT ACC ~ ACC + MBR

as

MAR~ PC READ MEMORY PC~ PC+ 1 IR~M BR

120 8-3

EXECUTE4

MAR ~ ( IR3_o) + 1 READ MEMORY WAIT ACC ~ ACC + MBR ACC ~ ACC + PSR ( Carry bit)

Micro operations for ADD instruction for Little Endien format( assuming as 4 bits, 6 bits for each addresses of A, B ) are as follows:

Machine C cle FETCH

Operations

EXECUTE1

MAR ~ (IR 94 ) + 1 READ MEMORY WAIT ACC~ MBR

EXECUTE2

MAR ~ ( IR3_0 ) + 1 READ MEMORY WAIT ACC ~ ACC + MBR

EXECUTE3

MAR~ IR94 READ MEMORY WAIT ACC ~ ACC + MBR

EXECUTE4

MAR~ IR3_0 READ MEMORY WAIT ACC ~ ACC + MBR ACC ~ ACC + PSR ( Carry bit)

opcode

MAR~ PC READ MEMORY PC~ PC+ 1 IR~ MBR

121

8-4

8.6

I

I

SL

SL SR

I

.

-~

POP PUSH

SL SR

SL SR

SL SR ' . ,.

'

I

DATA

I

,.._

.,

SR .....

'

1 ---i--"" ~ .. ,

)-DER-

Level 1

UN

2

0

3

0

. "

.

. .

. .

.

.

.

.

.

~

FLOW

. .

PUSH 0

8 ~

av ER-

-

FLOW DATA BITS

Control Register

SL= Shift left SR= Shift right The control register is also a shift register; A 1 is shifted into it at each PUSH; at each POP, a o is shifted into it from the other (level 8) end. When the stack is FULL, all the bits of control register will have ls; when the stack is EMPTY, they are all Os .

122

8-5

PUSH

8.7

OVERFLOW

READ

WRITE 0

8

DOWN

PUSH

WORD RAM

1

DELAY 4

bits/ word

POP 7

MBR

DATA

PUSH----> WRITE. MAR <-- MAR + 1.

POP

8.8

---->MAR<- - MAR - 1.

READ.

Assume PUSH and POP operations, as in problem 7.5; MEM is a dedicated memory location.

PUSH:

SSP STA* LDA ADD STA LSP

MEM MEM MEM =l MEM MEM

POP:

SSP LDA ADD STA LDA* LSP

MEM MEM =-1 MEM MEM MEM

ADD:

POP STA POP ADD PUSH

TEMP TEMP 124 8-6

8.9

PUSH

ADD

El

8.10

CP 1 • CP 2 CP 3 CP 4

MBR <-- ACC. SP <-- SP + 1.

MAR <-- SP, WRITE. STATE <-- F.

CP 1 CP 2 CP 3 CP 4

MAR <--

CP 1 C~2 CP 3 CP 4 CP 1 CP 2 CP 3 CP 4

MAR <--

SP, READ.

-

1. <-- SP ACC <-- MBR. STATE <-- F.

SP

SP, READ.

-

1. <-- SP ACC <-- MBR. MAR <-- SP, READ, STATE <-- El.

SP

MBR <-- ACC + MBR, WRITE. STATE <-- F.

We may use index addres sing mode to access an operan d whose addres s is in a memory locatio n.

Exampl e:

Addres s

50

Addres s

.

-.

Operan d ..

LOX

LDA

#H50,l 0,1

.

8.11

8.12

The value of the addres s field of the instruc tion is the offset X 2 - X 1 . If the addres s field is 10 bits10 long, the range · of branch es possib le is betwee n -2 and 2 10 - 1.

Immedi ate

Addres sing

EA: DATA is in the addres s field of the instruc tion.

Paged

EA:

Addres sing

(Page table base registe r) + Page No. $ Offset . $ is the notatio n of concat ation.

Base-R egister

Addres sing

EA: Conten ts of base regist er+ Offset .

125 8-7

Relative

Address ing

EA: Content s of PC+ Offset.

Implied

Addressi nq

EA: TL, SL in STACK manipul ation: PUSH, POP, ADD.

8.13

Zero Address Machine:

LOAD

a

PUSH, TL 0 M[a]

LOAD

X

PUSH, TL 0 M[x] SL 0 SL · TL, POP

MPY LOAD

PUSH, TL 0 M[x]

X

MPY LOAD LOAD MPY

SL 0 SL · TL, POP PUSH, TL 0 M[b] PUSH, TL 0 M[x] SL 0 SL · TL, POP

b X

SL 0 SL + TL, POP

ADD LOAD

PUSH, TL 0 M[c]

C

SL 0 SL+ TL, POP

ADD Result

STORE

M[R] 0 TL, POP

Result is stored in "Result" memory location.

a. One-Address Machine:

LOAD MPY MPY STORE LOAD MPY ADD ADD STORE

ACC 0 M[a] ACC 0 ACC • M[x] X ACC 0 ACC • M[x] Temp M[A] 0 ACC b ACC 0 M[b] X ACC 0 ACC · M[x] Temp ACC 0 ACC + M[Temp] C ACC 0 ACC + M[c] Result M[Result] 0 ACC

a X

Result is stored in "Result" memory location.

126 8-8

b. Two-Address Machine: MPY MPY MPY ADD ADD

a, x a, x b, x a, b a, c

M[a] f- M[al . M[x] M[a] f - M[al . M[x] M[a] f - M[b} . M[x] M[a] f - M[al + M[b] M[a] f - M[al + M[c]

Result is stored in "a" memory location. c. Three-Address Machine: MPY MPY MPY ADD ADD

a, x, a a, X, a b, x, b a, b, a a, c, c

M[a] f - M[a] • M[x] M{a] f - M[a] • M[x] M[b] f - M[b] · M[x] M[a] f - M[al + M[b] M[a] f- M[al + M[c]

Result is stored in "c" memory location.

8.14

Numb er of stack leve ls

(a) LOAD LOAD ADD LOAD LOAD LOAD LOAD MPY SUB MPY LOAD LOAD ADD DIV ADD STORE

1 2 1

M

N

2 3 4 5 4 3 2 3 4 3 2

p Q

R

s

T y

1 0

F

127

8-9

( c)

(b)

( d)

·Q

TEMP p

T,V R,S Q,R P,Q P,T N,P M,N F,F F,M

TEMPl M N F Tota l Prog ram Lenq th (Bits }

No. of Add ress

No. of Opco des

(.a) (b) (c)

ADD MPY SUB MPY DIV ADD ADD SUB ADD

T V TEMPl R s TEMP

LOAD ADD STORE LOAD MPY STORE LOAD SUB MPY DIV ADD ADD STORE

272 312 360

9

16 13

13 18

9

ins(e) Assu ming one fetc h mem ory cycl e for each and, the oper each truc tion and one cycl e to fetc h tota l mem ory cycl es need ed are (a)

25

(b)

26

(c)

27.

in prog ram (a). (f) At the most 5 stac k leve ls are used ence sequ If the stac k is only 4 leve ls deep , load ing then and S Q-R* ute comp ., need s to be alte red (i.e .

P) load

8.16

Tran slate MAR <-- PC, READ. PC <--P C+ 1.

MAR <-- MBR + ACC, READ. WAIT. ACC <-- MBR.

128 8-10

8.23 . Instruction Format:

I

I

I

I

I

I

I

I

I

11

I

I

I

I

I

I

I

I

I

I

I

111

Destination (12 bits)

Source (12 bits)

Opcode (8 bits)

I

I

I

I

I

I

I

I

12 The range of memory that can be addressed is (0- 4K) (since 2 =4K).

Instruction Format to address 64K memory: Indirect

Indirect

1 I

I

I

I

I

I

I

I

I

11

I

I

I

I

I

11

I

I

I 1 11

I

I

I

I

I

I

111

Destination (11 bits)

Source (11 bits)

Opcode (8 bits)

I

11-bit addresses can be used to address 2K memory only. But these 2K memory locations in turn contain the 16 bit address, so that we can address 64K memory.

8.24

Instruction Format for Zero address Instructions: Class code (2

!Tl

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

111111111111111

Opcode (30 bits)

The maximum number of instructions the machine can have in this class ( 30 Zero address) are 2 .

Instruction Format for One address Instructions:

Class code (2 bits)

I

I

I

I

I

I I

I

I

I

I

II

I

I

I

I I 111111111111111 Source (16 bits)

Opcode (14 bits)

129 8-11

The maximum number of instructions the machine can have in this class ( 14 One address) are 2 .

Instruction Format for Two address Instructions: Indirect addressing bit

Indirect addressing bit Class code(2 bits)

l

l

I I I I I I I I I, I I I I I I I 11 I I I, I I I I I I I I I 111 Opcode (6 bits)

Source (11 bits)

Destination (11 bits)

The maximum number of instructions the machine can have in this class 6 (Two address) are 2 .

130 8-12

8.26 A “core” can be defined as a central processing unit (CPU) that read and execute program instructions. These instructions include conventional CPU instructions such as add, move data, etc. A multicore processor is a single computing component with two or more independent cores. Using multiple cores gives such processors the ability to run multiple instructions at the same time, thus increasing the overall speed of programs cooperative to parallel computing.

We will focus on Intel Core Microarchitecture which offers a series of processors ranging from a single core per processor to six cores. This architecture provides the following 4 features that apply to both singlethreaded as well as multi-threaded workloads: 1. Intel® Wide Dynamic Execution: enable each processor core to fetch, dispatch, execute in high bandwidths to support retirement of up to four instructions per cycle.

— Fourteen-stage efficient pipeline — Three arithmetic logical units — Four decoders to decode up to five instruction per cycle — Macro-fusion and micro-fusion to improve front-end throughput — Peak issue rate of dispatching up to six micro-ops per cycle — Peak retirement bandwidth of up to 4 micro-ops per cycle — Advanced branch prediction — Stack pointer tracker to improve efficiency of executing function/procedure entries and exits 2. Intel® Advanced Smart Cache: delivers higher bandwidth from the second level cache to the core, and optimal performance and flexibility for single-threaded and multi-threaded applications.

— Large second level cache up to 4 MB and 16-way associativity — Optimized for multicore and single-threaded execution environments — 256 bit internal data path to improve bandwidth from L2 to firstlevel data cache 3. Intel® Smart Memory Access: prefetches data from memory in response to data access patterns and reduces cache-miss exposure of out-of-order execution.

— Hardware prefetchers to reduce effective latency of secondlevel cache misses — Hardware prefetchers to reduce effective latency of first-level data cache misses — Memory disambiguation to improve efficiency of speculative execution execution engine 4. Intel® Advanced Digital Media Boost: improves most 128-bit SIMD instruction with single-cycle throughput and floating-point operations.

— Single-cycle throughput of most 128-bit SIMD instructions — Up to eight floating-point operation per cycle

8-13

— Three issue ports available to dispatching SIMD instructions for execution 8.27 A system on a chip or system on chip (SoC or SOC) is an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixedsignal, and often radio-frequency functions—all on a single chip substrate.

A typical application is in the area of embedded systems.

8.28 Processors designed for use in smart phones have the following architectural features. They are typically housed in a smaller chip package since the space available in smart phones is very limited. Since smart phones do not have the luxury of having fans to cool it down, these processors are required to consume low power and run on lower voltages when compared to their desktop counterparts. They also have more “sleep mode” capabilities. A mobile processor can be throttled down to different power levels or sections of the chip can be turned off entirely when not in use. Further, the clock frequency may be stepped down under low processor loads. This stepping down conserves power and prolongs battery life, which is an important requirement for smart phones.

8-14

Chapter 9 MEMORY AND STORAGE

9.1

Memory system capacity 64k X 4 64k X 8 32k X 4 32k X 16 32k X 32 10k X 8 10k X 10

9.2

No. of bits in

No. of bi.ts in

MAR

MBR

16 16 15 15 15 14 14

4 8 4

16 32 8

10

No. of chips needed if the chip capacity is 2k X 1 lk x 8 lk X 4 128 32 64 256 64 128 64 16 32 256 64 128 512 128 256 40 10 20 50 13 25

(a) Storage capacity per inch = 800 bits length of the tape = 2400 ft. :.Maximum capacity == 800 X 2400 x. 12 = 23040000 characters Maximum data transfer rate= 800 X 10 = 8000 characters/sec . (b) Storage Capacity= 49 tracks X 4K bits/track= 196K bits.

Maximum transfer rate; 4K bits in 60/3600 seconds r.e. 4K X 3600/60 = 240K bits/second.

Maximum access time= Time to move to 49th track+ one rota_ tion 3 + 60 /3600 seconds 4 9 X 10· seconds = 0.065666 65.666 milliseconds. or

131 9-1

9.5 (a) Number of chips =

= 128 16k x 8 lk X l Chips ars arranged as a 16 x 8 array.

2..

I C.E

AD~

To

r

T

CE.

C-E

... .

1 I

'I c.E

1/o

I/o i

lo

·Row SE.lEC.T L

t

l

l

A~ +'-

Row SELECT 2.

cE

CE

10

)o bii::s

4- bi ts

• • •

MAR

2

I/o

I/o

i

1'

Vo t-

..

..

•

10

4 ..~

.•

TO atid.r. \;ne. S of a(_h c:.h; p.

•

•

•,1

Lf- TO if,

....

+10

De..c.ocl er

. ...

1

I/o

I

I

lo

~

~ ✓

...

.,

1/o

...

I

1b

2.

l c l-iip e.Mb\c.s

oi e.~c.h '(ow

l

oi c..hipS MB R. ( s bi-t .s)

All ·R/W lines are connected together,

(ROW SELECT)

to form system

R/W· signal.

CE= Chip enable R/W=

Read/wr;i.te

I/0= Input/output = 10 address lines

ADRS

132 9-2

of chips needed

( b) No.

=

16k

= 16

8

X

2k X 4 each. chips Arranged as 8 rows of 2

l 1 bits

3

4

3 TO 8 D~code.r-

IMAR

I II

To ADRS line.s

8

Row SELECTS l 2.

, 4.I

, ,4

..

4-,..i..,

¾

'

... u ¾

~

4-~ /

CE

Lf- ./

CE

Yo

4- 1 · '

l

l

I

-

¾ C.E

,JJ ...

I

Yo

I .

~

CE

CE

CE

-~I

l

l f< ow

Row SELECT 2..

Row SELECT 1

-

SELECT 8

~ddress and R/W lines are similar to l0.3(a) No.

(C)

of chips=

l6k

X

lk

X

8 8

=

16

I :i:

I

MAR

10 bits

4 bits

__A_d_d_r_,es s l in es -4-to_l_6_d_.e._c_od_e_r__l_Ol;

of each chi p.

to select a chip

M

/g

B

,v %

R

¾

•v i

/g

¾

~

1/r0

~

CE

I

I

I

Chip Select 1

Chip Select 2

133

~

•••

CE.

CE

1~

Chip Select 16

9-3

9.7

64k x 8 The probl em is to conv ·e rt 16k x 32 memo ry to each ing divid ly simp by shed RAM. This can be acco mpli Now, long. bits 8 each s, word memo ry word into 4 new of is to be the only thing that has to be taken care is need ed. A that word the lly, idua indiv able to pick simp ly AND-OR gatin g show n will achie ve this.

0-n"!ioo.l

A

S~,t ~ MAR (J~ bits)

Word

D C. I B I'--.-) '--..,-J

I

2{

'----v--- ' ~

9.8

Hexadecimal address 0000

I

I

ROM

4k

4 ROM chips

RAM

56k

56k x 8 = 28 RAM chips 4k x 4

ROM

4k

4 ROM chips

0FFF 1000

EFFF

F000 FFFF

Desig n of address decod e circu itry is simil ar ·to earlie r probl ems.

Addresses are expressed in Hexa decim al form (16 bits = 4 digits). ROM addresses have either O or F as the most signif icant digit. The error circu itry is: Write

Address digit is O or F

Error Where, A O through A ,s-, are the address bits, A O being the most signif icant bit.

134 9-4

9.9 0

l 2 3

1+ • • •

31

MBR

~

bits

5 MAR

f s5 to 32 decoder to select a page

8 to 256 decoder to select a word within a page

135

9-5

(From· the Processor)

9.10

10 bit address

8

2.

bits

2.

2. To 4-

De.c..oder

5 bit~

13 bi:t o..dd:<e ss

To

Ii°'\} Ke. st~.s.

me..moY-~

5

A~)(.i

~f

1

136 9-6

9.11

pc. s T~ ~ i ... } CLK

d

'" "" 0( ...res"t

'--1 E

~ --. ~

S.Ac..~

( l)

(2)

(3) (4)

{ c; • \

_, )

(7)

( 8)

13 address 1 i nes are required.

To tjecode Bk RAM, Controlle r provides 7 address outputs which are des1gned to drive the addresses of the RAM. Outputs(O ut 0 -0ut5) are functions of either the 13-bit address 1nputiAo-A 12) or the refresh counter output='.,.

Write Enable(WE ) 1s connected to the WE of the RAM. There are protected chip select(PC S), memory read/ write request, refresh reque~t and bank select inputs.

CAS(Colum Address Strobe): rh1s output 1s used to latch the column address into the dynamic RAM array RASi(Row Address Strobe): It 1s used to latch the r-ow address 1 nto the bank of dynam 1c RAMs. A refresh osc1llato r(not shown)pro v1des refresh request. Only RAS 1s required for a refresh cycle .

It causes the data to be transferre d to and from the Sense-Ref resh Arnpl1f1er s.

Transfer ac know 1 ed3e and s,.,. s te,n ac know 1 edge outputs are als0 provided.

137 9-7

9.12

Ca)

J..- DATA Register (D)

L -_ _ _ _ _ _ _ _

lt\

'()

MASK __ Re~ister (M) I I

'DATA

[ L.J

~

rlA ,_

HA

I

' I

HA HA

I

I I

rt A ,~

I

I

Memory Array (A)

t=i:;}

L

I

WSR

Response register

SA.me

Circuit ) as for the top Half-

adder

HALF . Adder Array

(R)

(1) Set DATA an~ MASK registers appropriately and issue SEARCH command; the bits of Response register corresponding to a MATCH are set to 1 as a result of the search.

(2) Response b1ts are used as Carry bits into the Half adder array, thereby adding 1 to only responded memory words.

(3) The add1t1on is performed, in a serial fashion at each word, starting from bit n, to the mth bit of the data word, where the field to be incremented is designated by the mth and nth bits.

138 9-8

(b) We can use the DATA register _to store the constant value tb be added. We will need a full adder array.

DATA register

,-..._ __,. Co..lYJ..

ln

I____ I FA

I FA Word Select Register

Response Register

I fA

(1) Response register contents are transferred to Word Select Register, after the search. ( 2 ) Response reg 1 s t e r i s c 1 ear- e d ( used as s tor age for Carry during the serial addition).

(3) A full-adder is activated only 1f the correspondin g Word Select Register bit i s l .

(4) The addition starts with the nth bit and continues through the mth bit.

139

9-9

9.13

.....

0

N

..

-

I Cf\

J.

.I,

~

'

..

•

r

__...-·

~

rl

("t

0

h

~

~

I+--

~

~

~

~

-,

~

~

iE-~

~

~

~~

~

. . . .,

•+,

~

'

l~

0

,~¼ ••• g,_ l'I

....

,_...

-~

m' z. > 0,

r

~

'r 1$"0

Cl'I ~

~

,..,.

l r

0

~

vaI

-~

~

,r

~

I

(

:

-

L

'I

I'

0

..0 .J ~ 1" "" '1I I

'" :

~ -1

ri> ~ ri>o

~

"

-·>t

140

y 9-10

(1} The 3-bit UP/DOWN counter is initialize d to 7(111 in binary) .

(2) If shift-in is on, the decoder is enahled. The decoder determine s into which flip-flop data will be shifted. After this, the counter decrement ed by 1.

(3) If shift-out is on, the whole register shifts one bit position. After shifting, the counter is incremente d.

9.14

,_

3 .

( ,~r~ I~~~ )

f°F rvs\\ (,~if 'fJ~) c.o o~ t! ~

...

•

0

1

,,..

~

•lo

1.

Jr-.

JL ...,, .~L'

'l.

.J

,

•

-. lf- 0

0

0

I

;~

~

0

-

STA~

EMpT'(

0

3

0

'r

0

r-

0

b

a

7

a

-

r--

... ~

T D

141

9-11

9.15

PUSH opera tion SP<- ---- SP+ 1 MBR <---- data MAR< ---- SP Write memor y POP opera tion

MAR< ----- SP Read memor y Outpu t <---- MBR SP,-- - SP - 1 SP --- Stack Point er regis ter is used to hold the addre ss of the top level of the stack .

The stack grows toward highe r addre ss memor y locati ons as items are PUSHed into it.

9.16

M

A

R 1

M

2

n

A

g_ 2

MBR2 .

142

9-12

9.20

cted ; Inte rlea ving Fetc h and Def er sequ ence s are not affe furt her . The LDA ons rati does not help opti miz e thes e ope or cyc les. But exec ute sequ ence requ ires at leas t 3 min , to fetc h the CP in red 2 the Fetc h sequ ence can be ente bloc k is bein g ory mem ent curr le whi tion ruc inst t nex rew ritte n.

REA Dl. (No te: MARl <-- MBR in Fetc h and CP 1 Def er sequ ence s) 2.

READ MAR2 <-- PC, CP 2 l.

ACC <-- MBR CP 3 STA TE< -- F. CP 4 have assu med tha t This wou ld sho rten the Fetc h cyc le; we s betw een the two the inte rlea ving hard war e dist ingu ishe the bloc k in phy sica l bloc ks; (MA Rl, MBRl) refe r to the (MAR2, MBR2) le whic h LDA oper and is fetc hed from whiruc tion is loca ted. inst t nex h whic in k refe r to the bloc Then the inte rThey cou ld both be in the same bloc k. leav ing does not help . h cyc le of the TCA exec utio n cyc le can ove rlap the Fetc nex t inst ruct ion, as in LOA.

143

9-13

9.21

8 Way-Inter leaved Memory

PC

Buffer PC

(a) PC increment s by 1, to fetch the next instructio n in sequence; PC is just a 3-bit counter that counts from o through 7. (b) If PC= 7 then READ. (c) During JUMP instructio n execution : IF IR(ADRS) >MAR+ 7 then MAR<-- IR(ADRS), READ else PC <-- IR(ADRS) - MAR. (d) Assume memory READ/WRITE operation s during DEFER EXECUTE do not use the instructio n buffer. (e) READ operation implies transferin g of 8 consecuti ve memory locations from the address shown in MAR into the buffer. This might need more than one· memory cycle. Assume interleav ing hardware is designed to do such transfers.

9.22

The operation s external to the memory system remain as in problem 8.3. Memory system hardware needs to be changed. Now READ implies 8 memory cycles, trnasferin g 8 words from the location pointed to by MAR into the buffer. This will slow the processor , since i t has to wait until the buffer is filled, to perform the next fetch. To reduce this delay, the buffer can be organized as a queue:

144

9-14

Increm ent by 1

I

{,

MAR

l. . .____

ME_M_O_R_Y_ _ ____.

i

IR (ADRS)

l

Prefetc h/Free ze

Buffer (~Qu_eu_e_)_ ___ ) ....__P_c_ _ : -

I

i

J To IR

Increm ent 1) During JUMP instru ctions : If IR(ADRS) < MAR then Freeze else MAR f - - IR(ADR S), READ. 2) Prefetc h and fetch from Buffer to IR are done simulta neousl y.

9.23

In an n-leve l memory , the hit ratio hi associ ated with the memory mi at level i may be define d as the probability that the inform ation reques ted by the CPU has been assigne d to mi. Assumi ng that all inform ation assigne d to mi also appear s in mi+l' then h 1 < h 2 < •,, < hn = 1.

145

9-15

9.24

Le t T 1 de no te Ca che T 2 de no te MAIN me mo ry T 3 de no te DISK T 4 de no te TAPE

+ (l- h 1 ) (l- h 2 )h 3 T 3 + Ta = h 1 T 1 + (l- hi) h 2 T 2 (1- hi) (l- h 2 ) (l- h 3 )T 4 )*0 .85 *1 00 0n s = 0.8 *1 00 ns + (l- 0.8 o . 8 ) ( 1- o . 8 5 ) * o . 9 * lm s

+ ( 1s + ( 1-O . 8 ) ( 1-0 . 8 5 ) ( 1- O . 9 ) * 5 Om

=4 27 ns.

9.25

ta= (1-p)tm + pt5

9.26

6 4 Kb yte 1-------+- 0

1

819 1 8

by tes

.. .

0

1

511

I Comparato~ - - - - Hit/Miss i

I Ta g(l 3b its )16I by te( 3) j Address(A) (a) Fu lly as so cia tiv e rs ne ed ed : 4x l02 4/8 (1) Th e num ber of com par ato (= 512 ) bi ts 13 ld : 512 x (2) Th e siz e of the tag fie (b) Di rec t rs ne ed ed : 1 (1) Th e num ber of com par ato ld : no nee d to sto re (2) Th e siz e of the tag fiein the cac he . the ad dre sse s of ite ms (c) 4-w ay se t as so cia tiv e par ato rs ne ed ed : 4 (1) Th e num ber of com ld : 4x l28 x6 bi ts (2) Th e siz e of the tag fie

146

9-16

9.27

(a) Fully assoc iativ e Data Area

Tag area (13 bits)

□□□□ □□ □□□

0 RAM

127 128

. .

RAM

255 256 RAM

511 (b)

Direc t Data

~□ 127

Fullt associative Addre ss Tag (13 bits) word (3) 16 Direct T-a-g-(6-)-r-l-B-lo-ck-(-7).......I_B_yt_e-(3----) Addre ss 16

I

1

I

l

.--I

25~ □ 511

tly (c) 4-way set assoc iativ e: The struc ture will be exac N n assig we if book the in 8.9 same as that of Fig value as 128.

9.28

Ta = hTc + (1-h)T m

(h = 0.85)

Ta= 0.85* Tc + 0.15* 10*Tc - - - - - - - with a cache = 2.35T c

147

9-17

with out a cach e = 2.35 Tc/1 0Tc = 0.23 5.

Tm= lOTc Acc ess effi cien cy= Ta/T m

= hTc + (1-h )Tm 500n s Tc= lOO ns, Tm= lOTc = lOOO ns, Ta=

Ta

9.29

500n s = h*lO Ons + (1-h )*lO OOn s = lOOOns - h*90 0ns we have h = 500/ 900 = 5/9. d = 9 bits (q + d) = 17 bits (p + d) = 13 bits ➔ q = 8 bits and p = 4 bits .

4 mem oy.

(1) The re are 2 (=16 ) fram es in the main es. pag (2) The seco ndar y stor age con tain s 256 and each ies (3) The page tabl e con sist s of 246 entr and 1 ber num e entr y is 5 bits long (4-b it fram resi den ce bit) . ct map ping (a) Dire ct map ping : This is call ed dire y for ever y entr an baca use the page tabl e con tain s . age page in this pro cess 's virt ual stor

9.30

q = 8

d

= 9

men t I I Displace I

I Page No.

Page No.

Fram e No.

..

...

0 1

.

..

'-

r

.

15

Vir tual add ress Res iden ce Bit

..

.

l

Rea l add ress p

=4

d

= 9

asso ciat ive (b) Full y asso ciat ive: Eve ry entr y in the page q. It for usly neo ulta stor age is sear ched sim g to page q, ndin espo corr e retu rns pas the page fram real and p· is con cate nate d with d, form ing the add ress , r.

148

9-18

q = 8

d

=9

I Displacement I Virtual Address

Page No.

Associ ative Page Table ,

.

.

•

,

.

.

"

.

•

.

.

.

\

r

l

,v

Real addres s p

9.31

= 4

d = 9

(1) The maximum page table sizes would be as large as second ary memory (i.e. 2q).

(2) The minimum page table sizes would be depend ing on the workin g set.

(3) The number 9f access es needed to search the page table for direct scheme is one and for fully associ ative scheme is 2q.

9.32

Minimum access time= 100 ns.

Maximum access time= 100 + 1000 = 4-100 ns.

9.33

Bank Switch ing

p

R 0 C

E

s s

,. /

+ 3000

Bank

...

3-to-8 Decode r

3

s e 1 ec t

I

-

Data Bus 3-bit Regist er

'

0

R

II 149

Bank

Bank

0

1

.... Ban7 k

1 r-

1~

..,

r 9-19

Base Regist er Base Reg . ✓

3

21-bit Addres s ,

Proces sor

18

150

9-20

9.36 The L1D cache is the first level data cache. It manages all load and store requests from all types through its internal data structures.

The L1D cache: • enables loads and stores to issue speculatively and out of order • ensures that retired loads and stores have the correct data upon retirement • ensures that loads and stores follow the memory ordering rules of the IA32 and Intel 64 instruction set architecture.

The below table lists its components for Intel microarchitecture code named Sandy Bridge and Nehalem.

Component Data Cache Unit (DCU) Load buffers Store buffers Line fill buffers (LFB)

Intel microarchitecture code name Sandy Bridge

Intel microarchitecture code name Nehalem

32KB, 8 ways

32KB, 8 ways

64 entries

48 entries

36 entries

32 entries

10 entries

10 entries

9.37 The distribution of data across multiple drives can be managed either by dedicated computer hardware or by software. When software is used for this purpose, the execution is known as Software-based RAID. Software RAID implementations are now provided by many operating systems.

They can be implemented as: 1.

A layer that abstracts multiple devices, thereby providing a single virtual device (e.g., Linux's md) 2.

A more generic logical volume manager (provided with most server-class operating systems, e.g., Veritas or LVM) 3.

A component of the file system (e.g., ZFS or Btrfs)

9-21

9.38 RAID # RAID 0 RAID 6 RAID 10

Space Available 12 10 6

Space used for protection 0 2 6

9.39 JBOD means “Just a bunch of disks”. It is an array of drives where each of them is accessed directly as an independent drive. SLED on the other hand means “A single, large, expensive drive”, which as the name suggests is single drive with a large capacity.

9-22

Chapter 10 ARITHMETIC/LOGIC UNIT ENHANCEMENT 10.2

We may use Carry-Look-Ahead Adders TTL74182 in the circuit design as

shown below.

.k., 0

v

)(.

+.c:

u

V)

rJ 0-d

:t-

C

u

(Ll">-----

\:I rJ t,a

r-J c,o

bO v')

I

•

LI")

\J1 X.

-+c \.)

0

Q..1">-----.rll

0-

·s n - - - - - n

~

c.:.... r-J ._,. c,.o

-

V)

151

10-1

10 . 3

(a) 24

8

X

Multi plican d regis ter (5 bits) D regis ter (4 bits) R Multi plier

11000 1000

Accum ulator (5 bits) ~

0 1 0 0

l 0 0 0

0 0 0 0 0 0

R

o 0 0 0 0

0 0 0 0 0 0 0 0 0 0

0 Q 0 Q 1 Q 0 1.

initia lize R 0 = O, shift .

R 0 = O, shift .

R 0 = 1, Add D to A and shift A¢ R right

one bit.

0 0 0 1 0 0 0 0

1 1 0 0 0 0 1 1 0 0

(b)

42 X 24 101010 11000

Multi plican d regis ter (6 bits) D regis ter (5 bits) R Multi plier

Accum ulator (6 bits) 0 0 0 0

0 0 ~0 0 0 1 0 1 0

( c) 17

0

1 1 1

X

10001 100000 0

0 0 0 0 1 0 1 1

Four shifts , stop.

Produ ct in A $ R.

0 0 0 0 0 1 1 1

1 1 0 0 0 0 0 0

1 0 0 0

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1

0

0 0 1

R 0 0 Q

1 0 Q 1 1 Q 0 1 1.

0 1 1 0 0 1.

0 0 1 0 0 0

initia lize shift. shift. shift. add and shift.

Ro= o, Ro= o, Ro= o, Ro= 1,

Ri= 1, add and shift.

Five shifts , stop; Produ ct in A Cf R.

64

Multi plican d regis ter (5 bits) D r,egis ter (7 bits) R Multi plier

Accum ulator (5 bits) 0 0 0 0 0 0 ~o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0

R

0 0 0 0 Q 0 0 0 0 Q 1 0 0 0 Q 0 1 0 0 Q 0 0 1 0 Q 0 0 0 1 Q 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

1 0 0 0 0 0 0

0 1 0 0 0 0

152

initia lize shift. shift. shift. shift. shift. shift. add and shift.

Seven shifts , stop; Produ ct in A Cf R.

R 0 =0, R 0 =0, R 0 =0, R 0 =0, R 0 =0, R 0 =0, R 0 =1,

10-2

10.4

(b). 43 /

15

X = 101011 Y = 001111 Q = q5q4q3q2q 1qo 00111 ( -

+

-

+ ( -

+

-

+

-

+

Expand X with 5 zeros Subtract 2 5 y

00000 101011 00111 1 11001 001011) 00110 110101 00111 1 00000 101011 0011 11 11100 111011 00011 000101 0011 11 00000 101011 001 111 11110 110011 00001 001101 001 111 00000 101011 00 1111 11111 101111 00000 010001 00 1111 00000 101011 0 01111 00000 001101 001111 11111 111110 00000 000010 001111 00000 001101

Result is negative, q 5 = o Restore by adding 2 5 y back Subtract 2 4 y Result is negative, q 4 = o Restore by adding 2 4 y back Subtract 2 3 y · Result is negative, q 3 = O Restore by adding 2 3 y back Subtract 2 2 y Result is negative, q 2 = O Restore by adding 2 2 y back Subtract 2 1 y Result is ~ositive, q 1 = 1 Subtract 2 y Result is negative, q 0 = O Restore by adding 2°y back Stop

Remainde r= (001101) Quotient = (000010)

154

10-3

10.4 (a) 24 /

8

X = 11000 Y = 01000

Q = q4q3q 2q1qo 01000

Expan d X with 4 zeros Subtr act 2 4 y

0000 11000 - 0100 0 ( 1100 11000 - 0011 01000 + 0100 0 0000 11000 010 0 ( 1110 11000 - 0001 01000 + 01 000 0000 11000 01 000 ( 1111 11000 - 0000 01000 01 000 + 0000 11000 0 1000 0000 01000 01000 0000 00000

Resu lt is nega tive, 4 q 4 = o.

Resto re by addin g 2 y back Subtr act 2 3 y Resu lt is nega tive, 3 q 3= o Resto re by addin g 2 y Subtr act 2 2 y Resu lt is nega tive, 2 q 2 = 0 Resto re by addin g 2 y

Rema inder = (0000 0) Quot ient = (0001 1)

Subtr act 2 1 y Resu lt is ~osit ive, q 1 = 1 Subtr act 2 y Resu lt is posit ive, q 0 = 1 Stop, after 5 steps .

153

10-4

10.4 (c)

129 /

23

X = 100000 01

y

= 000101 11

Q = q7q6qs q4q3q2 q1qo 000101 11

000000 0 100000 01 - 000101 1 1 ( 111010 1 000000 01 - 000101 0 111111 11 + 000101 1 1 000000 0 100000 01 000101 11 ( 111101 0 .11000 001 - 000010 1 001111 11 + 000101 11 000000 0 100000 01 00010 111 ( 111110 1 101000 01 - 000001 0 010111 11 00010 111 + 000000 0 100000 01 0001 0111 ( 111111 1 000100 01 - 000000 0 111011 11 0001 0111 + 000000 0 100000 01 000 10111 ;( 111111 1 110010 01 - 000000 0 001101 11 000 10111 + 000000 0 100000 01 00 010111 000000 0 001001 01 0 001011 1 ( 111111 1 111101 11 - 000000 0 000010 01 0 001011 1 + 000000 0 001001 01 000101 11 000000 0 000011 10

Expand X with 7 zeros Subtr act 2 7 y Resul t is negat ive, q7=0 Resto re 2 7 y Subtr act 2 6 y Negat ive, q 6 = 0 Resto re 2 6 y Subtr act 2 5 y Negat ive, q 5 = o Resto re 2 5 y Subtr act 2 4 y Negat ive, q 4 = 0 Resto re 2 4 y Subtr act 2 3 y Negat ive, q 3 = 0 Resto re 2 3 y Subtr act 2 2 y Positi ve, ~ 2 = 1 Subtr act 2 y Negat ive, q 1 = 0 Resto re 2 1 y Subtr act 2°y Positi ve, qo= 0 Stop.

Remai nder = (00001 110) Quoti ent = (00000 101)

155

10-5

10.5 (a)

24 /

8

X = 11000 y = 01000 Q = q4q3q 2q1qo

01000

0000 11000 - 0100 0 1100 11000 0011 01000 + 010 00 0001 01000 01 000 + 0000 01000 0 1000 + + 0000 01000 01000 + 0000 00000

-

-

-

Triv ial divid end Subt ract 2 4y Nega tive resu lt, q4= 0 Add 2 3 y Nega tive resu lt, q3= 0 Add 2 2 y Nega tive resu lt, q2= 0 Add 2 1 y

Posit ive resu lt, q1= 1 Subtr act 20y Posit ive resu lt, qo= 1

Quot ient = (0001 1) Rema inder = (0000 0) (b)

43 /

15

10101 1 = 00111 1

X =

y

Q =

q5q4q 3q2q1 qo

00111 1

00000 10101 1 - 00111 1 - 00110 11010 1 + 0011 11 - 00011 00010 1 001 111 + - 00001 00110 1 00 1111 + - 00000 01000 1 0 01111 + + 00000 00110 1 00111 1 - 00000 00001 0 00111 1 + + 00000 00110 1

Expan d X with 5 zeros Subtr act 2 5 y Nega tive, q5= 0 Add 2 4 y Nega tive, q4= 0 Add 2 3 y Nega tive, q3= 0 Add 2 2 y Nega tive, q2= 0 Add 2 1 y

Posit ive, 'J-i= l Subtr act 2 y Nega tive, q 0= 0 Corre ct the remai nder

Quot ient = (0000 10) Rema inder = (0011 01)

156

10-6

10.5 (c)

129 /

23

X = 10000001

Y = 00010111

Q = q;q6qsq4q3q2q1qo

00010111

0000000 10000001 - 0001011 1 - 0001010 11111111 + 000101 11 - 0000101 00111111 00010 111 + - 0000010 01011111 0001 0111 + - 0000000 11101111 000 10111 + - 0000000 00110111 00 010111 + + 0000000 00100101 0 0010111 - 0000000 00001001 00010111 + + 0000000 00001110

Trivial dividend Subtract 2 7 y Negative, q 7= o 6

Add 2 y

Negative, q 6 = o Add 2 5 y Negative, q 5 = o

Add 2 4 y

Negative, q 4 = o

Add 2 3 y

Negative, q 3 = o

Add 2 2 y

Positive, ~ 2 = 1 Subtract 2 y Negative, q 1 = O Add 2°y Positive, q 0 = 1

Quotient = (00000101) Remainder= (00001110) 10.6 We are assuming this is a hardwired-based stack.

SHR:

POP SHR (X)

PUSH Note: Here we assume that Z will be latched to the Input Register automatically.

COMP:

POP Twos complement signal for FU PUSH

SUB:

POP Twos complement signal for FU PUSH POP ALU-ADD (Addition signal for FU) POP PUSH

157

10-7

10.7

ALU-ADD ALU-SUB

I

I

~

{,

X

Z

ALU

y

ARITH TYPE REAL/INT

To EAL

To INT

TAG

1'

1'

I

I

p

Q

X

y

TAG

STACK INPUT

TAG

z

Data lines Control lines

p

ARITH TYPE Q

(a) Each conversion block is assumed to have an activate control signal. If the block is not activated, the output of the block is zero. (b) Control signals needed: PUSH push the stack, TL f- INPUT POP XE- TL, pop the stack ADD POP ALU-ADD PUSH SUB POP ALU-SUB PUSH

158

10-8

Excess 3

10.8

Excess 3

0110 + 0111 1101 Correction+ 0011 + 7 1010 3

3

+ 4

+ 7

0110 + 1010 1 0000 + 0011 1 0011

Correction

Carry

Add 3 i.e.+ 0 0 1 1 Subtract 3 i.e.+ 1 1 o 1 (Twos comp. of 3 ) Note that C0 = 1 C 1 = carry -C2 = c 3 .= Carry 1

0

The circuit is identical to that in Figure 10.9 except for the following correction circuitry: S3

S2

I -l,

rl I H

1I

S0

S1

o(}

i

1 ,1,

lr

H I I

FA

FA

-l,

,1,

...

{,

S3

S2

S1

So

Neglect

I

FA

159

~(Not corrected)

iarry

HA

f-

Corrected

10-9

1069 e

= exponent, m = mantissa. ·shift right mB e8

~

e 8 +1

IDAt---------------➔

Set R 1 flag I

,I

SUM~

mp_ + ma

Add mantissa

I

~

Set R2 flag/

1 Bit B Yes Shift SUM right eA ~ ep_ + 1

No Shift SUM left eA ~ ea + 1

2p Normalize

(Error conditions are neglected) output

mantissa= SUM ( exponent= eA+127

1'

(The MSB(i.e.B=l) discarded)

eA' and e B' are the exponents in IEEE representation. mA' and m B' are the mantissa in IEEE representation.

e.A = eA' -127, eB = e.B' -127. "'A= 1 ~ mA•, ms= 1 ¢ mg~

160

10-10

10.10 Stage 1: Since two numbers are represented in the

IEEE standard form, the exponents and mantissas have to be adjusted as follows: exponent= exponent - 127 mantissa= 1 ¢ mantissa. stage 2: Multiply the two mantissas to form a doublelength mantissa and add the two exponents. the product mantissa, and if it is Examine Stage 3: not normalized, normalize it and adjust the exponent accordingly. the product mantissa to a singleRound stage 4: length mantissa, and if the rounding should cause the mantissa to overflow, adjust the exponent.

10.11 The scheme diagram will be exactly same as that of problem 7.4, except that the levels of the stack

must be changed to be n.

10.12

PUSH

IUpper bound register

An-1-Ao

!

I OVERFLOW

Comparatorr----A < B

SP

n

Lower bound register l

UNDERFLOW

)

Comparato~ A < B

POP

161

10-11

10.13

Total computation time = (6 + (50 - 1))*15 ns =

10 .14

Total computation time = (M + (N - 1)) T

10.15

825 ns

faster than a serial In general, an n-stage pipeline is never n times are ignored and the machine. However, if the staging register delays ignore the pipeline fill number of tasks processed N is large enough to n in the following time, then -stag e pipeline is n times faster as show speedup equation:

NxTseq

----=n

(n+ N-l) T

162

10-12

10.16

The basic change for the 430X architecture was to introduce a 20-bit address range to allow addressing outside the 64K available on the original 430 devices. There are a new set of instructions that operate on the 20-bit address in parallel with the old style 16-bit instructions. e.g.  CALL ; takes a 16-bit address  CALLA ; takes a 20-bit address  PUSH ; Push the bottom 16 bits of a register onto the stack  PUSHA ; Push the full 20-bit register The existing code compiled for a 430 based processor will run within the bottom 64K address space of the 430X processor. In the development tools such as IAR you can specify a memory model so that the longer function calls and other 430X specific instructions are not generated if you ensure that your code does not cross the 64K boundary.

10.17

Available performance improvement from superscalar techniques is limited by three key areas: - Limited amount of instruction-level parallelism.

- The complexity and time cost of the dispatcher and associated dependency checking logic.

- The branch instruction processing.

Chapter 11 CONTROL UNIT ENHANCEMENT

11.3

Microinstruction sequence for LDA is changed as follows: Fetch

MAR~ PC, READ. PC ~PC+ 1.

IR ~ MBR, If IR 1 5 = 0 then MAR f - - IR 7 _ 0 + INDEX else MAR f - - IR 7 _ 0 , If IR 10 = 1 then READ. STATE f - - E.

Execute CP 1

If IR 10 READ. WAIT.

= 1 then MAR~ MBR.

ACC

MBR. F.

~

STATE

~

The change needed to the bus structure is to link the MBR directly to the IR. Also the control signals for I R ~ MBR have to be changed. In other words, we issue the indirect addressing operation with the I R ~ MBR operation simultaneously in the Fetch cycle, thereby eliminating the Defer cycle.

163

11-1

11.4

Fetch

M

PC, REltD ~ PC E-- PC+ 1.

IR E-- MBR. MARE-- IR1-o + INDEX If IR 10 = 0 then GO TO M READ WAIT MARE-- MBR READ WAIT ACC E-- MBR GO TO FETCH

MAR E--

GFetch begins .Index if needed .Indirec t address ing .Execute .End of LDA

The microin structio n format would remain unchang ed.

11.5

Assumpt ion : We cannot alter the bus structur e. (a) Equal length major cycles only The optimum length for the major cycle would be five minor cycles, then ASC needs two major cycles for each instruc tion.

We derive the microop eration sequence s as follows : PC, READ. PC+ 1.

IR E-- MBR. If IR 1 s = 0 then MARE-- IR 7 _ 0 + INDEX else MAR E-- IR 7 _ 0 • If IR 10 = 1 then READ. STATE E-- E.

MARE-PC E--

Fetch

CP 5

STA

LDA

Execute CP 1

If IR 10 = l then

CP 2 CP 3

READ WAIT ACC E-- MBR

CP 4 CP 5

STATE

MAR E-- MBR.,.

E--

F.

STATE

E--

F.

ADD

TCA

Execute

MBR E-- ACC .

WRITE.

CP 1

ACC

E--

ACC'

CP 2 CP 3 CP 4 CP 5

ACC

E--

ACC + 1

STATE

E--

F

164

If IR 10 = 1 then MARE-- MBR. READ. WAIT ACC E-- MBR + ACC. STATE E-- F

11-2

(b)

11.6

Major cycle s can be of varyi ng lengt h.

5 mino r cycle s Fetch cycle Execu te cycle 4 mino r cycle s LDA 3 mino r cycle s STA 3 mino r cycle s TCA 4 mino r cycle s ADD The major cycle can vary from 3 minor cycle s to 5 minor cycle s.

LDA

DEFER

.

MAR ~

.Inde x if neede d IR 7 _ 0 + INDEX = 1 then CALL DEFER .Exec ute

If IR 10 READ WAIT ACC ~ MBR Go to FETCH READ WAIT MAR ~ MBR RETURN

(a) The extra time neede d to save and resto re the retur n addre ss has to be added to the execu tion time of LDA. (b) We do not need extra time for savin g and resto ring the retur n addre ss.

11.7

( a) We will need three concu rrent contr ol seque nces le: (sign als or micr oinst ructi ons) one for each modu

I ... -}I

~

Fetch

Execu te contr ol signa ls

Defe r contr ol signa ls

Fetch contr ol signa ls

I

HIH

~

... I

I

i

~

Defer

165

I

... i

~~I Execu te

11-3

(b) All ASC registe rs are access ible by the three module s. (c) All microo peratio ns remain as in Tables 5.1 throug h 5.3 in chapte r 5. (d) Fetch module sets three flags: Defer (D), if indire ct cycle is needed .

Execut e (E), if Execut e cycle is needed .

Ready (R), indica ting the comple tion of Fetch.

Defer module perform s indire ct operat ion, if D=l, otherw ise idles; and transf ers E to Execut e module and signif ies the comple tion with R. Execut e.modu le perform s Execut e cycle based on E and the opcode . (e) Each of the module s access the memory ; the memory access confli ct must be resolve d in favor of Execut e module , followe d by Defer module and·th en Fetch module . (f) If the three module s are assume d to work synchr onously, (blocks of 4 clock pulses ), the R flag is not needed . If an asynch ronous operat ion is assume d, Defer and Execut e module s start a new cycle when the R flag is ON and they comple te the curren t cyc1e. R flag must be reset by them when the new cycle starts. Fetch and Defer module s can not set the R, D, and E flags unless R flag is o.

11.8

(a) In MCU we need two concur rent contro l sequen ces, one for Fetch and the other Execut e. (b) The other change s will be simila r to those made in HCU. (3) CROM should provid e for simulta neous access and high through put by multip ort, interle aving, and bankin g scheme s.

11.9

Jump addres s

Test

Instru ction

l

FIELD I

I

•OFF Bus 1, Bus 21Bus

ON

I I

ON

I

I

I

3

3

3

i

I

1

ALU I I

3:

i

I

I

1 ,2

I

I

I

I

3

2

2

166

MEMORY Condit ion Al.addr ess Code

;

i

I

3

I

I

i

2

2

3

7

11-4

11.10

d for the mic roWe hav e to enc ode eac h sub fiel blem 9.9 , the n form the pro in form at use d ins tru ctio n s: mic roi nst ruc tion form at as foll ow

I

I

'f

t

Con trol Sig nal s por tion rep Eac h bit in the mic roi nst ruc tion con tro l sig nal .

11.16

res ent s a

s faster than a serial In general, an n-stage pipeline is never n time ys are ignored and the machine. However, if the staging register dela to ignore the pipeline fill number of tasks processed N is large enough n in the following show as r time, the n-stage pipeline is n times faste speedup equation:

NxTseq (n+ N-l )T

-----=n

11.17

, we will need four stages to Since each stage can add two 2-bit numbers tes the two least significant add 8-bit integers. The first stage accumula The second stage bits and produces a 2-bit sum and a carry bit. with the carry from the first g accumulates the next two significant bits alon complete sum is produced. stage and so on until the last stage where the Reservation Table:

Sta Sta

167

11-5

11.18

s: The pipeline consists of the following stages and timing characteristic Operation Add Exponents Multiply Mantissas

Normalize Round Renormalize

Time T 2T T/2 (Assuming any number of shifts can be performed in time T/2) T/2 (Assumed) T/2

stage Since the last three stages operate at T/2, it is ideal to split the first Similarly, into two stages, each consuming T/2 and creating a partial sum. ing a produc each stages four into the second stage can be partitioned of time cycle a and stages partial product. Thus, the pipeline will have 9 T/2.

The normalized stages assume that any number of shifts can be d performed in T/2. In practice, this is not the case. The time require data. the on ds depen which d neede depends on the number of shifts 11.19

through The set of 50 numbers need to be multiplied as pairs sending then the pipeline. d a. The first 18 numbers can be inserted into the pipeline as 9 operan th pairs. At the 9 cycle, the first product of two numbers would be a ready. This is often forwarded to the first stage, to be inserted with new number as the second operand. r to be multiplied with a b. This mode of operation allows a new numbe th ing partial product, at each cycle after the 9 cycle. Thus, the remain (50 - 18 = 32) numbers require 32 cycles. At the end of these 32 cycles, we will have 9 partial products. pairs, c. These partial products are sent into pipelines as 5 operand requiring 9 + 4 cycles to create 5 products. pairs, d. These partial products are sent into pipelines as 3 operand ts. requiring 9 + 3 cycles to create 3 produc pairs, e. These partial products are sent into pipelines as 2 operand requiring 9 + 2 cycles to create 2 products. f.

These partial products are sent into pipelines as 1 operand pair, requiring 9 cycles to create 5 products.

The total is 9 + 32 + 13 + 12 + 11 + 9 = 86 cycles

168

11-6

11.21 Following are the components along with their functions:     



Instruction Cache: 32-Kbyte backing store of instruction bytes.

Legacy Decode Pipeline: Decodes instructions to micro-ops, delivered to the micro-op queue and Decoded ICache.

Decoded ICache: Provides stream of micro-ops to the micro-op queue.

MSROM: Complex instruction micro-op flow store, accessible from both Legacy Decode Pipeline and Decoded ICache.

Branch Prediction Unit (BPU): Determines next block of code to be executed and drive lookup of Decoded ICache and legacy decode pipelines.

Mirco-op queue: Queues micro-ops from the Decoded ICache and the legacy decode pipeline.

11.22. The performance improvement in superscalar techniques is limited by three key areas: 1. The degree of parallelism in the instruction stream: In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one instruction impacts either resources or results of the other.

2. The degree of complexity and time cost of the dispatcher and associated dependency checking logic: When the number of simultaneously issued instructions increases, the cost of dependency checking increases extremely rapidly. This is the case even when instruction stream contains no inter-instruction dependencies; superscalar CPU must check for that possibility.

3. The branch instruction processing: When the number of simultaneously issued instructions increases, the cost of branch checking increases extremely rapidly.

11.23 The main motivation for using branch prediction schemes is to increase the flow in the instruction pipeline. By this they play a critical role in the increase of the effective performance of the modern day pipelined-microprocessor such as x86.

Stall pipeline: This scheme handles branches by freezing or flushing. It holds or deletes any instruction after the branch until the branch destination is known.

Main feature: it is simple for both software and hardware implementations.

Predict taken: This works with the principle of feed forward mechanism. In this scheme a branch is predicted as not taken and let the hardware to take that

11-7

branch. Only after the full outcome of the branch is known the machine state is changed.

Main feature: The need to know when the machine state might be changed by an instruction and how to back out brings in the complexity. But it performs much better and is only slightly more complex than the Stall-pipeline.

Predict not taken: As a logical alternative to the previous method, as soon as the branch is decoded and the target address is computed, we assume the branch to be taken and begin fetching and executing at the target address.

Main feature: In some machines where the target address is known before the branch outcome a predict-taken scheme might be useful.

Delayed branch: In delayed branch scheme the execution cycle with a branch delay of length n is concatenation of each of the sequential successors.

Sequential successors are in the branch-delay slots. These instructions are executed whether or not the branch is taken. Compilers make the successor instructions valid and useful with three scheduling schemes: from before branch, from target and from fall through.

Though it is quite effective, there are limitations due to the restrictions on the instructions that are scheduled into delay slots and our ability to predict at compile time whether a branch will be chosen are not for execution.

11.24 The steps for the 5 stage MIPS are 1. Send PC to memory and branch-target buffer 2. Check - Entry found in branch-target buffer and if yes /no branch.

3. If NO, check - Has instruction a taken branch? If yes/no branch; If NO , then carry on with Normal instruction execution. If YES, - send out predicted PC. Then check Taken branch? If yes/no branch 4. With the NO from step 2, and yes in step 3, Enter branch instruction address and next PC into branch-target buffer.

With yes in step 2, and NO in step-3, Mis-predicted branch, kill fetched instruction; restart fetch at other target; delete entry from target buffer.

With Yes in step 2 and Yes in step-3 Branch correctly predicted; continue execution with no stalls.

The Yes in stage 2 leads to 5 stages to result in correct branch prediction.

11-8

Chapter 12 CONTROL UNIT ENHANCEMENT

12.1

The case of (N x N) matrices are usually simpler compared to non-square matrix solutions. Since N PEs are assumed in SIMD, in general either a row or a column is assigned to a PE.

12.2

The solutions now require that the (N x N) matrices are partitioned such that the partitions contain either M rows or M columns. The solutions from the above problem are applied to each of these partitions. Since there will be N/M + 1 partitions (with the last partition containing less than M rows or columns), there will be N/M iterations.

For instance, if N is 10 and M is 3, for a column sum computation, there will be 4 partitions with the last partition containing only 1 column. The result can be viewed as a (40 x 3) matrix, with the last 10 rows containing only the first column element. Then the column sun procedure is: sum(i) = 0 (1 < i < 3); k = 3; for j = 1 to 40 if U>= 30) k =1; sum(i) = sum(i) + AU,i) (1 < i < 3) endfor

12.3

12.4

a) Assuming no torus or diagonal connections, the nodes farthest apart are at opposite corners. From the corner to its horizontal opposites, 63 steps are required. From there to the vertical opposite, 63 steps are required, resulting a total of 126 steps (i.e. 2(N-1)). b) The farthest the distance between any two nodes in a hypercube is the dimension of the cube. Since a 4096 node cube has a dimension of 12, the maximum number of hops is 12 or log2N. A binary n-cube is a special case of a k-ary n-cube, which has n dimensions with k nodes per dimension or kn nodes. For a binary cube, k = 2 and hence it has 2n nodes.

A two dimensional torus is also a special case of a k-ary n-cube, where n is always 2 dimensions and k is the size of each dimension. A torus or k-ary 2 2-cube has k nodes. The binary cube is a superset of meshes. Given the number of nodes, there is the same number or more direct connections between nodes to simulate nearest neighbor connections of mesh and torus.

Assume that the 16 nodes of a 4 x 4 torus are cumbered from O through 15, starting at the top left corner, proceeding row by row, ending at the bottom right corner. When the nodes of this torus are embedded in a 16 node hypercube, the node numbering would be:

169

12-1

Node Number

Hypercube Node

0

0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000

2 3 4 5 6 7 8 9 10 11 12 13 14 15

In general, for this equivalent to hold, the number of nodes must be the same in both cases. That is, n x n = kn.

12.5

Some of the major characteristics are: • Detection of loops and the dependencies among the operations within the loops so that the iterations can be spread over the processors in the SIMD. • Rearranging the program flow at conditional branch statements, so that computations for the conditions are handled appropriately.

• Recognition of array-oriented data structures and the translation of corresponding operations into SIMD mode.

12.8

MEMORY: The memory elements themselves could be standard RAM devices with appropriate addressing and data 1/0 capability. In order to enhance the speed of access and reduce contention, capability to access each physical block independently would be ideal. Using multiport memory blocks would ease the design of interconnection network and reduce memory contention problems.

PROCESSOR: The processing element should have the control unit, arithmetic logic unit and 1/0 capabilities at the minimum. A flexible addressing mode (such as paged addressing, or base register/ offset addressing) is essential. In order to implement mutual exclusion, at least a test-and-set instruction in the instruction set would be needed.

In addition to the above minimum characteristics, capability to interface to standard busses and interconnection networks is needed.

170

12-2

12.9

The crossbar interconnection offers two main advantages • Up to four memory references can be in progress at once, and each processor's memory space can be increased from 64k8 to 256k8.

The path between the processor and memory has a delay only at the a cross point, so each processor is only one cross point delay from any memory. Up to four simultaneous accesses can be done provided that no two accesses involve the same memory or processor. If two processor attempt to access the same memory in the same cycle, one of the processors must wait for the other to complete.

A possible solution to reducing contention is to allocate the data so that accesses tend to be more evenly distributed across all memories rather than clustered in a single memory. This interleaving can be achieved by allocating blocks of data so that successive elements lie in successive modules. Also, shared program code can be allocated such that sequentially increasing addresses lie in successive modules. Under this scheme, when shared data or code is accessed by two processors simultaneously, the contention will delay one processor. Thereafter, the second processor will trail the first processor without conflict as long as the two processors continue to access memories sequentially.

The address fields can be laid out to distribute data and code across the four memory modules. The lower bits indicate which of the four modules is to be accessed, while the upper bits indicate the offset within that module.

12.11

Assumption: the phrase "An algorithm requires access to each row of an N x N matrix" implies that the calculation is row independent, i.e. the result i depends (at least primarily) on the elements in row i of the matrix, not the other rows. This is to distinguish from the case where every result depends on every row. Thus it is possible to parallelize this task by assigning each of the N rows of the matrix to a separate processor. a) N x N crossbar: Each row of the matrix is assigned to a separate memory bank. Once the initial crossbar configuration is established, it does not need to change. b) Bus: assuming each processor has local cache sufficient to hold a matrix row (or a substantial portion) and supports clock transfers, then row per bank storage is desirable. Each processor can fetch a row as a block at the beginning of processing and process entirely from cache there on. This reduces overall bus contention during the run and block transfer should result in lower overhead compared to a succession of word size references.

The above assumptions are not unreasonable considering the performance expectations for massively parallel systems.

171

12-3

12.12

Assumption: At any given phase of the execution accesses to a specific row I from a given processor P implies that P will also access a specific column J. That is to say the throughout the execution of the algorithm, a sequence of row-column associations will be established, where a given row element calculation is applied to an entire column. a) Crossbar: Column per bank storage is most efficient if processor P is assigned to row I as the processor will iterate down the column J once for each element of I (as assumed above). Given this, column-wise storage crossbar switching will yield the best result. b) Bus: Given the assumptions above and from the previous problem, the column per bank storage is most appropriate, for the same access efficiency reasons given in the previous problem. It will maximize cache effectiveness.

172

12-4

12.16

On the Pentium 4, a malicious thread can use a timing attack to monitor the memory access patterns of another thread with which it shares a cache, allowing the theft of cryptographic information according to Colin Percival in a research paper “CACHE MISSING FOR FUN AND PROFIT” in 2005. Potential solutions to this include the processor changing its cache eviction strategy, or the operating system preventing the simultaneous execution, on the same physical core, of threads with different privileges.

12.17

Most compilers don't generate SIMD instructions from a typical C program. Vectorization in compilers is an active area of computer science research so; implementing an algorithm with SIMD instructions usually requires human labor. Not all algorithms can be vectorized. For example, a flow-control-heavy task like code parsing would not benefit from SIMD.

12.18

Each Cray XK7 compute node has an AMD Opteron 6200 Series processor with four channels of DDR3 memory and an NVIDIA Tesla K20 GPU Computing Accelerator with 6GB of GDDR5 memory. Each blade is composed of four compute nodes for high scalability with up to 64 AMD processor cores per blade. The performance of the XK7 is performance of 17.59 petaflops (quadrillion of calculations per second, or Pflops). Each Blue Gene/L Compute or I/O node was a single ASIC with associated DRAM memory chips. The ASIC integrated two 700 MHz PowerPC 440 embedded processors, each with a double-pipeline-double-precision Floating Point Unit (FPU), a cache sub-system with built-in DRAM controller and the logic to support multiple communication sub-systems.

The dual FPUs gave each Blue Gene/L node a theoretical peak performance of 5.6 GFLOPS (gigaFLOPS). The two CPUs were not cache coherent with one another. The performance of the IBM Blue Gene/Q is 16.324.8 PFlop/s.

12-5

Chapter 13 EMBEDDED SYSTEMS 13.1

Microcontroller hardware requirements: The microcontroller needs to sense that there is a car at the intersection; so it needs either a camera or a sensor on the road.

Software Architecture: The simplest software architecture would be a loop providing red-yellow-green signals and change the cycle only when the car appears at one of the roads.

13.8

The fetch-and-add primitive provides an important capability in that, unlike other primitives, it can produce multiple "go aheads" for attempted simultaneous accesses each with different number. The fetch-and-add operation can itself be parallelized with appropriate supporting hardware.

The extension of fetch-and-add to generalize fetch-and-op, which can be done for any associative binary operator, yields the following important advantage: While the majority of the synchronization primitives (barrier semaphores, test and set) are intended to provide controlled access to shared data by manipulation code that is separate from the primitive used for access, a general fetch-and-op provides the ability to support fine grained highly parallel atomic access to shared data element but to perform an operation on this data. The ability not to only access a shared data element but to perform an operation on it in a guaranteed atomic fashion makes fetchand-op an extremely powerful tool for parallel computation.

13.9

i = 1 to N Z[i] = A[i] * b[i] + C[i] * d[i] forks 1 process per index, which computes program The following parallel the value of Z for that index.

For i = 1 to N-1 Fork sum 1 i=N sum_ 1: Z[i] = A[i] * b[i] + C[i] * d[i] join N print results end

13.10 Computation time estimates: Fork (N-1) processes: 10 (N-1) Join N processes: 4N Each process performs 1* 1=1 1 addition: 2 * 3 =6 2 multiplications: 1* 1= 1 1 assignment (the execution time for the assignment operation is not given in the problem so it is assumed to be 1 here!)

173

13-1

The execution time for each process = 1 + 6 + 1 = 8 The time required fork the processes = 10 (N-1) The time for N joins = 4N The approximate time to complete the program = 10 (N-1) + 8 + 4N The above calculations assume N processors. If M processors are available where M < N, then the program estimated time will be approximately: 10 (N-1) + 8 * N / M+ 4N.

174

13-2

13.11 32-bit ARM Instruction Set and 16-bit Thumb Instruction Set are the two instruction set most ARM processors implement and they differ in how the instructions are encoded. The ARM and Thumb instruction sets can interwork freely, i.e. different procedures can be compiled or assembled to different instruction sets, and still be able to call each other efficiently.

Thumb instructions are either 16-bit or 32-bit and can be intermixed freely.

They are aligned on a two byte boundary and many common operations are most efficiently executed using 16-bit instructions. Many operations that would require two or more 16-bit instructions can be more efficiently executed with a single 32-bit instruction. Most 16-bit bit instructions can only access eight of the general-purpose registers, R0-R7 and these are known as low registers. A small number of 16-bit instructions can access the high registers, R8-R15.

ARM instructions are always 32-bit, and are aligned on a four byte boundary.

13.12 Unified Assembler Language (UAL) is an assembly language syntax that provides a canonical form for all ARM and Thumb instructions. It describes the syntax for the mnemonic and the operands of each instruction and includes instruction selection rules that specify which instruction encoding is selected when more than one can provide the required functionality. For example, both 16-bit and 32-bit encodings exist for an ADD R0, R1, R2 instruction. The most common instruction selection rule is that when both a 16-bit encoding and a 32-bit encoding are available, the 16-bit encoding is selected, to optimize code density.

13.13 IDE (Eclipse IDE), Compiler Suite (GCC Compiler for ARM), Debugger (GNU Debugger), Simulator (Insight Debugger), JTAG Debugging probe (Hardware), Development Board (Hardware) are some of the ARM development tools. Both proprietary and Open Source tools are available in market, and some proprietary tools include IAR Workbench for ARM, Keil for ARM, Sourcery G++, Green hill Tools for ARM, Windriver, Embest IDE for ARM, CrossWorks for ARM, etc.

13-3

Chapter 14 MOBILE PROCESSORS AND SYSTEM ON CHIP

14.1. Implementation size, performance, and very low power consumption.

14.2. Microsoft surface, Apple iPad, Apple iPhone, iPod, Cannon Power Shot A470 digital camera, etc.

14.3. The recently released ARMv7 architecture design is divided into three profiles: ARMv7-A Application profile, implements a traditional ARM architecture with multiple modes and supporting a Virtual Memory System Architecture (VSMA) based on MMU. Supports the ARM and Thumb instruction sets.

ARMv7-R Real-time profile, implements a traditional ARM architecture with multiple modes and supporting a Protected Memory System Architecture (PMSA) based on an MPU. Supports the ARM and Thumb instruction sets.

ARMv7-M Microcontroller profile, implements a programmers’ model designed for fast interrupt processing, with hardware stacking of registers and support for writing interrupt handlers in high level languages.

14.4. Instruction fetch, Instruction decode, Instruction execute, Load/Store, L2 Cache, NEON, and Embedded Trace Macrocell (ETM).

14.5.

Cortex-A8, A9 and A15 processors.

Cortex-A8 ---- Intel Atom N330 Cortex-A9 ---- Intel Atom N270 Cortex-A15--- Intel i7 960 14.6.

Cortex A9 Number of Cores Frequency Power Consumption

2 (4 max) 800Mhz (Po) 2 Ghz (Per) 0.5 W (Po) 1.9 W (Per)

Atom N270 2 (4 max) 8 HT threads 1.6 Ghz 2.5W (TDP)

14-1

14.7. In ARMv7, a processor in ARM state can enter Thumb state and change to executing Thumb instructions by executing an ADC, ADD, AND, ASR, BIC, EOR, LSL, LSR, MOV, MVN, ORR, ROR, RX, RSB, RSC, SBC, or SUB instruction that has the PC as destination register and does not set the condition flags.

14.8.

User ------------------ used for executing most application programs FIQ ------------------- used for handling fast interrupts IRQ ------------------- used for general purpose interrupt handling Supervisor ----------- a protected mode for the Operating System Undefined ----------- entered upon Undefined Instruction exceptions Abort ----------------- entered after Data or Pre-fetch Aborts System --------------- privileged user mode for the Operating System Monitor -------------- a secure mode for TrustZone

14.9. The processor has three major clock domains: CLK - High speed core clock used to clock all major processor interfaces.

The Cortex-A8 processor uses only the rising edge of CLK. CLK controls the following units within the processor: • instruction fetch unit • instruction decode unit • instruction execute unit • load/store unit • L2 cache unit, including AXI interface • NEON unit • ETM unit, not including the ATB interface • debug logic, not including the APB interface PCLK - APB clock that controls the debug interface for the processor.

PCLK is asynchronous to CLK and ATCLK. PCLK controls the debug interface and logic in the PCLK domain.

ATCLK - ATB clock that controls the ATB interface for the processor.

ATCLK is asynchronous to CLK and PCLK. ATCLK controls the ATB interface.

14.10. SoCs can be found in cars, Medical Devices, home use electronic devices like TVs, Stereos, and cooling systems. The purpose of SoC in industry will be to identify the potential of low power SoC technology.

Bluetooth chips in modern vehicles are originally SoCs with a processing facility, a memory, Input/output interfaces, and other components as mention in chapter text. Similarly, SoC’s are located in seven potential areas for SoC technology in the automotive industry such as braking, transmission, airbag, vehicle Stability, driver information and in-car entertainment

14-2

14.11. SoC is a whole system with multiple components packaged in a single chip. SiP is multiple chips enclosed in a single module to achieve a single functionality. The feature of having fewer packages in the system made assembly costs of a SoC become less but there is no possibility to upgrade any component like (Memory, Processor, GPU) in SoC. The only way is to replace that SoC with a newer SoC that is more powerful. In SiP upgrading a component is easier by simply replacing a chip in the package with a more powerful chip. SoC are famous of their small size, low power and comparatively high performance. All these characteristics encouraged researchers and industry to invest more time and money in making SoC chips more efficient and smaller in size so that they can be integrated in any real-world application.

14.12. Yes, Intel Tolapai is the code name of Intel's system-on-a-chip (SoC) embedded processor which combines an x86 processor core, DDR2 memory controllers and I/O controllers, and a QuickAssist Integrated Accelerator unit for security functions. Systems on chip are multiple components packaged in a single chip however; ARM architecture is itself processing unit architecture that was integrated in many famous devices like iPhone. The Apple A4 that came in iPhone 4 is a system-on-a-chip (SoC) designed by Apple Inc. and manufactured

by Samsung. It combines an ARM Cortex-A8 CPU with a PowerVR GPU and a 512 MB RAM. 14.13. The multiprocessor System-on-Chip (MPSoC) is a system-on-achip (SoC) which uses multiple processors, usually targeted for embedded applications. It is used by platforms that contain multiple, usually heterogeneous, processing elements with specific functionalities reflecting the need of the expected application domain, a memory hierarchy and I/O components.

A chip scale package (CSP) is a type of integrated circuit chip carrier. The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer-level chip-scale package (WL-CSP) or a wafer-level package (WLP).

Wafer-level chip-scale package (WL-CSP) is a type of chip-scale package (CSP), which enables the IC to be attached face down to the printed circuit board (PCB) using conventional SMT assembly methods. The chip's pads connect directly to the PCB pads through individual solder balls. WLP technology differs from other ball grid array, leaded, and laminate-based chip scale packages (CSPs) because no bond wires or interposer connections are required.

14-3

14 Chapter 15 COMPUTER NETWORKS AND DISTRIBUTED PROCESSING

15.3 14.3

A router takes information arriving on one of its incoming communication links and forwards it through one of its outgoing communication links.

A bridge reduces the amount of traffic on a network by dividing data into segments.

14.4 15.4

The transmission rate of the satellite communication channels is slow because of the long signal propagation delay. This limits the use of realtime applications on the network.

15.5 14.5

DNS allows nodes on the internet to be assigned both an IP address and one or more corresponding names, called domain names.

To avoid addressing conflicts, the network numbers have been assigned by the lnterNIC (formerly known simply as Network Interface Card NIC).

15.8 14.8

Making a central system secure is not hard when simple security standards are followed such as using known authorization/authentication techniques, and protecting the centralized database in secure locations.

Constructing secure distributed systems, on the other hand, is not that easy. The resources are distributed over several databases, many of them may not be locked up in secure locations and most of the communication goes over insecure data links especially in large systems.

Furthermore, it is hard to ensure that a resource found "somewhere on the net" is trust worthy.

14.9 15.9

Firewall is a security mechanism that filters data before it reaches the machine connected to it.

175

15-1

15.11

Google Apps Engine is a platform as a service (PaaS) cloud computing platform for developing and hosting web applications in Google-managed data centers. Google Apps Engine does not provide the IaaS, or SaaS. IBM smart cloud and Oracle cloud both provide IaaS, PaaS, and SaaS. IBM smart Cloud, Oracle Cloud and Google Apps Engine can be deployed as a public, private, community, and or hybrid cloud.

15.12

Scalability in the cloud refers to the feature of being able to obtain more application servers, web servers, and data servers as requested by a cloud service consumer. Multi-Tenancy refers to a single instance of the software runs on a server, serving multiple client organizations (tenants). Multi-tenancy is contrasted with a multi-instance architecture where separate software instances (or hardware systems) are set up for different client organizations. With a multitenant architecture, a software application is designed to virtually partition its data and configuration, and each client organization works with a customized virtual application instance. Transparency is the capability to look inside the operational day-to-day activity of your cloud provider.

15.13

Load balancers can provide features such as SYN cookies and delayedbinding (the back-end servers do not see the client until it finishes its TCP handshake) to mitigate SYN flood attacks and generally offload work from the servers to a more efficient platform.

15-2

15 Chapter 16 COMPUTER NETWORKS AND DISTRIBUTED PROCESSING

16.6 15.5

INSTRUCTION ADD SHR LOA* STA TDX LOX

SPEED

OCCURENCE

(cycles) 8 4 12 8 8 8

20% 15% 20% 15% 15% 15%

The weighted average instruction speed = (8 X 0.2 + 4 X 0.15 + 12 X 0.2 + 8 X 0.15 + 8 X 0.15 + 8 X 0.15) = 8.2 cycles 6 2 MHz = 2x10 cycles/second The machine performs (1/8.2)* 2 = 0.244 MIPS To run at 2 MIPS, the clock frequency should be Clock Frequency= MIPS * Speed = 2 * 8.2 = 16.4 MHz

16.7 15.5 INSTRUCTION

ADD SHIFT LOA* STA* Geometric Mean

ASC1 8 4 12 12

ASC1 normalized 2 2 1.5 1 1.565

ASC2 6 4 8 8

ASC2 normalized 1.5 2 1 0.67

ASC3 4 2 8 12

1.189

ASC3 normalized 1 1 1 1

1

The relative performances are: ASC2/ ASC1 = 1.189 / 1.565 = 0.760 ASC3/ ASC1 = 1 / 1.565 = 0.640 ASC3/ ASC2 = 1 / 1.189 = 0.841 The relative performances are close to the ones in Example 15.4.

16.8 15.5

Refer to mathematical libraries with the vector processor systems available to you for these algorithms. Also refer to Levesque, 1989 and Ortega, 1988 for more details (See the references listed at the end of this chapter).

176

16-1

15.5 16.9

Consider the program segment depicted by part (a) in the flowchart below. Here A, B, C and D represent blocks of instructions. If parallel execution were not employed, the processor executes A, then executes either B or C depending on the condition. After that, it executes D and continues with the rest of the instructions.

In case of parallel execution, some data streams satisfy the condition a while others don't. Therefore, the processor tests the condition and sets s flag based on that condition. Then it performs all instructions that satisfie don't that those all s perform then the condition first (Instruction Block A), (Instruction B). After that it executes D and continues with the rest of the instructions. This is shown in part (b) of the flowchart. (a)

(b)

Onl: if in~ition is True

Onl! if t~ition

~ All

Continue

16.10 15.5

Continue

The scalar processor can execute the program in (1-x)*1 +x*20 time unites. The vector processor executes the code in (1-x) + x = 1 time per unit. Since the vector processor executes twice as fast as the scalar processor, (1 - X) * 1 + X * 20 = 2 *1 X = 1/19

177

16-2

16.11

PassMark provides two separate performance evaluations for the Android and iPhone mobile devices. Android and iOS benchmark tests are conducted to evaluate the CPU, disk, memory and graphics. CPU suite measures mainly the mathematical operations, encryption, and compression. Disk suite measures the reading and writing of internal and external file storage. Memory suite measures the reading and writing to memory locations. Graphic suite measure simple, complex vector and images, as well as complex scenes.

16.12

There are multiple benchmarks to evaluate Memory IO, CPU, disk IO, application, and network of the modern composite computing models like CLOUDSLEUTH for evaluating response time, STREAM for measuring memory bandwidth, LINPACK for measuring the floating point operations per second, Bonnie++ and IOzone for disk IO measurement, Bzip2 for cloud and grid computing application comparison, Iperf, MPPTEST for measuring network performance.

16.13

CIS assesses the system for patches and additional software, Minimization of the imitated services and the Demon services. Using CIS an evaluator can routinely assess the configuration of production systems compared to the CIS Benchmarks and internal security policies; Provide dashboard reporting capability; Create standard configuration images for hardening systems prior to deployment; Improve security awareness by comparing the security of "out-of-the-box" systems and hardened systems; and Assess and monitor multiple systems simultaneously by integrating CIS with system management utilities.

16-3

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