AimPCB ENGINEERING REVIEW · ISSUE 01
Flyback Power Supply PCB Design A 12 V / 1 A offline isolated converter, reviewed from the factory floor — with the full schematic and PCB layout
7
12 W
0.254
Findings that block a production
Output class, at the controller's
mm global clearance — across the
release
listed limit
mains barrier
aimpcb.com/blog/flyback-power-supply-pcb-design
SECTION 01
The design under review An offline isolated AC-DC flyback — not the analog board the filenames suggested.
Parameter
Value
Output
12 V / 1 A, approximately 12 W
Input
90–264 VAC universal
Controller
DK112 — self-powered flyback device, integrated 700 V BJT
Transformer
EE19 5+2
Secondary rectifier
SR3100, 3 A / 100 V class Schottky
Feedback
TL431 shunt reference with PC817C optocoupler
Setpoint divider
18 kΩ / 4.7 kΩ → ≈ 12.05 V against a 2.495 V reference
Output filter
680 µF / 10 µH / 680 µF pi network
Board
60.7 × 35.7 mm, two layers, ≈ 35 µm copper
Database state
≈ 35 PCB component records against 31 schematic symbols
The topology is conventional and entirely appropriate for a 12 W isolated supply. The release risk is not in the circuit. It is in the data. Why we published this
How to read it
Most published material on flyback design is written by people who have never had to build the board. It explains the topology, reproduces a reference schematic, and stops.
Everything here comes from the files themselves. Component values, board dimensions, clearance rules and database inconsistencies are as found. Where a part could not be qualified from the information supplied, we say so rather than assume.
This review goes the other way. It starts from a real set of design files that landed on our desk, and asks the only question a contract manufacturer can afford to ask: is this releasable?
The design under review
The answer was no — not because the circuit was wrong, but because the engineering data behind it was incomplete in ways that would have surfaced only after tooling.
02
FIGURE 01
The schematic, as released
Figure 1. 12 V / 1 A offline isolated flyback converter. Mains enters at F1 and RV1, through the MB6F bridge and the EE8.3 30 mH commonmode choke, into the 10 µF / 400 V bus. U1 (DK112) drives the EE19 primary; D1, R3, R4 and C8 form the leakage clamp. D2 (SR3100) rectifies the secondary into the 680 µF / 10 µH / 680 µF pi filter. U3 (TL431) and U2 (PC817C) close the loop across the barrier.
What the schematic tells us
What it does not
R8 at 18 kΩ and R9 at 4.7 kΩ set the output against the 2.495 V TL431 reference — approximately 12.05 V, consistent with the stated 12 V rail. C10 at 100 nF is the only compensation element in that loop.
T1 is annotated only as EE19 (5+2). There is no turns ratio, no primary inductance, no gap, no winding order and no insulation system — the parameters that decide whether the supply is safe and whether it can deliver 12 W at low line.
CY1 is drawn as 222 / 400 V and sits directly across the barrier. CX1 is drawn as 0.1 µF / 275 V across line and neutral.
The schematic, as released
Neither CX1 nor CY1 carries a manufacturer part number or a safety class. Both are mains-connected suppression capacitors, and a voltage rating is not an approval.
03
FIGURE 02
The board, 60.7 × 35.7 mm
Figure 2. Two-layer board, approximately 35 µm copper. Mains entry at lower left through F1, RV1 and CX1; the bridge and bulk capacitors C1 and C2 across the top left; T1 central; CY1 bridging the barrier above the transformer; D2, C6, L2 and C7 forming the secondary output stage on the right.
What the board does well
What has to be proven
The physical separation is sensible: primary on the left, secondary on the right, with T1 and CY1 occupying the barrier region and the optocoupler U2 placed beneath it. D2, C6 and C7 sit close to the secondary pins, which keeps the rectifier loop compact.
Separation that looks adequate is not the same as separation that has been specified. The board carries a single global clearance rule of 0.254 mm, with no distinct primary-to-secondary safety rule, no keepout around T1, U2 and CY1, and a net database that cannot support netaware checking of either.
The board, 60.7 × 35.7 mm
04
SECTION 02
Energy path and the isolation barrier AC L / N
mains inlet
F1 · RV1 · CX1
2 A fuse, 7 mm MOV, line filter
DB1
MB6F full-wave bridge
C1 · L1 · C2
10 µF / 400 V high-voltage bus
T1 + DK112
EE19 transformer, 700 V switch ISOLATION BARRIER · T1 · PC817 · CY1
D2
SR3100 Schottky, 3 A / 100 V
C6 · L2 · C7
680 µF pi filter → 12 V / 1 A
The feedback loop 12 V output after L2 → R8 / R9 divider → TL431 with C10 → PC817C → DK112 feedback pin. Because the divider senses the output after the filter, the LC dynamics of that filter sit inside the control loop.
There is no star point across the barrier. Separation here is a safety property, not a grounding preference. Primary and secondary grounds must never share copper. Controlled coupling is permitted only through transformer parasitic capacitance, the optocoupler, and a certified Y capacitor.
Energy path and the isolation barrier
The clamp network formed by D1, R3, C4 and R4 absorbs leakage energy at turn-off. Its loop must be physically tiny: parasitic inductance contributed by the PCB directly reduces clamp effectiveness and increases ringing on the switch node.
05
SECTION 03
Four numbers that decide this design 100 %
93 %
of the DK112's listed 12 W output-power category is
of the 400 V bulk-capacitor rating is reached at the 373 V
used by a 12 W product
peak at 264 VAC
1.93 kHz
200–400 %
L2 · C7 resonance — a double pole sitting inside the
PC817C current transfer ratio at a single bin, before
voltage-control loop
temperature and ageing
A headline rating is not a margin
Two loops, not one
Ambient temperature, enclosure, transformer loss, minimum line voltage, conduction mode and PCB copper all reduce what reaches the load. A device listed at 18 W is a candidate if testing shows inadequate margin — but that is a power-stage redesign, not a BOM change.
The divider senses the output after L2, so the filter resonance is a control-loop element rather than a ripple detail. A board stable on the bench at room temperature can go underdamped at another load, or with a different electrolytic ESR.
At 264 VAC a 400 V electrolytic runs at roughly 93 % of rating before any abnormal mains event. A 450 V part deserves evaluation. The bus must also be assessed dynamically: the minimum valley under low-line full-load governs peak primary current, duty ratio and flux density.
The optocoupler spread is inherent to phototransistor devices, not a defect. Compensation must hold at both ends of it. The shunt-reference cathode current, LED bias, controller feedback pin and C10 form a single loop, and a 100 nF capacitor chosen empirically proves nothing about robustness.
Four numbers that decide this design
06
SECTION 04
Seven findings that block release Insulation coordination comes from the end-product standard. Never from a default CAD clearance rule.
An empty net database The parsed net stream in the PCB file is empty and track objects carry no usable network assignment, so net-aware design-rule checking cannot be trusted. The fix is regenerating connectivity from the released schematic and reviewing the resulting engineering change order.
Designator mismatch Roughly 35 PCB component records against 31 schematic symbols. Every difference must be intentionally dispositioned before release.
A 10 mil global clearance rule 0.254 mm may be a reasonable low-voltage manufacturing clearance. It cannot be used to claim mains-to-SELV reinforced insulation, which derives from working voltage, impulse conditions, pollution degree, material group, altitude and insulation class.
CX1 identified by voltage alone “0.1 µF / 275 V” is a value, not an approval. An X2 safety capacitor requires a specific manufacturer part number with recognised certification.
CY1 crossing the barrier Marked as approximately 2.2 nF at 400 V. An ordinary 400 V film capacitor is not an acceptable substitute for a Y-classified part on the component that bridges primary and secondary.
A transformer called “EE19 5+2” That names a core and a pin count. A production drawing needs core material, gap, primary inductance and tolerance, turns ratios, winding sequence, wire gauge, DCR limits, leakage inductance, withstand voltage, insulation system, bobbin creepage and temperature limits.
Ambiguous GND / SGND labelling A global label capable of logically joining both domains can cause a future engineering change or a regenerated PCB to create a dangerous connection, even where the present physical board happens to be separated.
Seven findings that block release
07
SECTION 05
Layout rules that decide EMI and safety Primary high-di/dt loop CBULK+ → T1 primary → U1 switch → CBULK− Minimum physical area. The switch node is simultaneously a high-dv/dt field source; the common temptation to spread it into a large thermal pour buys avoidable common-mode capacitance and radiated emissions.
Secondary high-di/dt loop T1 secondary → D2 → C6 → secondary return L2 and C7 form the subsequent low-ripple path. Place by current loop, not by visual symmetry.
Quiet feedback region R8 / R9 Kelvin-sensed after L2, returned to C7 Neither trace may share meaningful copper impedance with the rectifier loop. The divider is an analog circuit embedded inside a switching converter and should be treated as one.
Safety net classes to declare in the PCB tool MAINS_L / N
RECTIFIED_HV
PRIMARY_HOT_GND
Primary-to-primary functional spacing and primary-tosecondary safety spacing are different rules, and both belong in the CAD tool — accompanied by a dedicated nocopper corridor around the transformer, the optocoupler and the Y capacitor. Pours on either layer obey the same barrier.
Layout rules that decide EMI and safety
SWITCH_NODE
SECONDARY_0V
12V_OUT
Slots can usefully increase creepage where board area is constrained, but must be deliberately designed and manufactured. Solder mask is not a substitute for a required physical insulation distance unless the applicable product standard and construction explicitly permit that insulation system.
08
SECTION 06
Risk priorities and corrective order Pri
Finding
Impact and required action
P0
Empty net database, unassigned tracks
Net-aware DRC unreliable; update from the released schematic and review the ECO
P0
PCB and schematic designator mismatch
Every PCB-only designator must be intentionally dispositioned
P0
≈ 10 mil global clearance
Define primary-to-secondary clearance, creepage and keepout from the end-product standard
P0
CY1 / CX1 by voltage only
Specify approved Y- and X2-class parts for the insulation system
P0
Transformer specified by core only
Release the full magnetic and insulation specification
P0
Ambiguous ground labelling
Verify domain separation by electrical rule check in the original CAD project
P1
Controller at its listed power category
Verify low-line, full-load, high-temperature enclosed operation
P1
400 V bulk electrolytics · 100 V rectifier
Evaluate 450 V parts; measure high-line reverse peak and ringing
P1
1.93 kHz LC inside the feedback path
Measure the loop response and compensation at both optocoupler corners
P2
Fuse, varistor and output-capacitor margin
Check I²t, surge, abnormal fault behaviour and lifetime
The order in which to fix them 1. Restore the CAD database. Regenerate connectivity and engineering change data from the released schematic.
4. Release the transformer specification. Ratio, inductance, DCR, core, gap, construction, withstand voltage, creepage.
2. Define the insulation system. Derive safety spacing from the end-product category, then enter the rules in the design tool.
5. Resolve the ground-naming ambiguity. Distinct primary and secondary reference names throughout.
3. Qualify the safety capacitors. Exact part numbers, correct X and Y classes, approval documents.
Risk priorities and corrective order
6. Verify the closed loop. Include post-filter dynamics in simulation and frequency-response measurement.
09
READ THE FULL REVIEW
The complete article — with the full component tables and the detailed analysis behind every finding aimpcb.com/blog/flyback-power-supply-pcb-design What we do AimPCB is the brand of Tianjin Huaxing Chengda Electronics Co., Ltd. We design, fabricate and assemble printed circuit boards for engineering teams in Europe and North America — from a single prototype through to volume production, with the design review done before the stencil is cut. PCB design
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Engineering reference only, based on historical design files. Not a certified or production-ready product. AimPCB Engineering Review · Issue 01 · Tianjin Huaxing Chengda Electronics Co., Ltd.