Spartan UltraScale+ architecture Based on a 16 nm process node, the UltraScale architecture blends logic density, deterministic timing, high-speed connectivity, and memory bandwidth in a scalable platform. The Spartan UltraScale+ family extends these capabilities to cost-optimized applications with high I/O counts, transceiver support, and hard IP for an LPDDR5-class memory interface, while maintaining low power consumption and offering long product lifecycles. The architecture is built around high-performance, programmable logic coupled with embedded memory, DSP resources, and high-speed I/O. At its core, it uses configurable logic blocks (CLBs) that contain 6-input Look-Up Tables (LUTs), fast carry chains, and flip-flops, enabling efficient implementation of both combinational and sequential logic. Spartan UltraScale+ devices incorporate several tiers of memory, including 36 Kb block RAM with builtin ECC and FIFO modes, 288 Kb UltraRAM blocks in larger device sizes offering deeper, more powerefficient storage, and distributed RAM in the LUTs for fast, localized memory. DSP48E2 slices deliver compute capability with 27×18 multipliers, pre/post adders, accumulators, and wide XOR logic, allowing the architecture to meet demanding signal processing workloads. High-speed serial connectivity is delivered through GTH transceivers, which operate at up to 16.3 Gb/s and appear in devices larger than the Spartan UltraScale+ SU35P devices.
These transceivers include sophisticated equalization, pre-emphasis, and adaptive receiver features designed to support long PCB traces, backplanes, and modern high-speed protocols. Devices with transceivers also provide hard IP for PCIe® Gen4 blocks. Clocking resources are organized into clock management tiles, each containing a MixedMode Clock Manager (MMCM) and two PhaseLocked Loops (PLLs). Global and regional clock routing networks ensure low skew and flexible distribution. The architecture’s segmented clocking scheme reduces power and improves determinism, while the ability to derive clocks from PLLs, MMCMs, or transceiver outputs provides system-level flexibility. Integration between the clocking network and memory interfaces ensures stable timing for Double Data Rate (DDR) memory and high-performance physical layers (PHYs). Memory interfaces are another major strength of the UltraScale+ portfolio. While traditional DDR4 interfaces remain widely supported, Spartan UltraScale+ devices introduce hard IP controllers for LPDDR4X and LPDDR5, delivering data rates up to 4266 Mb/s via the XP5IO banks. These hard IP controllers reduce both logic utilization and power, and simplify PCB design compared to soft memory controllers. Devices larger than the SU35P in the Spartan UltraScale+ range support PCIe Gen4 through integrated hard blocks, which also enable a reduction in power dissipation compared to soft implementations.
Getting started with logic folding
Pipelining – Provide pipeline registers at the beginning or end of the datapath module. This allows the synthesis tool to perform retiming, inserting registers in the datapath as needed to achieve the highest performance.
When it comes to implementing designs on a Spartan UltraScale+ FPGA using logic folding, we can leverage the capabilities of the programmable logic to implement a solution that is not only faster but also operates at a higher clock frequency.
Placement wrapper – Create wrappers around a module to register its I/O. This provides the implementation tool with the ability to locate the registers as needed in the routing path to improve timing closure.
A good way to demonstrate this is to migrate a module from a Spartan 7 XC7S100 in a -2 speed grade to a Spartan UltraScale+ XCSU35P FPGA, also in a -2 speed grade with a voltage supply of Vnom. The module combines several features common to FPGA applications: a CIC filter implementing a rolling average, high-speed AXI-Stream interfaces, and Cyclic Redundancy Check (CRC) protection.
Write flexible code – Leverage generics and parameters to enable the module to be easily configurable for different bus widths, etc. Leverage capabilities – Take advantage of the device features, such as the Single Instruction, Multiple Data (SIMD) pattern detection capabilities of the DSP48E2.
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