Letter from the Publisher Welcome to Xcell Software Journal
SOFTWARE PUBLISHER Mike Santarini mike.santarini@xilinx.com 1-408-626-5981 EDITOR
Diana Scheben
ART DIRECTOR
Scott Blair
DESIGN/PRODUCTION Teie, Gelwicks & Assoc. 1-408-842-2627 ADVERTISING SALES Judy Gelwicks 1-408-842-2627 xcelladsales@aol.com INTERNATIONAL Melissa Zhang, Asia Pacific melissa.zhang@xilinx.com Christelle Moraga, Europe/Middle East/Africa christelle.moraga@xilinx.com Tomoko Suto, Japan tomoko@xilinx.com REPRINT ORDERS 1-408-842-2627
EDITORIAL ADVISERS Tomas Evensen Lawrence Getman Mark Jensen
Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124-3400 Phone: 408-559-7778 FAX: 408-879-4780 www.xilinx.com/xcell/
© 2015 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. The articles, information, and other materials included in this issue are provided solely for the convenience of our readers. Xilinx makes no warranties, express, implied, statutory, or otherwise, and accepts no liability with respect to any such articles, information, or other materials or their use, and any use thereof is solely at the risk of the user. Any person or entity using such information in any way releases and waives any claim it might have against Xilinx for any loss, damage, or expense caused thereby.
Earlier this year, Xilinx® released its SDx™ line of development environments, which enable non-FPGA experts to program Xilinx device logic using C/C++ and OpenCL™. The goal of the SDx environments is to let software developers and embedded system architects program our devices as easily as they program GPUs or CPUs. Xilinx’s FPGA hardware technology has long been able to accelerate algorithms, but it was only recently that the underlying software technology and hardware platforms reached a level where it was feasible to create these development environments for the broader software- and system-architect communities of C/C++ and OpenCL users. The hardware platforms have evolved rapidly during this millennium. In the early 2000s, the semiconductor industry changed the game on software developers. To avoid a future in which chips reached the energy density of the sun, MPU vendors switched from monolithic MPUs to homogeneous multicore, distributed processing architectures. This switch enabled the semiconductor industry to continue to introduce successive generations of devices in cadence with Moore’s Law and even to innovate heterogeneous multicore processing systems, which we know today as systems-on-chip (SoCs). But the move to multicore has placed a heavy burden on software developers to design software that runs efficiently on these new distributed processing architectures. Xilinx has stepped in to help software developers by introducing its SDx line of development environments. The environments let developers dramatically speed their C/C++ and OpenCL code running on systems powered by next-generation processing architectures, which today are increasingly accelerated by FPGAs. Indeed, FPGA-accelerated processing architectures, pairing MPUs with FPGAs, are fast replacing power-hungry CPU/GPU architectures in data center and other compute-intensive markets. Likewise, in the embedded systems space, new heterogeneous multicore processors such as Xilinx’s Zynq®-7000 All Programmable SoC and upcoming Xilinx UltraScale+™ MPSoC integrate multiple processors with FPGA logic on the same chip, enabling companies to create next-generation systems with unmatched performance and differentiation. FPGAs have traditionally been squarely in the domain of hardware engineers, but no longer. Now that Xilinx has released its SDx line of development environments to use on its hardware platforms, the software world has the ability to unlock the acceleration power of the FPGA using C/C++ or OpenCL within environments that should be familiar to embedded-software and -system developers. This convergence of strong underlying compilation technology for our high-level synthesis (HLS) tool flow with programming languages and tools designed for heterogeneous architectures brings the final pieces together for software and system designers to create custom hardware accelerators in their own heterogeneous SoCs. Xcell Software Journal is dedicated to helping you leverage the SDx environments and those from Xilinx Alliance members such as National Instruments and MathWorks®. The quarterly journal will focus on software trends, case studies, how-to tutorials, updates and outlooks for this rapidly growing user base. I’m confident that as you read the articles you will be inspired to explore Xilinx’s resources further, testing out the SDx development environments accessible through the Xilinx Software Developer Zone. I encourage you to read the Xcell Daily Blog, especially Adam Taylor’s chronicles of using the SDSoC development environment. And I invite you to contribute articles to the new journal to share your experiences with your colleagues in the vanguard of programming FPGA-accelerated systems.
— Mike Santarini Publisher
There is a new bass player for the blues jam in the sky . . . This issue is dedicated to analyst and ESL visionary Gary Smith, 1941 – 2015.