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user_logic.vhd. It is in this latter file that you create your design. You will find that the wizard has already given you a helping hand by generating the registers and interfaces necessary to communicate over the AXI bus within this file. The user-logic module is instantiated within led_if.vhd. Therefore, any changes you make to the entity of user_logic.vhd must be flowed through into the port map. If external ports are required—as they are in our example design, to flash the LED—you must also flow through your changes in the entity of led_if.vhd. Once you have created your logic design, you may wish to simulate it to ensure that it functions as desired. Busfunctional models are provided under the Pcores/devl/bfmsim directory. USING YOUR MODULE WITHIN XPS Having created the VHDL file or files and ensuring they function, you will wish to use the module within your XPS project. To correctly do this you will need to ensure the Microprocessor Peripheral Description file is up to date with the ports you may have added during your VHDL design. You can accom-
plish this task by editing the MPD file within XPS. You will find your created peripheral under the Project Local Pcores->USER->core name. Rightclicking on this name will enable you to view your MPD file. You will need to add the non-AXI interfaces you included in your design so that you can see the I/Os and deal with them correctly within XPS. You will find the syntax for the MPD file at http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/p sf_rm.pdf, although it is pretty straightforward, as you can see in Figure 3. The highlighted line (line 59, at the bottom of the central list) is the one I added to bring my LED output port to the module. When you have updated the MPD file, you must click on “re-scan user IP repositories” to ensure the changes are loaded into XPS. At that point, you can then implement the device into your system just like any other peripheral from the IP library. Once you have it in the address space you want (remember, the minimum is 4K) and have connected your outputs as required to external ports, if necessary you can run the design rule checker. Provided there
are no errors, you can close down XPS and return to PlanAhead. Back within the PlanAhead environment, you need to regenerate the top level of HDL; to do this, just right-click on the processor subsystem you created and select “create top HDL” (see Xcell Journal issue 82 for information on creating your Zynq SoC PlanAhead project). The final stage before implementation is to modify the UCF file within PlanAhead if changes have been made to the I/O pinout of your design. Once you are happy with the pinout, you can then run the implementation and generate the bitstream ready for use in the SDK. USING THE PERIPHERAL IN SDK Having gotten this far, we are ready to use the peripheral within the software environment. As with the tasks of creation and implementation, this is an easy and straightforward process. The first step is to export the hardware to the Software Development Kit using the “export hardware for SDK” option within PlanAhead. Next, open the SDK and check the MSS file to make sure that your created peripheral is now present. It should be listed with the name of the
Figure 2 – The next two windows, covering name, revision and bus standard selection
Third Quarter 2013
Xcell Journal
45