SPI flash in the Enhanced Quad mode of the AXI Quad SPI IP core. The document is based on using the KC705 board with Numonyx SPI memory, which, with a few modifications in the software example files, can be tested on any other board. Authors Sanjay Kulkarni and Prasad Gutti show how to measure the performance of the system by writing and reading 1 Mbyte of data to and from SPI flash. These systems are built using Xilinx Platform Studio (XPS), v14.4, which is part of the ISE® Design Suite System Edition. The design also includes software, built using the Xilinx Software Development Kit, that runs on a MicroBlaze processor subsystem and implements control, status and monitoring functions. The main focus of this application note is to measure the SPI bandwidth where the core is configured in Quad SPI mode with an SPI clock rate of 40 MHz. XAPP1084: DEVELOPING TAMPER-RESISTANT DESIGNS WITH XILINX VIRTEX-6 AND 7 SERIES FPGAS http://www.xilinx.com/support/documentation/application_notes/xapp1084_tamp_resist_dsgns.pdf Keeping one step ahead of the adversary, whether military or commercial, is a continuous process that involves understanding the potential vulnerabilities and attacks, and then developing new mitigation techniques or countermeasures to combat them. By taking advantage of various Xilinx FPGA anti-tamper (AT) features, a systems engineer can choose how much AT to include with the FPGA design, enabling individual silicon AT features or combining a number of them. This application note provides anti-tamper guidance and practical examples to help the FPGA designer protect the intellectual property (IP) and sensitive data that might exist in an FPGA-enabled system. Tamper resistance needs to be effective before, during and after the FPGA has been configured by a bitstream. Sensitive data can include the configuration data that sets up the functionality of the FPGA logic, critical data or parameters that might be included in the bitstream, along with external data that is dynamically brought in and out of the FPGA during post-configuration normal operation. Author Ed Peterson summarizes the silicon AT features available in the Virtex-6 and 7 series devices and offers guidance on various methods you can employ to provide additional tamper resistance.
Second Quarter 2013
XAPP739: AXI MULTI-PORTED MEMORY CONTROLLER http://www.xilinx.com/support/documentation/application_notes/xapp739_axi_mpmc.pdf Designers use a multiported memory controller (MPMC) in applications where several devices share a common memory controller. This is often a requirement in many video, embedded and communications applications, where data from multiple sources moves through a common memory device, typically DDR3 SDRAM memory. This application note by Khang Dao and Dylan Buli demonstrates how to create a basic DDR3 MPMC design using the ISE Design Suite Logic Edition tools, including Project Navigator and CORE Generator™. The idea is to create a high-performance MPMC by combining the Memory Interface Generator (MIG) IP block and the AXI Interconnect IP block, both provided in the ISE Design Suite Logic Edition. The AXI interfaces used in this example design consist of AXI4, AXI4-Lite and AXI4-Stream, all of which provide a common IP interface protocol framework for building the system. The example design, a full working hardware system on the Virtex-6 FPGA ML605 evaluation platform board, implements a simple video system in which data from a video test pattern generator loops in and out of memory multiple times before being sent to the DVI display on the board. The DDR3 memory therefore acts as a multiported memory shared by multiple video frame buffers. XAPP593: DISPLAYPORT SINK REFERENCE DESIGN http://www.xilinx.com/support/documentation/application_notes/xapp593_DisplayPort_Sink.pdf This application note by Arun Ananthapadmanaban and Vamsi Krishna describes the implementation of a DisplayPort™ sink core and policy maker reference design targeted for a MicroBlaze processor in the Spartan-6 FPGA Consumer Video Kit. The reference design is a loopthrough system that receives video from a DisplayPort source via the receive link, buffers the video data and retransmits it over the DisplayPort transmit link. The policy maker performs several tasks, such as initialization of GTP transceiver links, register probing and other features useful for bring-up and use of the core. The application controls both the sink and source of the reference design and communicates with the monitor (sink) connected on the transmit port of the reference design using the auxiliary channel. The reference design uses DisplayPort source and sink cores generated from the Xilinx CORE Generator tool, along with a policy maker and frame buffer logic using external memory. Xcell Journal
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