X P L A N AT I O N : F P G A 1 0 1
Signal
Description
d_mat1_V_read
Signals when the design is ready for inputs to matrix 1 (left matrix)
d_mat1_V_dout [15:0]
16-bit streaming element of matrix 1
d_mat1_V_empty
Signals to the design that no more elements for matrix 1 are left
d_mat2_V_read
Signals when the design is ready for inputs to matrix 2 (right matrix)
d_mat2_V_dout [15:0]
16-bit streaming element of matrix 2
d_mat2_V_empty
Signals to the design that no more elements for matrix 2 are left
d_product_V_din [15:0]
16-bit output element of product matrix
d_product_V_full_n
Signals that product matrix should be written to
d_product_V_write
Signals that data is being written to the product matrix
ap_clk
Clock signal for design
ap_rst
Active high synchronous reset signal for design
ap_start
Start signal to begin computation
ap_done
Done signal to end computation and signal output ready
ap_idle
Idle signal to indicate that the entity (design) is idle
ap_ready
Indicates to the data-feeding stage that the design is ready for new input data; to be used in conjunction with ap_idle Table 3 – Description of signals for the design in Figure 5
Device: XC6VCX75TFF784-2 Design Metric
Without BRAM or distributed RAM for matrices
With single-port BRAM for matrices
With distributed RAM (implemented in LUTs) for matrices
DSP48E
1
1
1
Lookup tables
185
109
179
Flip-flops
331
102
190
BRAM
0
3
0
Best achieved clock period (ns)
2.886
3.216
2.952
Latency
84
116
104
Throughput (initiation interval)
84
116
104
Table 4 – Design metrics for the design in Figure 5
38
Xcell Journal
Second Quarter 2013