XCELLENCE IN AEROSPACE & DEFENSE
A Digital ADC IP core on a radiation-hardened FPGA can get down to 0.5-Hz bandwidth per channel and can consume less than 6 mW, compared with 335 mW for an external part. instantiated right inside the FPGA and is easy to implement through digital synthesis. On a Xilinx® Virtex®-5QV device, a scenario such as that pictured in Figure 1 utilizes less than 1 percent of FPGA resources. Proprietary signal processing makes it possible to replicate analog sigma-delta ADC performance with all-digital library cells. Companies like SEAKR Engineering and the Finnish Meteorological Institute are
synthesizable and digitally testable design. Designers can create digital IP blocks of ADCs, DACs, DC/DC converter controllers and clock multipliers in RTL format and implement them in all-digital processes. With these IP blocks, military designers can take advantage of rugged and radiation-hardened FPGAs to implement customized analog functions. Not only does this approach leverage the inherent protection prop-
Analog Input
FPGA or ASIC
LVDS Input +
Reconstruction Filter
Digital Core
– Digital Output
Clock Input
Figure 1 – An example of a fully digital ADC IP core interface
erties of the FPGA, but these blocks are also a great way to utilize unused FPGA resources. Xilinx recognizes this advantage and now partners with Stellamar to provide these functions. Increasingly, aerospace companies are turning to these solutions to attack analog-integration problems. DIGITAL ADC CORE YIELDS BENEFITS Figure 1 depicts an example block diagram of a Stellamar Digital ADC IP core. With the digital approach, the core requires only a few external passive components. The IP core is 20
Xcell Journal
using Digital ADC IP in their On Board Processor Program and Lunar Landing Missions, respectively. Some benefits are: • 50 percent lower power than analog ADC parts • 68 percent smaller area than analog ADC parts • Process technology independence • Reduced risk and cycle time • Digital integration, synthesis and testing • Easier radiation-hardened design
PERFORMANCE PLUS APPLICATIONS Current performance is up to 15 bits of resolution and several hundred kilohertz of bandwidth. Bandwidth depends on the selected resolution. This level of performance is suitable for a host of applications including sensors (temperature, pressure, voltage, current and acceleration), touchscreen integration, high-quality voice and motor control. As an example, many design teams use a radiation-hardened, 12-bit, 10MHz bandwidth ADC part for monitoring onboard temperature and voltage. Some FPGAs, such as the Xilinx Virtex-5QV space-grade FPGA, even have embedded diodes highlighting the importance of the temperaturesensing function. However, normal bandwidths for these types of measurements are 0.5 Hz to 10 Hz, so using bandwidth in the megahertz is like driving the head of a pin with a sledgehammer. A Digital ADC IP core on a radiation-hardened FPGA can get down to 0.5-Hz bandwidth per channel and can consume less than 6 mW, compared with 335 mW for the external part. Why waste critical board space and power for such a low-level task? CONTROLLING DC/DC POWER MANAGEMENT Power management is becoming a larger part of overall system design. Sometimes a single design can include more than 30 power supplies. External radiation-hardened DC/DC converters retain the same difficulties as external ADCs. Thus, the use of these parts to control power complexity in high-reliability applications does not scale well. First Quarter 2013