TOOLS OF XCELLENCE
The FPGA has access to all of the board's data and control paths, enabling factory-installed functions such as data multiplexing, channel selection, data packing, gating, triggering and memory control. Each function exists as an IP block. sum signal. A CPU analyzes this sum signal and makes adjustments to the phase and gain coefficients to track or adapt to new targets. PENTEK MODEL 53661 BEAMFORMING BOARD The Pentek Model 53661 software radio board is a 3U OpenVPX Cobalt board shown in the simplified block diagram of Figure 3. It features four 200-MHz, 16-bit A/D converters; a timing, clock and synchronization section; and a Xilinx Virtex-6 FPGA. The FPGA has access to all of the board’s data and control paths, enabling factory-installed functions such as data multiplexing, channel selection, data packing, gating, triggering and memory control. The
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Cobalt architecture organizes the FPGA as a container for data-processing applications where each function exists as an intellectual property (IP) module. We can use a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include the LX240T, LX365T, SX315T and SX475T. The SXT parts feature up to 2,016 DSP48E slices and are ideal for modulation/demodulation,encoding/decoding, encryption/decryption and channelization of the signals between transmission and reception. Factory-installed in the FPGA are four DDC IP cores, each capable of accepting A/D samples from any of the four A/Ds. Each DDC has a decimation
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range of 2k to 64k and can deliver downconverted baseband bandwidths from 2.5 kHz to 80 MHz. Each DDC has programmable gain and phase shift controls accessible to the processor across the VPX backplane. In this system we will be assigning one A/D to each DDC. A power meter at the output of each DDC calculates the downconverted signal power. Each power meter is equipped with a threshold detector that generates a system interrupt if the output power exceeds the upper threshold or falls below the lower threshold. These features simplify gain calibration and signal-monitoring tasks that the system processor would otherwise have to do in software. The 53661 FPGA also includes a native Aurora summation block that
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8 total
A/D
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A/D
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DDC
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Gain
Gain
Phase
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Phase
Phase
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Frequency Gain, and Phase Control
CPU
Figure 2 – Eight-channel beamforming system block diagram
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Xcell Journal
Third Quarter 2012