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tor) at the programmable-system level. This file defines the interface of the PRM module with the programmablesystem components such as the Peripheral Local Bus (PLB) v4.6. The User_logic.vhd represents the user logic function, and it includes the instance of the PRM module. Once the programmable-system design has been completed, we can generate the NGC file for this configuration. Using XPS, we defined the programmable-system as well as the general system architecture. It’s important to note that we defined all the PRMs as a black box in XPS. Using PlanAhead™ we can merge the outputs and NGC files coming from the two processes, XST and XPS, in order to have just a few PRM bitstreams and a default bitstream. A top-level implementation will be defined and built up using the NGC file from XPS and one of the NGC files from XST. The designer then needs to add a partial-reconfiguration region to the design and must specify the NGC file associated with it. The last step is to promote this configuration in order to make this implementation the default system implementation that will load into the system at startup. The output of this process will be the default bitstream. To build the PRMs’ bitstream files, we must reopen PlanAhead and, starting from scratch, check the option “PR project” in order to import all the NGC files. PlanAhead will generate a distinct bitstream for each of those PRMs. In our case, it outputs two PRM bitstreams, one for demodulator1k and the other for demodulator2k. For debug purposes, we suggest creating n (number of PRMs) different static implementations, one for each PRM. In this case the designer will have n static full implementations, each of which will perform the function of the nth PRM statically attached to the FPGA. In our opinion, this is a good compromise between debug needs and development complexity. Third Quarter 2012
The last step is to download the generated bitstream into our target device. You can program the device using the IMPACT tool as well as the command-line data2mem and the Xilinx Microprocessor Debugger (XMD) tool, in case you need to store the bitstream and System ACE™ file in a CompactFlash. In our case, we opted to program the device by command-line methods, since the ML507 Xilinx board has a CompactFlash on it and the System ACE manages the CompactFlash as a boot device. TRANSFORMABLE DEVICES Compared with static reconfiguration, the technique of partial dynamic reconfiguration is extremely efficient in terms of the time it takes for reconfiguration to occur. Although the time is related to the physical dimensions of the PRMs, if these modules can be smaller than the full bitstream by even one gain factor, that implies a time of reconfiguration of tens vs. hundreds of milliseconds. The use of PDR brings FPGA system design to another level, giving the designer an opportunity to drastically reduce the power consumption and the cost of a whole system. In the context of the EU’s pSHIELD research project, where design criteria such as security, privacy and dependability are the main factors, we found the PDR technique extremely useful. The possibility of changing a cryptographic algorithm or communication protocol on the fly while keeping the other functionality alive was a big advantage. With this approach, we think that the FPGA is going to usher in a new era in electronic design. We are envisioning systems that can change their functionality and adapt themselves to a specific scenario or threat. In short, we are thinking of a world made up of transformable devices.
TE0630 Xilinx Spartan-6 LX (USB)
• Scalable: 45 k to 150 k Logic Cells • Hi-Speed USB 2.0 • Very Small: 47.5 × 40.5 mm • Compatible with TE0300
GigaBee Xilinx Spartan-6 LX (Ethernet)
• Scalable: 45 k to 150 k Logic Cells • Gigabit Ethernet • 2 Independent DDR3 Memory Banks • LVDS I/Os • Very Small: 40 x 50 mm • Coming Soon: Version Common Features • On-Board Power Supplies • Very Low-Cost • Long-Term Available • Open Reference Designs • Ruggedized for Industrial Applications • Customizable • Custom Integration Services Development Services • Hardware Design • HDL Design • Software Development
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