X C E L L E N C E I N S O L I D - S TAT E D I S K S
olid-state disk (SSD) technology based on NAND flash memory provides higher throughput and lower power consumption than traditional mechanical-drive-based storage systems. For that reason, SSD usage has mushroomed over the last decade, moving from handheld devices to laptop and desktop computers and, now, making incursions into the enterprise storage market. The rapid rate of expansion has been further aided by the enterprise storage industry’s adoption of SSDs based on the Serial Advanced Technology Attachment (SATA) standard. However, as SSD manufacturers look toward next-generation systems that achieve new performance and density highs by using flash memory that is implemented in 19-nanometer process technology, SATA hasn’t kept up. Even with the latest revision (SATA 3.0), the 6-Gbps physical interface hardly meets the highest throughput of the SSD NAND flash arrays, and thus leaves extra performance on the table.
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To break the interface bottleneck, SSDs based on PCI Express® are making a huge impact on the market. PCIe® is an industry-standard local bus with higher performance and scalability than SATA. It is based on multilane high-speed serial links that support one to 16 lanes, each operating at up to 8 Gbps (2.5 Gbps for Gen1, 5 Gbps for Gen2, 8 Gbps for Gen3). The PCIe interface for SSDs supports gigabyte throughput and better margins for the foreseeable future as NAND flash technology evolves. However, creating a PCIe-based SSD system using 19-nm flash has its share of challenges. The PCIe interface requires more high-speed serial links and more-complex interconnect than SATA. The throughput demands require the PCIe direct memory access (DMA) to operate at a gigabyte bandwidth level. In addition, at the 19-nm process node, flash reliability—or specifically, the metric known as “wear” (the number of times a NAND can read or write before encountering
AXI 4 Bus
9 x 2 Gbit DDR3
32-MB XOR Flash
Temperature Sensor
MIG DDR3 Controller
QSPI Flash Controller
IIc Controller
Interrupt Controller
System Controller
MicroBlaze
7 Series PCIe Core PCIe Gen 2 x 8
TLP RX Engine
DMA RX Engine
DMA Register
TAG Module
an error)—is a growing issue. At 19 nm, companies must perform wear leveling and error correction faster than ever before. Xilinx® Kintex™-7 FPGAs establish a new benchmark for FPGA high-end performance at less than half the price of previous-generation FPGAs. The Kintex-7 family is one of four product lines Xilinx built using TSMC’s HPL (high-performance, low-power) 28-nm process, designed for maximum power efficiency and delivering a twofold price/performance improvement while consuming 50 percent less power than previous generations. Kintex-7 FPGAs offer high-density logic, high-performance transceivers, memory and DSP, plus Agile Mixed Signal—all to enable higher systemlevel performance and the next level of integration. These capabilities allow for continued innovation and differentiation in designs at volume price points. As such, Xilinx’s Kintex-7 series FPGAs are ideally suited for use as 19-nm flash PCIe SSD controllers.
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On-Chip Register File
AXI 4 Lite Bus TLP RX Engine Interrupt
DMA TX Engine PCIe SG-DMA Subsystem
Kintex-7 325 T
RS-232
UART
0
BRAMs
MicroBlaze
Identify Chip
Data Address Translate
High-Speed Intelligent ECC Ecoding
High-Speed Wear Leveling/ Flash Block Manage
19-nm Flash Controller
Data Address Translate
High-Speed Intelligent ECC Ecoding
CPU Subsystem
Storage Subsystem 19-nm Flash Arrays
Figure 1 – The Kintex-7 SoC solution for a PCIe 19-ns NAND flash SSD consists of three subsystems: CPU, storage and PCIe SG-DMA. Third Quarter 2012
Xcell Journal
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