X P L A N AT I O N : F P G A 1 0 1
FOR i IN 1 TO 14 LOOP IF z_array(i-1) < to_signed(0,17)
DOWNTO 0));
THEN
END ARCHITECTURE rtl;
x_array(i) <= x_array(i-1) + (y_array(i-1)/2**i); y_array(i) <= y_array(i-1) (x_array(i-1)/2**i); z_array(i) <= z_array(i-1) + tan_array(i); ELSE x_array(i) <= x_array(i-1) (y_array(i-1)/2**i); y_array(i) <= y_array(i-1) + (x_array(i-1)/2**i); z_array(i) <= z_array(i-1) tan_array(i); END IF; END LOOP; END IF; END PROCESS; cos_op <= std_logic_vector(x_array(x_array'high)(16 DOWNTO 0)); sin_op <= std_logic_vector(y_array(y_array'high)(16
There are two basic topologies for implementing a CORDIC in an FPGA: either a state machine-based approach or a pipelined approach. If the processing time is not critical, implement the algorithm as a state machine that computes one CORDIC iteration per cycle until the desired number of cycles has been completed. If you require a high calculation speed, then a parallel architecture is more appropriate. The code above implements a 15stage parallel CORDIC operating within the rotation mode. It uses a simple lookup table of ArcTan(2-i) as demonstrated in Table 2 for a circular configuration, coupled with a simple array structure to implement the parallel stages. In all of these ways, the CORDIC algorithm proves its merit as a simple but powerful algorithm that all FPGA designers should be aware of. Even better, you can implement the CORDIC very simply using either core-generation tools or hand coding.
Versatile FPGA Platform PCI Express 4x Short Card Xilinx Virtex Families I/0 enabled through an FMC site (VITA 57) Development kit and drivers optimized for Windows and Linux
Opt
ical
-Me z
The Versatile FPGA Platform provides a cost-effective way of undertaking intensive calculations and high speed communications in an industrial environment. Second Quarter 2012
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