EVP6472 Embedded MultiCore Solution Easy development platform for Dual ‘TI C6472 DSPs C6472
C6472
Multicore DSP
Multicore DSP
Sundance Multiprocessor Technology
Outlines
TMS320C6472 MultiCore DSP Diamond software architecture for MultiCore DSP Model-based design concept for DSP + FPGA ‘C’-based design concept for FPGA EVP6472 Evaluation Platform • Technical Overview • Prices
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TMS320C6472 Six ‘C64x+ DSP Cores in one chip 9 The best power performance multicore DSP in industry with 3 GHz performance at 6.5 MMAC/mW 9 Highest performance DSP from TI with up to 4.2 GHz/33600 MMACs and 4.8 MB onchip L1/L2 RAM 9 Optimized DSP architecture to maximize subsystem performance on a chip
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Computer architecture Design flow strategy and methodology Electronic System Level tools PARS, System Generator, HDL coder, Impulse C, IP cores...
3L Diamond DSP
3L Diamond FPGA
Code Composer Studio
XILINX ISE
Compiler & Linker
Synthesis, Implementation and PAR
DSP Tasks
FPGA Tasks
Platform abstraction and communication links
Network of heterogeneous processor devices DSPs, FPGAs, PowerPC, Host processor...
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3L Diamond Development System Multi-DSP RTOS and FPGA task-based co-design tool What is 3L Diamond for Sundance? Multiprocessor devices co-design tool optimised for the Sundance hardware Designed for multiprocessor systems, simplicity and efficiency •
During development and execution
Reduce the application development time and integration burden • • • •
Automatically invoke Xilinx ISE to build hardware tasks Automatically call Texas Instruments Code Composer to compile software tasks Automatically creates one single application Automatically configure your network of processor devices
Key features: • • • • •
Interactive development environment Support for DSP, FPGA, Embedded PowerPC cores… Real-time operating system for DSP processors Design structure for reusable FPGA IP cores Leverage system complexity and reduce time-to-market
www.3L.com/IDE/IDE%20Demo.htm
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Six Processor Cores Six Processor Cores
Twelve C64x+ DSP Cores: Interconnection Channels: A 3L Diamond Multicore application: Software Tasks to execute: a Diamond task
Diamond processor
a Diamond channel
A complex 3L Diamond Multicore application ... in just one file!
3L Diamond IDE Integrated development environment framework
Describe the application only, everything else is automatically done.
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Impulse CoDeveloper for 3L Diamond Electronic system level (ESL) design tool What is Impulse C? Development tool for FPGA-accelerated computing C-programming language to FPGA design approach Hardware Acceleration for High-Performance Systems • •
For embedded digital signal processing systems For high-performance computing
Key features: • • • • • •
Design of FPGA devices Made for dataflow-oriented applications Software-to-hardware compiler Interactive parallel optimizer Increase code execution performance from 10x up to 30x Platform support package for the Sundance hardware
http://www.impulsec.com/app_web_training.htm
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PARS Model-based design Parallel application from rapid simulation Simulink design environment
PARS pluggin
Target hardware Multi-DSP and FPGA applications from Simulink速 Hardware-in-the-loop testing for real-time simulations
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PARS Model-based design Why is PARS efficient and how does it work? Build a model with MATLAB Simulink® Verify and simulate the Simulink model created Use PARS to partition the model into: • • •
DSP Tasks FPGA Tasks HOST Tasks
PARS creates a 3L Diamond project (Diamond generates a single application) The test vectors are generated from the Simulink testbench model The application is loaded and runs on the Sundance hardware The simulation model is executed on the real hardware system The test results are sent back to Simulink for data analysis Hardware-in-the-loop testing is the most efficient technique for: • • •
Rapid simulation Efficient proof of concept for algorithm Fast prototyping system
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PARS Model-based design Design environment from MATLAB Simulink速
http://www.youtube.com/user/SundanceDSPVideos
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EVP6472 Dual ‘C6472 DSPs,Virtex-5 FX30 FPGA, USB2.0, 109 LVDS I/O pins
EVP6472 is a stand-alone platform for experimenting with algorithms for high-speed signal processing for various applications.
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EVP6472 Dual ‘C6472 DSPs,Virtex-5 FX30 FPGA, USB2.0, 109 LVDS I/O pins
EVP6472 is a stand-alone platform for experimenting with algorithms for high-speed signal processing for various applications.
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SMT372T Dual ‘C6472 DSPs,Virtex-5 FX30 FPGA, 109 LVDS I/O pins, TIM Module
SMT372T is the Module that EVP6472 is based on and can be used for OEM customers as a components
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SMT372T Dual ‘C6472 DSPs,Virtex-5 FX30 FPGA, 109 LVDS I/O pins, TIM Module
SMT372T is the heart of the Evaluation Platform for TI’s TMS320C6472 DSP and can be used on a range of carriers, from PCI104 to Compact PCI.
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www.EVP6472.com Complete ‘C6472 Evaluation Platform – Shipping Dec. ‘09
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www.EVP6472.com Complete ‘C6472 Development System
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www.EVP6472.com Complete ‘C6472 Development System
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www.EVP6472.com Complete ‘C6472 Development System
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www.EVP6472.com Complete ‘C6472 Development System
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www.EVP6472.com Complete ‘C6472 Development System
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Thank you! Complete ‘C6472 Development by Sundance Flemming Christensen Managing Director Sundance Multiprocessor Technology www.sundance.com Contact details: Flemming.C@Sundance.com Cell/Mobile + 44 7850 911 417
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