Technology in
context OpenVPX
The Quest to Navigate the OpenVPX Standard: VITA 65 OpenVPX offers huge potential for performance, ruggedness and I/O in a wide variety of system configurations. Navigating through the specification can be intimidating at first, but once the terms have been recognized and the map laid out, the path to truly functional system topologies will open before us. by Ken Grob, Elma Electronic
OpenVPX - the Standard
M
uch has been written recently about the new OpenVPX standard known as VITA 65. This article provides an introduction to the structure of the specification. In order to define a system, it’s important to understand how to properly navigate through and decipher the different sections of the specification and its lexicon. Part two, a follow-on article scheduled for the November issue, will discuss how VITA 65 enables a user to build OpenVPX systems by combining slot and backplane profiles that support the establishment of an end system topology. The OpenVPX standard has been brought to fruition through an intense effort driven first outside, then subsequently within the OpenVPX VITA Working Group. In a few months, a short list of companies and a team of dedicated industry veterans have brought us a 400+ page document that provides concepts and
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came to fostering interoperability among offerings from different manufacturers of VPX boards and backplanes. So off on a quest went these VPX Knights—a new standard they sought, to alleviate these plights. Contending with MultiGig-2 wafer-based connectors good for data rates up to 10 Gbit/s and new backplane materials, including FR408 and Nelco 4000-13SI, OpenVPX is taking us to new data transfer rates where we have not gone before (Figure 1). SerDes-based physical interfaces supporting baud rates of 3.125, 5.0 and 6.25 Gbit/s are now common within the OpenVPX Module and Backplane lexicon. OpenVPX has generated a well structured specification volume, which at first glance would send Don Quixote back to the windmill. Introducing a new set of terms for describing lane-based point-to-point interconnects, the document quickly grew large driven by the unique topology required of each backplane described, and using equation-based formulas that specify Slot, Module and Backplane profiles.
Figure 1 VPX wafer-based connectors fitting into backplane sockets.
methods to describe system topologies using a new breed of serial fabric technologies and high-speed backplanes. As discussed in recent articles, OpenVPX is based on prior VITA standards that initially addressed VPX, including VITA 46.0 and VITA 46.1. These standards formed a good base to allow the design and implementation of new high-speed, highpower systems, but they fell short when it
The standard was created to allow for definition of system topologies and to promote interoperability. The specification is divided into 16 sections. Section One covers structure and defines terminology. Key Words are defined. The concepts of Profile Names are introduced and are summarized in Figure 2. Slot (SLT) in Types: Payload (PAY), Peripheral (PER), Switch (SWH) and Storage (STO). Module (MOD): Same Attributes as Slot but specific to the module (board) and defines the protocol associated with the ports. Backplane (BKP) in Types: CEN, DIS, HYB, BRG, where: • Central (Star) • Distributed (Mesh) • Hybrid (VME & VPX) • BRG (Bridge, e.g., parallel VME to VPX) Naming conventions for profiles are described to allow a user to create a name