The magazine of record for the embedded computing

Page 32

SYSTEM Integration

the background to accomplish this type of low-level FPGA design. Automated “C-to-gates� flows have emerged as a possible solution. These flows are software centric and allow performance bottlenecks, identified through profiling, to be mapped to the FPGA fabric using a pushbutton approach. Modest performance gains are achievable but the hardware results tend to be more suitable for prototyping than for production hardware. An alternative approach would be to use a domain-specific development environment with FPGA-optimized IP. Such environments exist today for DSP applications that enable the use of The Mathworks DSP-friendly Simulink / Matlab modeling environments for FPGA development (Figure 5). Vendor-optimized libraries are provided for use within Simulink that include up to 100 DSP building blocks. Creating the design within Simulink allows these blocks to be abstractly connected and verified within the context of a DSP simulation.

Integration now exists to allow DSP development environments to automatically convert designs into custom peripherals for a corresponding embedded development environment. Integration includes the ability to automatically generate the hardware interface and software driver files and can often save weeks of development time (Figure 6). It is the combination of FPGA-optimized IP tightly integrated into a domain-specific development environment that enables developers with programming backgrounds to leverage the flexibility of an FPGA-based hardware system for their applications. These development environments are able to abstract away low-level implementation details of the interconnects and present the IP as abstract system building blocks in an appropriate context. Embedded development environments present a bus-centric view of the system—including masters, slaves and peripherals—which makes sense for em-

bedded development, while DSP development environments present a dataflow view of the system that includes fixedpoint bit growth and key DSP operations such as filtering or transforms, which is intuitive for DSP development. Integration between these two environments makes including a hardware-accelerated customer function for DSP a straightforward process. Because the IP supporting these environments is optimized for the target FPGA, production quality results are achievable, and the performance, cost and power benefits of the FPGA are fully realizable. Xilinx San Jose, CA. (408) 559-7778. [www.xilinx.com].

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1 32Untitled-2 January 2008

WHEN YOU NEED DATA ACQUISITION, THINK DIAMOND.

1/3/08 4:18:46 PM


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