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DDR4 is expected to deliver significantly higher performance, via faster data transfer rates reaching at least 3200 MT/s over time. In addition, the new specification introduces a number of enhancements used to improve both power efficiency and reliability. These features can add significant verification complexities for system designers, firmware developers and software designers. As one would expect, engineers are expected to march through the natural progression of the technology validation including signal integrity, timing analysis and specification compliance, performance tuning and power management modeling. This article explores methods to verify initial design and compliance with the new DDR4 JEDEC specifications along with techniques used to take advantage of DDR4 features and maximize system performance. While there are many potential instruments that can be used, a new generation of dedicated DDR bus analyzers now provide comprehensive timing and protocol analysis, making them an important tool for accelerating DDR4 system validation and design. Substantially lower in cost than a logic analyzer, these systems can be used to qualify different memory DIMM components, as well as help sustain engineering groups as they verify system operations over the entire product life cycle.
DDR4 Technical Overview Table 1 provides a brief comparison between DDR4 and DDR3 memory technology. DDR4, initially targeted for the server market, adopts a number of enhancements intended to deliver better performance, power-savings, and RAS (reliability, accessibility and serviceability) versus DDR3. These enhancements present unique and significant performance improvement and power reduction opportunities. Special attention must be taken when setting DDR4 power savings parameters so that suitable performance levels are still achieved.
DDR4’s new memory interface employs “pseudo-opendrain� (POD) termination where memory cells can store a logical 1 without consuming power. POD relies on switchable, on-die termination instead of a separate resistor pull up. Parallel-terminating the receiver at the far end means the DDR4 DIMM only consumes power when the Vdd rail is pulled low to represent logical zero. The anticipated higher transfer rates in DDR4 mandate tighter timing margins to support normal variations in memory DIMMs. DDR4 also offers programmable Command-to-Address Latency that can be used to improve system power efficiency. Expanded role of MRS and the introduction of bank groups make memory controller designs more complex. These factors are expected to drive changes in memory controller designs and associated IP in order to support DDR4. Data transfer rates for DDR4 and DDR3 should overlap for the foreseeable future, with DDR4 delivering a longer performance runway. It is quite conceivable for a DDR4 platform to deliver moderate power savings versus a comparable DDR3 design, but potentially at the expense of lower memory bandwidth under certain DDR4 operating parameters. System designers need to design highly tuned, balanced platforms that leverage the power saving and RAS enhancements of DDR4.
Managing DDR4 JEDEC Specifications The JEDEC specification targets specific timings for DDR4 memory controllers and their associated DRAMs. The majority of these are described as minimums, along with a minimum time before subsequent events are allowed. One of the primary JEDEC specification objectives is to avoid memory collisions caused by overlapping commands. Memory controllers and DRAMs therefore must be designed and tested for adherence to the JEDEC specifications across process, voltage, and temperature
Table 1: DDR4 vs. DDR3 key enhancements
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