TECH COLUMN
SUMMARY
4a.
4b.
FIGURE 4: (a) Efficiency and (b) thermal comparison for conventional and proposed parallel GaN device designs (VIN=48 V, VOUT=12 V, fsw=300 kHz, L=3.3 uH, eGaN FETs: 100 V EPC2001).
By offering lower individual parasitics and better parasitic balance, the distributed four high frequency loop design has more effective paralleling. This results in better electrical and thermal performance as shown in figure 4. The distributed high frequency loop design offers a 0.2% gain in efficiency at 40 A, shown in figure 4a, and has an almost constant 10째C improvement in the maximum transistor temperature, as shown in the thermal comparison graph shown in figure 4b.
The introduction of high performance GaN devices offers the potential to switch at higher frequencies and efficiency than possible with traditional Si MOSFET technology. This column evaluated the ability to parallel eGaN FETs for higher output current applications by addressing the challenges facing paralleling high speed, low parasitic devices, and demonstrated an improved paralleling technique. For experimental verification of this design method, four parallel half bridges in an optimized layout were operated as a 48 V to 12 V, 480 W, 300 kHz, 40 A buck converter, and achieved efficiencies above 96.5%, from 35% to 100% load. The design method achieved superior electrical and thermal performance compared to conventional paralleling methods and demonstrated that high speed GaN devices can be effectively paralleled for higher current operation. REFERENCES [1] A. Lidow. (2013, August 1). How to GaN: Driving eGaN FETs and Layout Considerations. EEWeb [Online]. Available: http://www.eeweb.com/blog/ alex_lidow/how-to-gan-driving-egan-fetsand-layout-considerations
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