CONTENTS
Modern Printed Circuits
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TECH ARTICLE
Critical Design Steps for A Third Design Choice LED PCBs Fig. 1
Whatever laminate is used, PTFE or otherwise, the copper remaining after etch must be cleaned or automated optical inspection to detect trace shorts or opens will be unreliable and soldermask will not stick. The best way to clean the copper is an abrasive scrub. However, all the suppliers of PTFEbased laminates advise that the laminate surface fresh from copper etch is best for adhesion and is compromised by scrubbing. There are alternative cleaning methods, though none are as satisfactory as scrubbing to support AOI of the copper and soldermask adhesion. Consequently, the copper is scrubbed before inspection. A plasma process is used after the scrubbing to reinvigorate the exposed laminate, to return the “tooth” to the surface so that soldermask will adhere, if it is an outside layer, or to aid subsequent lamination. However, the plasma oxidizes the copper, so it must be cleaned again if soldermask is to be applied. To avoid compromising the PTFE laminate surface by another scrubbing, a chemical clean for the copper follows in lieu of scrubbing, in preparation for soldermask. The panel must be dried immediately to eliminate moisture that could stain the copper and thereby inhibit soldermask adhesion. The process is a balancing act. Sometimes it does not work and the soldermask has to be stripped, the panel cleaned again and dried, and the soldermask reapplied. Instead of the standard practice of covering a board in soldermask (leaving openings for pads and so forth) rf and microwave designers commonly soldermask only the circuitry (except for the pads,etc) leaving the PTFE laminate surface open. The copper can be scrubbed, AOI can be performed successfully, the soldermask is applied to the copper where it sticks, and there is no need to worry about it on the laminate because it develops off. Another common approach is to restrict the deposit of soldermask to little dams next to pads, which limit solder from traveling down the traces (Figure 1). This approach may be easy to implement for simple circuits, but tedious if thousands of dams are required (Figure 2).
TECH ARTICLE
The need for scrubbing or chemical cleaning of the copper can be avoided altogether, and therefore the need to plasma treat the surface of the PTFE dielectric if a lamination will follow, if gold is plated over the copper before etch. The gold does not oxidize, remaining bright after etch, so does not require cleaning to be ready for AOI. Furthermore, a full soldermask with conventional solder openings can adhere to the board. Of course, gold is expensive, but one (or more) cleaning processes and a plasma process are eliminated. There is with gold the issue of copper migration to consider as well. Over time, copper and gold tend to diffuse into each other, the copper brought to the surface oxidizes, and contact resistance increases as a result of the oxidation. Higher temperatures accelerate the process. Nickel ordinarily is used as a barrier layer between copper and gold to prevent diffusion, however nickel cannot be used for rf and microwave circuits. At rf and microwave frequencies, the skin effect predominates in conductors: Most of the current flows in the outside of traces. Nickel is a lossy metal compared to copper especially at high frequencies, and the skin effect would tend to concentrate much of the current through the nickel near the trace surface. Copper diffusion into gold really is not a problem, unless the fabricated boards are kept in inventory a long time before assembly. Once components are soldered to their goldplated contacts, there is no worry about contact deterioration. Regarding the cost of gold, the plating amounts to a few microns thick. If there’s a plane on one side of the board, that would involve slightly more expense (more gold) than a signal layer, of course. Yet, there are fewer process steps with full-body plated gold. The copper is simply plated and then etched, with the gold as an etch resist, leaving the final metal surface finish. Yield ultimately governs the cost of fabrication.
If panels must be reprocessed because soldermask fails to adhere to blemished board traces, or worse if panels must be scrapped, cost accrues. For prototypes that are manufactured according to a flat price, that may not matter to designers. But as far as production quantities go, that is a different story.
Fig. 2
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Design Choices for Soldermask on Microwave PCBs Soldermask dams surround pads on this microwave board, which was designed using Altium tools.
COVER INTERVIEW
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This screen shot from the fab Genesis CAM tool reveals one of the soldermask dams. Biography Atar Mittal directs the design and assembly divisions of Sierra Circuits, a manufacturer of printed circuit boards in Sunnyvale, CA. He is responsible for the development of strategies and process automation tools for the fabrication and assembly of complex PCBs. Prior to Sierra Circuits, he held senior executive positions in R&D and technical marketing at computer hardware and software services companies in the United States and India. He holds a B.Tech. degree in Electrical Engineering from IIT Kharagpur (India), and a MS degree from CSU.
Hemant Shah: Dir. of Product Management of Allegro PCB Products at Cadence
COVER INTERVIEW Model
20 PCB Potential Gradie Josh Moore: Dir. of Product Marketing for OrCAD Solutions at Cadence
Using26SPICE
CIRCUIT PROJECT
Model PCB Potential Gradients Using SPICE
By David Cuthbert
EEWeb Contributing Author
In this article you’ll learn several techniques to control PCB Plane Po Gradients and you’ll learn how to simulate these techniques with You can then design successful low-level signal layouts on the first
PCB traces and planes offer electrical resistance to electrical c resulting in potential gradients and signal corruption. Voltage gra are especially important in low level analog circuitry—such as Ana Digital converters—where measurement accuracy can be compromi a potential gradient of just a few microvolts.
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