Issue 68 October 16, 2012
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INTERVIEW EEWeb.com
Alan Kraemer CTO SRS Labs
Electrical Engineering Community Visit www.eeweb.com
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TABLE OF CONTENTS
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Alan Kraemer SRS LABS Interview with Alan Kraemer - Chief Technology Officer
Featured Products
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Efficient Shifting, Rotating and Normalizing Structures
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BY RAY ANDRAKA WITH ANDRAKA CONSULTING How utilizing merged trees improves performance in signal processing and reduces routing congestion, which means using fewer resources.
The Highs and Lows of Resistance Measurements: Part 2
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BY JONATHAN TUCKER WITH KEITHLEY An illustration of the difference in accuracy that a four-wire connection method provides over the two-wire method.
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RTZ - Return to Zero Comic
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Alan
Krae
SRS La
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EEWeb | Electrical Engineering Community
INTERVIEW
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emer
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SRS Labs is a provider of state-of-the-art audio technology and is dedicated to making digital entertainment exciting, engaging and effortless for the user. We spoke with Alan Kraemer, the Chief Technology Officer, about his passion for music and audio technology, why the state of audio hasn’t changed in 75 years, and what SRS Labs is doing to change that.
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EEWeb PULSE Tell us a little about yourself. What first interested you in audio? I’ve been interested in audio since I was about three years old. I had a real attraction to audio and music technology. I started to play piano when I was around seven or eight and studied music in school and continue to compose and play to this day. On the other side, I had a parallel interest in technology—I was designing things when I was ten years old like rotary dial systems for my house, illegal FM transmitters and tube amplifiers. I studied fine arts for awhile and then my career took another diversion and ended up spending 20 years managing computer architects and design groups at various companies, including AST Computers and Northrup Electronics, which was good in relation to the kind of work I am doing now, especially with Multi-Dimensional Audio (MDA), which is partially data processing. I continued to do a lot of classical music recordings with members of the L.A. Chamber Orchestra and the L.A. Master Choral and local groups around Orange County and sort of went full time on that for awhile—producing jazz and classical CDs. I had known Tom Yuen—who is our CEO—from AST Research Computers, where I was the Executive Vice President of Engineering and we were looking for the next thing to do in the early 90s when we discovered SRS. I was excited because it was the perfect blend of technology and my other love, which is audio and music and I’ve been there ever since. 18 years!
Retrieval System that was created by Arnold Klayman, which was bought from Arnold by Hughes Aircraft. Essentially, Arnold was an inveterate inventor and audiophile as well and was wondering why stereo audio reproduction didn’t sound like the real thing; the casual listener could walk into a room and say, “That’s a stereo system playing” versus “That’s a band playing”. Arnold did some of the early, seminal research into psychoacoustics and created SRS—basically retrieving cues from stereo recordings and rendering them to be more spatially accurate. You can take the basic engineering approach to audio and do harmonic distortion, modulation distortion and crossover distortion, but if you look at just a traditional two-channel stereo system, you have 100% spatial distortion. Arnold’s goal was to use the principles of psychoacoustics to reduce some of that spatial distortion, because we don’t listen to real sounds coming out of two speakers in front of us. That was the origin of SRS. In 1993, they shouldn’t be in the audio business, they should be in the aerospace business. So SRS was spun out to a group of private investors, and Tom
Yuen came around six months later with a second round of financing and he and I have been here ever since.
“The impetus for [our NViro technology] came from looking at the state of audio and realizing that it hasn’t changed for 75 years. It also came from my experiences sitting in movie theaters and realizing that the sound was grossly inadequate. We can do better than that!”
What kind of technology and services did SRS offer and how has it evolved? 18 years ago, SRS basically offered SRS, which stood for the Sound
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IWow Family
INTERVIEW
Audio Rendering Lab Are you an IP licensing company? Yes. Since 1993, we’ve developed a very large portfolio of audio signal processing and voice signal processing technology that we offer to the consumer electronics industry. Our biggest customer, for example, is Samsung and we also have Sharp TV and HP. We license to about four or five different segments, being home entertainment, PC, automotive and mobile devices. Basically anything that makes a sound. How would you segment the type of IPs you offer? How do you distinguish between one type of IP and another? In my mind, there are two categories of audio signal processing IP. One is experience improvement, which would comprise rendering surround sound. We have a new technology
called NViro, where we actually project depth into the room and you get a sense of proximity in the sound field. To broaden that even further, we have our TruVolume technology, which uses perceptual cues to create the perception of constant volume, especially for TV broadcasting, when you have commercials coming in in all kinds of crazy levels and it maintains that perceived level. The other category is our TruBass technology, which is a pyschoacoustic bass enhancement that, yes, improves the user experience, but also overcomes physical device limitations like small speakers in portable devices and ever-diminishing speakers in flat-panel TVs. We also have our Focus technology, which can create a sense that the sound is coming from not just the point sources of the device, but from a sound field. These are the classes of technology
that overcome limitations of the devices and they are becoming more and more important as the devices become more and more limited from an audio standpoint. How do you identify the next kind of product to begin developing or what consumers are looking for? We kind of tell the consumers what they are looking for. Basically, we are thinking about audio all the time, for example, our depth rendering technology, we took a look at what we call “surround sound” today and determined that it was such a crude version of the ability to actually project depth and the proximity of the sound source to the listener. We studied that and wondered how we can create a more immersive sound field or create the ability for the listener to perceive proximity. That’s Visit www.eeweb.com
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“If you look at the NViro technology and the depth rendering and immersive sound field, we have realtime processes that can do analysis of that sound field and try to determine where we think objects are within it.”
Alan Kraemer speaking at AM just not done with surround sound— everything is through the speakers. We started to research on our NViro technology on that basis, basically listening to our customers, but also looking at the current state of the art of audio and determining where the gaps are. We also did that with our MDA effort, which is a whole new campaign to change audio from a channel-based world to an objectbased world so that the number of channels and the number of speakers becomes purely arbitrary and that the audio objects are mixed into 3D space and mapped to the playback sources available on a dynamic basis. The impetus for that came from looking at the state of audio and realizing that it hasn’t changed for 75 years. It also came from my experiences sitting in movie theaters and realizing that the sound was grossly inadequate. We can do better than that!
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Tell us a little about your team at SRS. Does everybody share your passion for audio? Absolutely. Most of our guys, especially our younger guys, have an audio background and are also musicians. Our company is about 130 people scattered around the world, but mostly concentrated in Orange County, California. I think around 55 of those people are engineers, so it is a heavily technology-concentrated company. These are people that don’t just sit around writing code, but people that really understand audio and have the ability to really hear. A lot of companies in the 90s failed to do the things that we do based on what was understood as the math. The models we have of the hearing system are so grossly inadequate and don’t have full coverage of the how the hearing system actually
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works. You can have the theory, but at the end of the day, you need to sit down and actually listen and determining whether or not it is the audio experience you are trying to get. The hearing system is so subtle and complex that it can’t be fully described by any current theory, so we need and pursue people that have a passion for audio and sound. What are the challenges you face in getting consumer electronics companies or recording studios to embrace this MDA technology? It turns out there is high consciousness about this technology right now. Audio is going to have to go to object-based configuration. What we are doing is proposing the language of MDA as an open standard, which is very attractive to the studios, as opposed to a lock
INTERVIEW In regards to IP that you provide, do you help designers implement ICs?
MD Fusion 2012 down proprietary sort of thing. The important thing about MDA is that it’s not an audio codec, it’s a language that expresses information about audio in 3-dimensional space. The codec becomes an arbitrary choice based on the capabilities of the transmission and storage medium. Can you take a traditional track in speaker configuration and approximate the model? Yes. If you look at the NViro technology and the depth rendering and immersive sound field, we have real-time processes that can do analysis of that sound field and try to determine where we think objects are within it. That’s the first step. Once we get the explicit object information, we can do much more. It’s really doesn’t sound like anything you have heard before.
When we first started out, our IP was all embodied in analog circuitry. We helped designers implement the analog ICs based on op amp designs. As the DSPs became more commonplace and more prevalent in the late 90s, we rapidly transitioned to digital technology. We do all of our algorithm prototyping in things like MATLAB and we translate that to reference c-code, which is ported to the various processing platforms needed for the application.
completely controlled by software— there’s no physical patching that goes on. This allows us to switch from one configuration to another in milliseconds. We can compare psychoacoustic rendering to physical rendering almost instantly. Basically, any idea we can think of, we can go back to the ARL and try it.
What kind of lab environment do you have for testing? We have a number of different listening rooms. The biggest one that we have is called an Advanced Rendering Lab (ARL), which is about 60 feet by 35 feet. We are currently hanging a 22.2 speaker system in there that we are actually going to move up to 30.2. It’s all
For more information about SRS Labs, visit their website:
www.srslabs.com
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Efficient Shifting, Rotating and Normalization Structures Ray Andraka Andraka Consulting Group, Inc - President
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TECH ARTICLE
Signal processing and communications algorithms frequently make use of dynamic bit rotates or shifts. Utilizing merged trees improves performance and reduces routing congestion using fewer resources. Embedded features provide additional options for efficient structures.
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EFFICIENT SHIFTING, ROTATING NORMALIZATION STRUCTURES
AND
In signal processing applications, we frequently encounter situations where data must be either shifted or rotated by a variable number of bit positions. A rotator wraps bits shifted off one end back around to the other end, while a shifter discards bits shifted off one and, and zero fills (or copies sign) bits shifted in the other end. Shifters are used extensively in floating point applications for normalization and de-normalization, and for range reduction in fixed point applications. Rotators are found in communications framers, encryption, and other places where bits need to be realigned to a reference. The natural tendency for a designer is to use n N:1 selectors (aka multiplexers) as shown in Figure 1 to implement a shifter or rotator. Each multiplexer has to 0
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For illustration purposes, the rotator in Figure 1 has only four shift positions, which will translate to a single layer of logic in most modern FPGAs (or at worst two layers of logic). However, a real-world rotator is usually wider and will have as many shift positions as there are bits in the output. In that case, the size of the multiplexer grows to the point where it has to be constructed out of several FPGA logic cells, using two or more layers of logic (or has to use slower wide AND-OR logic that augments the logic cells in the FPGA fabric in some devices). The speed of the design slows as the number of shift positions increases due to increased routing congestion, increased fan-in and increased number of logic cells traversed by the signal. MERGED TREE SHIFTER
0 Data Out 3 2 1 1 0 3 2 0 1 0
Shift Left by
Figure 1 Rotator implemented with multiplexers. Red dashed connections are replaced with ‘0’ for shifter.
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be mapped into FPGA logic, which typically consists of small (3 to 6 input) look up tables (LUTs) with specialty logic (e.g. carry chains) surrounding them and optionally feeding a flip-flop. A 4 input-LUT can handle a maximum of a 2 input selector with non-constant inputs. An n input shifter built in this manner requires n(n-1) 2-input selectors to construct the n multiplexers. The number of 2:1 selectors the signal passes through on its way to the output is Log2n. It is also worth noting that all of the input bits connect to the selector trees for all of the output bits (except inputs that are constants in the case of a shifter), which congests the routing at the input and contributes to a high signal fan-in (fan-in is the number of loads on the signal). Both the routing congestion and the high fan-in will tend to degrade the maximum clock performance.
Examination of a shifter built up of decomposed larger multiplexers reveals an opportunity for significant hardware savings that was hidden by considering the multiplexer a black box. For example, consider the decomposition of the 8:1 multiplexers of an 8 position rotator shown in Figure 2 into three layers of 2:1 multiplexers. Each term that is shared rather than duplicated not only eliminates the duplicated logic at that level, but also prunes that entire branch off the tree, sharing an identical branch instead. A careful analysis of the tree reveals there are only as many unique branches as there are bits in the output, and that each bit output at each layer drives exactly two inputs, thus eliminating the high fan-in of the original design. You may also notice that the assembly of multiplexers in any particular layer selects between no shift and a fixed shift by a power of 2 bit positions that depends on the layer in the merged tree. The resulting rotator or shifter circuit is redrawn in Figure 3.
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TECH ARTICLE
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Figure 2 Decomposition of an 8 position rotator into 2:1 multiplexers reveals redundant terms (shaded blue). Only the portion of the decomposed tree leading to the upper 3 output bits is shown.
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Shift by Figure 3 Merged Tree Shifter
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Using optimal merged trees like this significantly reduces the shifter complexity, especially in larger shifters. Another way to look at it is the optimal merged tree shifter decomposes the shifting to a sequence of shifts performing a partial shift at each layer in the design. The shift distance at each layer is β x bits, where ...is the number of inputs to the multiplexer and x is the β index for the layer. Using 2 input multiplexers, the circuit complexity is nlog2n instead of the n(n-1) complexity of a shifter composed of n:1 multiplexers. The delay through the circuit remains log2n. The routing density is still about the same as the brute-force design, but now the routing is spread out over the layers instead of being concentrated at the input layer. That makes this easier to route and easier to pipeline for higher clock rates.
two between 20 and 216 to one input and a data word up to 18 bits (signed) to the other. The most significant bit on the multiplier inputs has a weight of -217 (because it is a signed multiplier) so if a 17 bit shift is required the sign of the result has to be corrected. One thing to note here is that the shift control is a one-hot code rather than the binary control word typically associated with a shifter, so a decoder may be needed to produce the correct shift controls. Larger shifters can be built either with several multipliers assembled into a larger multiplier using the multiplication by parts technique used in long-hand multiplication, or by combining a multiplier with a merged tree shifter where the multiplier does the fine shift of 0 to 16 bits and the merged tree shifter does the coarse part of the shift.
The circuit shown in Figure 3 is the implementation for 2 input multiplexers. In cases where the FPGA fabric handles a 4 input multiplexer in one level of logic, a similar circuit using 4 input multiplexers at each layer can be constructed. In this case, each layer shifts by 0,1,2 or 3 times a power of 4, and each output connects to 4 inputs on the next layer. Depending on the FPGA structure, a shifter built from 4 input multiplexers may yield a slightly more compact design, but often at the cost of lowered performance.
MERGED TREE NORMALIZER
The ordering of the shifts in the merged tree is not important. This gives us the opportunity to interleave large and small shifts in order to help ease the routing congestion. For example, the circuit depicted in Figure 3 has longer vertical routes on the right side. Those routes overlap since they all travel a distance of 8 bits. On the left side the two loads are adjacent bits, so the interconnect is local and there is little congestion. If we rearrange the order of the shifts to 1 8 2 4, then the more congested vertical channels are all adjacent to less congested ones, so the routing can spill over, resulting in a more routable and often faster solution. SHIFTERS USING EMBEDDED MULTIPLIERS The inclusion of low latency embedded multipliers in FPGAs offers another option for shifting data by variable amounts. In this case, one input of the multiplier is the data to be shifted; the other is a power of 2 value, where the exponent is the number of bit positions to shift left. Shifts to the right can be obtained by bit-reversing the control multiplicand (which converts the exponent, n to const-n)and dropping least significant bits off the product. A typical embedded multiplier is an 18×18 signed multiplier. With that, you can accomplish a 0-16 bit shift with a single multiplier by applying a power of
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Normalization is a common function in signal processing applications, particularly for floating point operations and for range reduction when computing difficult functions. Normalization generally consists of left shifting the data until the most significant ‘1’ bit in the word lands in the left most position. Normally, in order to do this you need to first know how many leading zero bits there are in the word, and then you must encode that into the correct format for the shift control (which is an unsigned binary word in the case of the merged tree shifter). One solution is to use a “priority encoder” which does exactly that. That approach adds latency to the design because the shift distance generally must be computed using the input data before the data can be actually shifted, which requires either pipeline registers added to the shifter input to match the delay of the priority encoder or a slow enough clock to allow the signal to propagate through the priority encoder. Typically, a normalizer needs to output the shift distance along with the data to provide scale. Often, the exponent is just the shift control word added to an offset. A normalizer made up of a priority encoder and merged tree shifter is shown in Figure 5. Data In
35x18 Signed Embedded Multiply
35
Shifted Data Out Shift by
Binary to one-hot decoder
<<17 2ˆshift
Figure 4 33 bit shifter using 35×18 multiplier and 0/17 bit shift. 17 bit shift is used to take advantage of 17 bit shift built into embedded DSP block.
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The merged tree shifter can be rearranged to do normalization without having to first compute how many bits to shift. To do this, we take advantage of the fact that the shift at each layer is a binary decision (either shift or don’t shift), and the fact that the ordering of the layers in a merged tree shifter is arbitrary. If the shift layers are ordered so that the largest shift comes first, then the shift decision at each stage is reduced to determining whether or not that shift operation will cause an overflow at that stage. An overflow will only occur if there is a significant bit in the top 2n bits before the shift by 2n. For unsigned data, if all of the top 2n bits are zero, then the data is shifted. Otherwise, the data is passed un-shifted to the next layer. The shift detection at each stage for unsigned data is then just the logical OR of the top 2n bits at the input to that stage, as shown in Figure 5. We have effectively decomposed the shift controls into a series of shift or don’t shift decisions matching the decomposition of the shift into power of two shifts.
TECH ARTICLE
with a handful of OR gates, and at the same time have arrived at an optimal normalizer architecture. Note also that if we leave the shifted output bits disconnected and prune the trees from the unused outputs back we arrive at an optimal merged tree implementation of a priority encoder. Two’s complement values can be normalized using this same technique. In that case, the shift is made if all the high bits match the sign bit instead of all being zero. The shift detection at the initial stages can sometimes be made faster by using the fast carry chain logic. Two’s complement is typically a little slower because more inputs feed into the decision. It is often better, smaller and faster to convert to sign-magnitude notation before doing the normalization.
About the Author
Raymond J. Andraka, P.E. earned a B.S.E.E. degree from Lehigh University, Bethlehem, PA, and an M.S.E.E. The sequence of the shift decisions forms a binary word degree from the University of Massachusetts, Lowell, indicating the total number of bit positions shifted. This in 1984 and 1992, respectively. He is the President of word can be directly interpreted as the change in the the Andraka Consulting Group, Inc., a digital hardware exponent due to normalization, thus this normalization design firm he founded in 1994. His company is focused circuit can also be used for fixed point to floating point exclusively on high-performance DSP designs using conversion by adding an appropriate offset to the FPGAs. He has applied FPGAs to signal processing shift value. By using a merged tree architecture for applications including radar processors, radar the shifter and paying attention to the overall goal, we environment simulators, sonar, Industrial ultrasound, have eliminated an ugly priority decode and replaced it HDTV, digital radio, spectrum analyzers, image processing, and communications test equipment. Ray’s prior signal 0 0 0 0 processor design experience Shifted Data In includes five years with Raytheon Data Out 1 1 1 1 <<1 <<2 <<4 <<8 Missile Systems designing radar signal processors and three years of signal detection and reconstruction algorithm development for the U.S. Shift by Priority ‘Exponent’ Air Force. He also spent two years Encoder Out developing image readers and Figure 5 Normalizer using priority encoder and merged tree shifter processors for G-Tech, where he set the company time-to-market record ‘Exponent’ for a new product. He also authored over 20 conference papers and articles dealing with various high8 msbs 4 msbs 2 msbs msb performance FPGA design and signal processing topics, and has been a 1 1 1 1 regular contributor to several on-line Normalized Data In forums dealing with FPGA and DSP Data Out design. 0 0 0 0 <<8 <<4 <<2 <<1 Figure 6 Merged tree normalizer eliminates the separate priority encode.
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The Hig Resista
Part 2 Can
You Jonathan Tucker
Senior Marketer and And Product Manage Tektronix/Keithley Instruments
22
EEWeb | Electrical Engineering Community
TECH ARTICLE
ghs and Lows of ance Measurements:
n You Trust ur Test?
er
Two-Wire Vs. Four-Wire Measurements
In the first part of this series on the highs and lows of resistance measurements, I discussed the basic principles for making two- and four-wire resistance measurements for measuring resistances of less than 100 ohms. The differences between the two techniques were also addressed. To illustrate the difference in accuracy the four-wire connection method provides over the two-wire method, I measured the resistance of a silver e-Ink sample (Figure 1) that could be used in making flexible printed circuit boards.
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Figure 1: Probing a printed circuit pad made from a silver e-Ink. (Photos courtesy of Keithley Instruments)
Figure 1 also illustrates how the sample was probed using coaxial-type probes made of solid tungsten wire, surrounded by a TeflonÂŽ insulator. The outer conductor or shield of the probe is gold-plated copper. Figure 2 is the equivalent circuit for the measurement of resistance on a surface material by using a two-point probe method. Two probes carry the test current and measure the voltage. Each probe has a probe resistance (RP), a probe contact resistance (RCP), and a spreading resistance (RSP) associated with it. Unfortunately, these parasitic resistances cannot be neglected because they are not only in series with the lead resistance but with the resistance (RS) to be measured.
The measured resistance is easy to calculate. The combination of the lead resistance with the probe resistance, contact resistance, and the spreading resistance across the two probes will result in a significant error if the total is greater than the resistance to be measured. Measured Resistance =
VM = RS+ [2 x (RLEAD +RP+RCP+RSP)] I
Figure 3: Eq. 1
The equivalent circuit for the measurement of a surface resistance by using the four-point probe method is shown in Figure 4. Letâ&#x20AC;&#x2122;s analyze this circuit.
DUT RLEAD
Rp1
Rcp1
Rsp1
Probe 1
I
VM
Rs RLEAD Rp2
Source/Measure Unit
Rcp2 Probe 2
Figure 2: Surface two-point probe measurement of resistance
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EEWeb | Electrical Engineering Community
Rsp2
I
TECH ARTICLE I
V
Rp1
Rp2
Rp3
Rp4
Rcp1
Rcp2
Rcp3
Rcp4
Rsp1
Rsp2
Rsp3
Rsp4
I=0
Rs
I Figure 4: (Above) Surface four-point probe measurement of resistance Figure 5: (Right) Model 4200-SCS parameter analyzer and Model 2400 SourceMeter® instrument
Two probes carry the current and the other two probes sense the voltage. Again, each probe has a probe resistance (RP), a probe contact resistance (RCP), and a spreading resistance (RSP) associated with it. However, these parasitic resistances can be neglected for the two voltage probes because the voltage is measured with a high impedance voltmeter, which draws very little current. Even the lead resistance, which is not shown, can also be neglected. Thus the voltage drops across these parasitic resistances are insignificantly small. The voltage reading from the voltmeter is approximately equal to the voltage drop across the sheet resistance. To carry out our measurement experiment, we used the Keithley 4200-SCS parameter analyzer. The experiment could also be carried out using one of Keithley’s Series 2400 or 2600A SourceMeter® instruments. These instruments are often used for research studies of organic electronics, printed electronics, semiconductor devices and nanotechnology-based systems that require I-V characterization. Visit www.eeweb.com
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We programmed the first SMU in the Model 4200-SCS (SMU1) in the definition page to sweep current from 0A to 1mA incrementing in 100 micro-amp steps, totaling 11 test points. SMU2 was programmed to measure voltage only and was set to auto-ranging as we were not initially sure what the measured voltage would be.
The sourced current and measured voltages across two of the SMUs are displayed in Table 1. SMU1Volts is the voltage measured using the two-point approach; SMU2Volts is the voltage measured using the fourpoint approach. Notice the differences in the measured voltages between the two columns.
The results of the test are shown in Figure 6, which compares the resistance as measured using the twopoint probe method with the resistance as measured with the four-point probe method. In this configuration, SMU1 was used for sourcing the current as well as measuring the voltage, indicative of a two-point probe measurement.
From this data, we can calculate the resistance. For this calculation, we chose to measure the delta voltage between the two current points of 900 micro-amps and 100 micro-amps. For the two-point measurement, the resulting resistance measurement is ~3.3 ohms. The same current test points are used for the fourpoint measurements, which produce a resistance
4.0E-3 1.1E-3 1.0E-3 900.0E-6
SMU1Volts
800.0E-6 700.0E-6
2.0E-3
600.0E-6
Data Variables 1 Data: SHRES = 5.37988
500.0E-6
1.0E-3
400.0E-6
SMU2Volts
300.0E-6
SMU2 Volts
SMU1 Volts
3.0E-3
200.0E-6
0.0E-3
100.0E-6 0.0E+0 1.0E-3
900.0E-6
800.0E-6
700.0E-6
600.0E-6
500.0E-6
400.0E-6
300.0E-6
200.0E-6
Fit1(Lin): y=a+bx a=47.48e-6 b=1.20 1/b=833.79e-3 xint=39.59e-6
-100.0E-6 100.0E-6
-1.0E-3
SMU1 Curr Figure 6: Two-wire vs. four-wire measurements
The trace indicated by “SMU1Volts” in the graph is the result from the two-point probe measurement. Note that this plot spans voltage measurements from approximately 0 volts to 3.3 millivolts. The trace indicated by “SMU2Volts” in the graph is the result from the fourpoint probe measurement. Notice the difference in the two plots, especially their slopes. These results are as should be anticipated, given that the two-point probe measurement also includes the resistances from the probes, leads, spreading, and contact resistance. Let’s review the numerical results to confirm the errors with the two-point probe approach versus the four-point probe approach and to obtain the values needed to calculate the resistance.
26
Smu1Curr
Smu1Volts Smu2Volts
000.0000E+0
-10.7986E-6
100.0000E-6
327.1888E-6
72.4560E-6
200.0000E-6
654.0748E-6
190.0227E-6
300.0000E-6
986.3097E-6
312.3849E-6
400.0000E-6
1.3099E-3
428.4137E-6
500.0000E-6
1.6413E-3
544.9526E-6
600.0000E-6
1.9737E-3
669.7575E-6
700.0000E-6
2.3035E-3
790.3785E-6
800.0000E-6
2.6299E-3
901.1007E-6
900.0000E-6
2.9664E-3
1.0319E-3
1.0000E-3
3.2921E-3
1.1459E-3
-48.9888E-6
Figure 7: Results from two- and four-point probe approaches to resistance measurements
EEWeb | Electrical Engineering Community
measurement of 1.2 ohms. The difference between the two values is clearly a result of the error resistances previously discussed. Thus, the amount of error is approximately 2.1 ohms. This is a significant amount compared to the actual resistance. The error masks the true value of the measured resistance in the two-point probe method. In addition to lead resistances, thermoelectric voltage offsets can seriously affect low resistance measurement accuracy. The current-reversal method, the delta method, and the offset-compensated ohms method are three common ways to overcome these unwanted offsets. CURRENT-REVERSAL METHOD Thermoelectric EMFs can be canceled by making two measurements with currents of opposite polarity, as shown in Figure 8. In this diagram, a voltmeter with a separate bipolar current source is used. Voltage measurements are taken first with a positive current and then with the current polarity reversed. The two measurements can be combined to cancel thermoelectric EMFs. Note that the thermoelectric voltage (VEMF) is completely canceled out by this method of resistance calculation. However, for the current-
TECH ARTICLE
reversal method to be effective, it’s important to use a low noise voltmeter with a response speed that is fast compared with the thermal time constant of the circuit under test. If the response speed is too slow, any changes in the circuit temperature during the measurement cycle will cause changes in the thermoelectric EMFs that won’t be completely canceled, and some error will result. DELTA METHOD When the thermoelectric voltages are constant with respect to the measurement cycle, the current-reversal method will compensate for these offsets successfully. However, if changing thermoelectric voltages are causing inaccurate results, then the delta method should be used. The delta method is similar to the current-reversal method in terms of alternating the polarity of the current source, but it differs in that it uses three voltage measurements to make each resistance calculation. This method can best be explained through an illustration and mathematical computations. Figure 10 shows the voltage drop of a DUT as a function of time with an alternating polarity current applied. A voltage measurement (VM1, VM2, VM3, etc.) is taken each time the polarity is changed. Each voltage measurement includes a constant thermal voltage offset (VEMF) and
Measurement with Positive Polarity
Measurement with Negative Polarity
VEMF
VEMF VM+
I
VM–
I
R
R
VM+ = VEMF +IR VM =
VM– = VEMF –IR VM+ – VM– = IR 2
Figure 8: Canceling thermoelectric EMFs with current reversal
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a linearly changing voltage offset (_δ V). The thermal voltage drift may be approximated as a linear function over short periods, so the rate of change of voltage as a function of time (δ V) can also be treated as a constant. The first three voltage measurements include the following voltages:
VM1 = V1 + VEMF VM2 = V2 + VEMF + dV VM3 = V3 + VEMF + 2dV
Cancellation of both the thermoelectric voltage offset (VEMF) term and the thermoelectric voltage change (δVI) V term is possible through mathematical computation using three voltage measurements. First, take one-half the difference of the first two voltage measurements and call this term VA. Then, take one-half the difference of the second (VM2) and third (VM3) voltage measurements and call this term VB. Both VA and VB are affected by the drift in the thermoelectric EMF, but the effect on VA and VB is equal and opposite. The final voltage reading is the average of VA and VB and is calculated as:
VFinal =
Figure 9: Eq. 2
where: VM1 , VM2 , and VM3 are voltage measurements
V A – VB V1 + V3 – 2V2 = 2 4
Figure 11: Eq. 3
VM1 is presumed to be taken at time = 0
Notice that both the VEMF and δ V terms are canceled out of the final voltage calculation.
V1, V2, and V3 are the voltage drop of the DUT due to the applied current
In the delta method, each data point is the moving average of three voltage readings. This additional averaging of the voltage measurements means that the data resulting from the delta method has lower noise than the data derived when the current-reversal method
VEMF is the constant thermoelectric voltage offset at the time the VM1 measurement is taken
δ V is the thermoelectric voltage change
VM1 VM1
dV = linearly
DUT Voltage
changing thermoelectric voltages
VEMF VM1
Test Current Time Figure 10: Canceling thermoelectric EMFs with delta method
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EEWeb | Electrical Engineering Community
is used to calculate it, even when both sets of data are taken over the same time period. The success of the delta method depends on the linear approximation of the thermal drift, which must be viewed over a short period. Compensating for changing thermoelectric voltages successfully dictates that the measurement cycle time must be faster than the thermal time constant of the DUT. Therefore, an appropriately fast current source and voltmeter must be used for the delta method to be successful. Figure 12 shows a delta mode test configuration that employs the Model 2182A Nanovoltmeter with the Model 6221 AC+DC Current Source. Another offset-canceling method used by microohmmeters and many DMMs is the offset-compensated ohms method. This method is similar to the currentreversal method except that the measurements are alternated between a fixed source current and zero current. Device heating can be a consideration when making resistance measurements on temperature-sensitive devices such as nano-wires or highly conductive smallscale wires. The test currents used for low resistance measurements are often much higher than the currents used for high resistance measurements, so power dissipation in the device can be a consideration if it is high enough to cause the device’s resistance value to change.
TECH ARTICLE
the lowest current possible while still maintaining the desired voltage across the device being tested. If the current cannot be reduced, use a narrow current pulse and a fast responding voltmeter. Most micro-ohmmeters and DMMs don’t provide the functionality for setting the test current—it is generally determined by the range. In those cases, alternate means must be found to minimize device heating. One simple but effective way to do so is to use the instrument’s one-shot trigger mode during measurements. While in this mode, the instrument will apply only a single, brief current pulse to the DUT during the measurement. In the final installment of this article, I will address making measurements from mega-ohms to tera-ohms.
About the Author Jonathan Tucker is a Senior Marketer and Product Manager for Keithley Instruments in Cleveland, Ohio, which is part of the Tektronix test and measurement portfolio. He is responsible for business development of Keithley’s research and education business with emphasis in the areas of nanotechnology, semiconductor, energy, printable/organic electronics, and electrochem. He is also product manager for Keithley’s sensitive measurement instruments. He joined Keithley Instruments in 1987 and has held numerous positions, including test engineer, applications engineer, applications manager, and product marketer.
Recall that the power dissipation in a resistor is given by the formula P = I2R. From this relationship, we see that the power dissipated in the device increases by a factor of four each time the current doubles. Therefore, one way to minimize the effects of device heating is to use
Model 2182A
Model 6221 RS-232 Trigger Link
GPIB or Ethernet
DUT
Figure 12: A delta mode test configuration designed to compensate for changing thermoelectric voltages.
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Get the Datasheet and Order Samples http://www.intersil.com
Low Voltage ORing FET Controller ISL6146
Features
The ISL6146 represents a family of ORing MOSFET controllers capable of ORing voltages from 1V to 18V. Together with suitably sized N-channel power MOSFETs, the ISL6146 increases power distribution efficiency when replacing a power ORing diode in high current applications. It provides gate drive voltage for the MOSFET(s) with a fully integrated charge pump.
• ORing Down to 1V and Up to 20V with ISL6146A, ISL6146B, ISL6146D and ISL6146E
The ISL6146 allows users to adjust with external resistor(s) the VOUT - VIN trip point, which adjusts the control sensitivity to system power supply noise. An open drain FAULT pin will indicate if a conditional or FET fault has occurred. The ISL6146A and ISL6146B are optimized for very low voltage operation, down to 1V with an additional independent bias of 3V or greater. The ISL6146C provides a voltage compliant mode of operation down to 3V with programmable Undervoltage Lock Out and Overvoltage Protection threshold levels The ISL6146D and ISL6146E are like the ISL6146A and ISL6146B respectively but do not have conduction state reporting via the fault output. TABLE 1. KEY DIFFERENCES BETWEEN PARTS IN FAMILY PART NUMBER
KEY DIFFERENCES
ISL6146A
Separate BIAS and VIN with Active High Enable
ISL6146B
Separate BIAS and VIN with Active Low Enable
ISL6146C
VIN with OVP/UVLO Inputs
ISL6146D
ISL6146A wo Conduction Monitor & Reporting
ISL6146E
ISL6146B wo Conduction Monitor & Reporting
+
VOLTAGE DC/DC (3V - 20V)
VIN GATE VOUT BIAS ADJ ISL6146B FLT GND
EN
Q2 +
VOLTAGE DC/DC (3V - 20V)
VIN GATE VOUT VOUT BIAS ADJ ISL6146B FLT GND
EN
-
FIGURE 1. TYPICAL APPLICATION
October 5, 2012 FN7667.3
• VIN Hot Swap Transient Protection Rating to +24V • High Speed Comparator Provides Fast <0.3µs Turn-off in Response to Shorts on Sourcing Supply • Fastest Reverse Current Fault Isolation with 6A Turn-off Current • Very Smooth Switching Transition • Internal Charge Pump to Drive N-channel MOSFET • User Programmable VIN - VOUT Vth for Noise Immunity • Open Drain FAULT Output with Delay - Short between any two of the ORing FET Terminals - GATE Voltage and Excessive FET VDS - Power-Good Indicator (ISL6146C) • MSOP and DFN Package Options
Applications • N+1 Industrial and Telecom Power Distribution Systems • Uninterruptable Power Supplies • Low Voltage Processor and Memory • Storage and Datacom Systems
+
Q1
• Programmable Voltage Compliant Operation with ISL6146C
C O M M O N P O W E R
GATE FAST OFF, ~200ns FALL TIME ~70ns FROM 20V TO 12.6V ACROSS 57nF GATE OUTPUT SINKING ~ 6A
B U S +C O M M O N P O W E R B U S
FIGURE 2. ISL6146 GATE HIGH CURRENT PULL-DOWN
Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2011, 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.