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Issue 59 August 14, 2012
Alan Gotcher CEO Xtreme Power
Electrical Engineering Community
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TA B L E O F C O N T E N T S TABLE OF CONTENTS
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Alan Gotcher XTREME POWER Interview with Alan Gotcher - CEO
9
Featured Products The Other “Halting Problem”: Debugging in a Real-time Environment BY DAVE LACEY WITH XMOS
11
The nasty end of programming made easier--a look at what debugging tools are most effective for your system.
For Those About to Clock, We Salute You BY BILLIE JOHNSON WITH ON SEMICONDUCTOR
15
A look into clock tree synthesis relating to hierarchal approaches, low power considerations and new flow recommendations for smaller geometries.
19
RTZ - Return to Zero Comic
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INTERVIEW
FEATURED INTERVIEW
Alan
Gotcher Xtreme Power How did you get into the electrical engineering field? I came out of the University of California system—I was at the Irvine campus—with a PhD in Chemistry and I went to work for a material science company called Raychem. I spent ten years there and became the Chief Technical Officer at Avery Dennison, which is a company based out of Pasadena, California, where I spent fifteen
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years. After that, I went and started my own venture capital firm. One of the firms we invested in was a nanomaterials company, which led me into energy storage and product development in the energy space. I came to Xtreme Power last year and became their Chief Technical Officer; in January of this year, I was promoted to the position of President and CEO.
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INTERVIEW
Part of our growth strategy is to expand geographically; we see terrific opportunity in Asia—in particular, China and India. The other part of our strategy is to develop products that will target needs in the marketplace that are not very well-satisfied by other solutions. our largest product family is the Dynamic Power Resource®. This product is an integrated power management and energy storage system that provides solutions to a variety of market segments including renewable integration (wind power and solar power) onto the grid. The Dynamic Power Resource provides
firming, smoothing and ramp rate control. This removes the variability you get from wind when it pulses and from sun when it’s cloudy. We also provide products that are integrated onto micro-grids. These are typically in areas where the grid is really small, like on an island. What we do there is offer a variety of services to strengthen the grid on that island—whether it is providing power or for instance if they have a transformer go out, we’ll quickly respond with however much power that transformer was providing to the grid as well as provide power quality management. This is a fourquadrant product, which provides the ability to push real and reactive power to the grid, and—if need be—pull it from the grid. Our system sizes vary; our smallest is one megawatt, and the largest product we are fielding right now, which is for Duke Energy, is 36 megawatts. What other types of uses are there for the Dynamic Power Resource? As I said before, the Dynamic Power Resource is an integrated solution consisting of power electronics, and an energy storage device we manufacture called PowerCells™, and power management software that we have developed internally. We combine the power electronics, which control the power and quality of that power with the energy storage device; that’s where the electrons go for the duration of when you’re pushing or storing this energy. We integrate those components with our software, which allows us to do real-time control. We have six sites that are fielded—five of them we monitor continuously and every few
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seconds, we grab data from the site and store it both locally and here in our Texas database. This allows us to control that site remotely and make sure that our customer is getting exactly the service that we’ve offered them. What’s unique about our real-time control is that we can provide power quality management and voltage regulation several times a day. How big are your plants typically? Our plants are remarkably small and compact. A plant that runs in the size of 10 to 35 megawatts would typically be 20,000 to maybe 50,000 square feet, which is around half an acre to just over an acre. What kind of technology do you use for your storage mechanisms? The PowerCell is an advanced lead-acid battery. We picked that intentionally because advanced lead-acid allows you to extract thousands of amps of current very rapidly and allows you to swing up to 30 megawatts of power and push it to the grid. Or, in 30 milliseconds (0.03 seconds), we can go from fullpower out to full-power storage. We really like that storage device and over the next year, you’ll see us introduce additional storage technologies. What are some the advantages of using this type of system? For example, if you look at datacenter services, you are worried about losing your connection to the grid and experiencing the occasional flutter where the voltage
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FEATURED INTERVIEW
Tell us a little bit about Xtreme Power. What kind of products do you sell and what markets are you targeting? Xtreme Power was founded back in 2004, so it’s a young, rapidly growing, venture capital-backed firm that has doubled its sales in the last two years. In terms of products,
INTERVIEW FEATURED INTERVIEW
or frequency varies a bit, which isn’t good for servers. Most of the time, data-centers will have a large group of diesel-powered generators to detect when there’s a change in power going into the data-center and power the grid until regular power is restored. Our system can work hand-in-hand with the dieselpower generator; instead of 30, 40 or 50 of these generators, we can reduce them by at least 50%. This reduces the fuel load to these datacenters and substantially reduces the CO2 emissions caused by diesel-fired electric generators. We are a nice complement to these uninterruptable power supply (UPS) systems, and our technology gives these customers more reliability and allows them to use two different types of technologies to keep these data-centers running.
Figure 1: DRP SolarTAC Container
How would you describe the culture at Xtreme Power? Today, we are located at four sites— two sites in Texas, a manufacturing facility in Oklahoma, and a recently opened office in Beijing, China. I would say the culture at all of our locations is fast-paced with highly skilled employees that are smart and hard-working and, most importantly, I think we are all having a lot of fun. There is a feeling that we may be able to positively impact the power industry in a number of different nations and islands, so it’s a very exciting time.
Figure 2: Xtreme Power System
What are some of the things you look for in hiring engineers? We hire a lot of engineers, but we also hire a lot of people that are experienced in manufacturing,
business development, marketing and sales. The types of employees we are looking for are intelligent people who can speak their mind clearly, and people who are very straightforward with a lot of energy.
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We also value diversity, and with that comes the ability to express different points of views on data and to be issue-focused, so that the decisions we make as a team are well-grounded and well-articulated.
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INTERVIEW
What direction do you see your company headed in the next 5-10 years? We’re a pretty small company right now, but we are rapidly growing. Part of our growth strategy is to expand geographically; we see terrific
opportunity in Asia—in particular, China and India. The other part of our strategy is to develop products that will target needs in the
I would say the culture at all of our locations is fast-paced with highly skilled employees that are smart and hard-working and, most importantly, I think we are all having a lot of fun.
marketplace that are not very wellsatisfied by other solutions. One area that is in our sight is what’s called a digital peaker. Today, when you have a peak load coming off the grid, operators who generate electricity will turn on peaking power plants, which are typically based on natural gas. These plants are large, ranging from 50 megawatts to several hundred megawatts, and they come on for a short period of time, for a few days a year. We see this as an opportunity to bring in our Dynamic Power Resource and size it around 25 to 50 megawatts. So, rather than having one large plant in one spot, what we could do is have multiple plants that are small, quiet and compact with zero emissions in areas that are typically more difficult to develop. We see this as a potentially large market opportunity for Xtreme Power. ■
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FEATURED INTERVIEW
What kinds of patents do you and your company have? At Xtreme Power we are always looking for new, innovative solutions. Our engineers and even our business development people are coming up with ideasthat are unique and create value for our customers. We then look at our IP and decide whether we should patent it or not. Our IP is generally focused on our software and integration, so it allows us to have these fastresponding multi-services that we can layer onto our products to solve customers’ problems.
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The Other “Halting Problem”: Debugging in a Real-Time Environment
Dave Lacey
XMOS - Software Tools Technical Director
1 0 10 L et’s
talk about the nasty end of programming: debugging. The cause of many sleepless nights and lost hair. Everyone has to go through it and the easier it can be made the better.
There are many tools around to help with debugging a system and each helps in a different way. However, across the different tools we can categorize how they help us understand a system.
The majority of time debugging is not spent removing bugs but understanding code behavior. Once you understand why undesirable behavior is happening it is usually relatively easy to fix this behavior.
Tools may vary in scope i.e. what part of the system the tools looks at, and they may also vary in function i.e. what the tool actually does. With regards to scope, there are tools that look at the internal state of our code i.e. the
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TECHNICAL ARTICLE External
State Inspection
Step-by-step debuggers
Logic Analyzer
Instrumentation
Logging, Tracing, Debug LEDs, Print, Statements
Analysis
Memory analyzer
Scope, Logic Analyzer
Figure 1: Debugging tools
state of the processor running the software. Other tools look at the external state of the system e.g. the state of connected hardware or the microprocessor ports. In terms of function, inspection tools let us inspect the state of the system at a particular point in its execution. Instrumentation tools add extra output and tracing to your application to give us more information about what is going on at runtime. Finally, analysis tools try and analyze part of the system as it is running. The table in Figure 1 shows some of the popular tools at our disposal categorized into their scope and function. It may be a large generalization but if we asked a general purpose software engineer what the main debugging tools are, they are likely to say print statements (or logging) and step-by-step debuggers. However, if we asked an embedded engineer they are more likely to say scopes, debug LEDs and logic analyzers. To understand this difference of viewpoint it is worth understanding what happens in an embedded environment when a step-by-step debugger (like GNU GDB) is used.
The embedded system will usually be connected to the PC via a hardware connector. Nowadays this is often a connector that implements a JTAG connection (though this is not necessarily the case). This connection controls execution of the program. When we want to examine the state (by either breaking into the program or hitting a predefined breakpoint) the connection will stop the execution of the program and allow us to look at the state of the software: memory, registers etc. Now we have hit the problem for embedded, real-time development: the execution of the program has stopped, which can be a big problem for a real-time program. All inputs during this suspended state will be missed resulting in, for example, missed packets on incoming bus interfaces. Also, any timers in the code risk getting out of sync with the external world. The upshot is that suspending the processor for many real-time systems means that the system is broken from then on – so we only get one shot at stopping and having a look around. This is not ideal. We are in the same position as the hapless bank robber in the quote at the top of this article – we cannot get the system to freeze and do what we want.
Figure 2
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TECHNICAL ARTICLE
Internal
TECHNICAL ARTICLE when each value is taken, a timestamp is also taken so the values can be related to each other in the time domain.
When it comes to analysis tools, scopes and logic analyzers leave the developer well served in terms of functionality. They provide tools to monitor, relate and analyze signals in the system to really understand what is going on. They also let us analyze events in the time domain.
2. http://www.eeweb.com/blog/paul_clarke/the-mostpowerfully-debugging-tool-ever-the-led
At XMOS we felt there was a gap though: we have sophisticated analysis tools for external parts of the system but only quite crude instrumentation for internal parts (print statements, LEDs). So we developed XScope . This is a system inspired by scopes for the analysis of real-time behavior of external properties but lets us analysis internal state values. The way it works is by the developer adding instrumentation calls to the program to trace the values of variables. At run-time, these calls execute a very low overhead routine to send the values over the high speed interconnect built into our chip. These values get picked up from the interconnect by the debug adapter and sent over USB to a PC. Additionally,
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Once the values reach the PC, they are displayed on screen using a GUI that mimics a scope: This way the user gets all the analysis and time visualization of a scope but for values within the software. We think that XScope is a great addition to the debugger’s armoury. It is part of our free tools offering and you can check it out at http://www.xmos.com.
References 1. http://en.wikipedia.org/wiki/Joint_Test_Action_Group
3. http://www.xmos.com/published/xscope-applicationnote
About the Author Dr David Lacey works as Technical Director of Software Tools at XMOS Ltd. With over ten years of research and development in programming tools and compilation technology he now works on the development tools for XMOS devices. As well as tools development he has worked on application development for parallel and embedded microprocessors including work in areas such as math libraries, networking, financial simulation and audio processing.
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So if using a debugger to stop execution and inspect the state is no good then we are left with instrumentation and analysis as available methods for debugging a running system. In terms of instrumentation it often seems the case that embedded programmers prefer LEDs to print statements (as a recent EEWEB blog article shows for a case in point). The reasons for this are probably that code to flash LEDs takes up less memory than print statements, they are probably easier to setup and the most important point may be that a flashing LED is easy for the developer to relate to the timing of other parts of the system. A print statement will go through a buffering layer before getting to the user so the relationship between the information we are seeing and real-time system events is lost.
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1.8V to 3.3V, Micro-Power, ±15kV ESD, +125°C, Slew Rate Limited, RS-485/RS-422 Transceivers ISL32600E, ISL32601E, ISL32602E, ISL32603E The Intersil ISL32600E, ISL32601E, ISL32602E and Features ISL32603E are ±15kV IEC61000 ESD protected, micro power, wide supply range transceivers for differential communication. The ISL32600E and ISL32601E operate with VCC ≥ 2.7V and have maximum supply currents as low as 100µA with both the transmitter (Tx) and receiver (Rx) enabled. The ISL32602E and ISL32603E operate with supply voltages as low as 1.8V. These transceivers have very low bus currents, so they present less than a “1/8 unit load” to the bus. This allows more than 256 transmitters on the network, without violating the RS-485 specification’s 32 unit load maximum.
• Single 1.8V, 3V, or 3.3V Supply
Rx inputs feature symmetrical switching thresholds, and up to 65mV of hysteresis, to improve noise immunity and to reduce duty cycle distortion in the presence of slow moving input signals. The Rx input common mode range is the full -7V to +12V RS-485 range for supply voltages ≥ 3V.
• Up to 65mV Hysteresis for Improved Noise Immunity
Hot Plug circuitry ensures that the Tx and Rx outputs remain in a high impedance state while the power supply stabilizes.
• -7V to +12V Common Mode Input/Output Voltage Range (VCC ≥ 3V)
This transceiver family utilizes slew rate limited drivers, which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications.
• Half and Full Duplex Pinouts; Three State Rx and Tx Outputs
The ISL32600E and ISL32602E are configured for full duplex (separate Rx input and Tx output pins) applications. The half duplex versions multiplex the Rx inputs and Tx outputs to allow transceivers with output disable functions in 8 Ld packages.
Applications
• Low Supply Currents . . . . . . . ISL32601E, 100µA (Max) @ 3V . . . . . . ISL32603E, 150µA (Max) @ 1.8V - Ultra Low Shutdown Supply Current . . . . . . . . . . . . . . 10nA • IEC61000 ESD Protection on RS-485 I/O Pins . . . . . . ±15kV - Class 3 ESD Levels on all Other Pins . . . . . . . . . >8kV HBM • Symmetrical Switching Thresholds for Less Duty Cycle Distortion • Data Rates from 128kbps to 460kbps • Specified for +125°C Operation • 1/8 Unit Load Allows up to 256 Devices on the Bus
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10m
ISL3172E DYNAMIC (9.6kbps) 1m
25°C, RD = ∞, CD = 50pF
100µ
ICC (A)
ICC (A)
ISL3172E STATIC
ISL3260XE DYNAMIC (9.6kbps)
DYNAMIC (256kbps)
DE = VCC, RE = GND
DYNAMIC (128kbps) 1m
ISL3260XE STATIC STATIC DE = VCC, RE = GND
10µ 2.7
2.8
2.9
3
25°C, RD = ∞, CD = 50pF 3.1
3.2
3.3
3.4
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SUPPLY VOLTAGE (V)
FIGURE 1. ISL32600E AND ISL32601E HAVE A 9.6kbps OPERATING ICC LOWER THAN THE STATIC ICC OF MANY EXISTING 3V TRANSCEIVERS
June 22, 2012 FN7967.0
3.6
100µ 1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
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SUPPLY VOLTAGE (V)
FIGURE 2. ISL32602E AND ISL32603E WITH VCC = 1.8V REDUCE OPERATING ICC BY A FACTOR OF 25 TO 40, COMPARED WITH ICC AT VCC = 3.3V
Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
TECHNICAL ARTICLE
We Salute You Billie Johnson
Physical Design Engineer
ON Semiconductor
Introduction As a quick review, clock signals direct a circuit’s performance in digital design. As they alternate between high and low states, logic will switch on the rising edge, falling edge or both edges in an application. With thousands of instances running off of a given clock domain, it is necessary to insert a tree of buffering to adequately drive the logic. Clock trees have delay, skew, maximum power, and signal integrity requirements that the layout engineer must meet. Before layout, ideal clocks are used for synthesis and timing constraints. The constraints’ clock definitions may appear on top-level pads or pins of a block; on the output of a macro such as a DLL (Delay-locked loop) or PLL (Phase-locked loop); or as a generated clock on a dividing register. These clock definitions may or may not be where the layout engineer needs to define clock roots to attain optimal latencies, balancing skew across various modes of operation.
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TECHNICAL ARTICLE
For Those About to Clock,
TECHNICAL ARTICLE Hierarchical CTS
TECHNICAL ARTICLE
Conventional CTS
B A
C
CLK
Hierarchical Approaches Conventional CTS is executed at the top-level with a topdown methodology that attempts to balance all the flops at one pass. A “bottom-up” approach or hierarchical CTS is becoming increasingly popular due to inherent hierarchy in designs as well as better results attainable with this methodology. Clock trees are inserted at lower levels first and then in subsequent steps moving up toward the top level. The “hierarchical” description encompasses both soft and firm modules within a design. A firm or hardened block, including its clock trees, is built independently from the top-level design and then instantiated at a point later in the top-level implementation. Space is often set aside for it and termed a “black box” region. Engineers may employ this approach to facilitate parallel efforts among different portions of a design, to improve software runtimes, to ensure complete replication for identical logic used more than once, and to better allow for last minute design changes in specific pieces of a design without wreaking havoc on the entire chip. Top level clocks are connected to the individual blocks without being able to see the circuitry inside. Within the Cadence® digital layout tool set, a macro model can be defined for the clock trees of each block representing the min and max trees along with the input capacitance. When the top level is built, the tool knows exactly what lies downstream and will take into account latencies and skews at each block boundary.
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There are cases where a design my not contain a firm block but rather lower-level logic where clocks have been inserted. A macro model can be generated and defined so those trees will remain undisturbed and CTS will go right up to a defined port or pin, again accounting for the delay data downstream to help with its balancing or other directives for synthesis. Accurate macro models are great for clock balancing but engineers can also use them to implement useful skew to meet power requirements, allow for time borrowing or force a desired phase offset for high speed interfaces.
Low Power Considerations As design sizes continue to increase, addressing power dissipation is paramount. There are a host of tactics to tackle a chip’s power during clock insertion and everyone including the front end designer, the layout engineer and library developers should have a hand in it. Previous best practices include applying overly pessimistic timing constraints to build in margin, implementing fast trees with high-drive buffers and ensuring clocks have as little skew as possible. These can all increase the chip’s power dissipation, so industry is doing almost an about face when including power as a CTS variable. Realistic constraints and an assortment of buffer drive strengths in less balanced trees are recommended for lower power. Fortunately, layout software has become more power-aware to accommodate this change in methodology, so clock tree
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TECHNICAL ARTICLE In Enable In
Clk
Clk
Enable
insertion can be aptly directed. The front end designer can also address potential power issues with the clock architecture.
Smaller Geometries
Clock gating is a design technique which reduces dynamic power by disabling the clocks to registers intended to be inactive. Gating logic is added into trees so the sheer magnitude of registers switching states can be reduced thus reducing power dissipation. This isn’t a new concept, but gating is becoming more prevalent across blocks in a given chip. Part of the CTS methodology may now also involve focused handling of the enable signals to specific branches of trees.
Another spectacle in the layout flow that has emerged in sub-90nm technologies is centered acutely on CTS. We’ve been driven by the idea of balancing clocks in an effort to ensure that real or propagated clocks will match the ideal clock values used in pre-layout synthesis. The introduction of Multi-Corner Multi-Mode (MCMM) CTS technology helped minimize intra- and inter-corner skew and insertion delays in a single run by addressing process variations across corners, but many chips ended up with excessive switching power or the preand post-layout timing diverged drastically after clocks were inserted
When gating does not help achieve quite enough power savings, designers are now stitching blocks together with their own separate power domains—either at the same or lower voltages than the heart of the design. Many libraries now include three types of cells to handle separate power domains: an isolation cell, a level shifter, and a level shifting isolation cell.
Power handling strategies were discussed above, but how can the pre- and post-CTS timing discrepancies be addressed? The diagram below illustrates a typical physical design flow for 180nm technologies and larger. Many iterations of CTS have become necessary due to gating, muxing, clock generating registers, complex scan chains, and OCV (on-chip variation).
These cells can function as a regular buffer cell so that clocks can be inserted and purposefully balanced or skewed across domains. A separate enable input can
The Cadence suite of layout tools offers a new technology called Clock Concurrent Optimization (ccopt). I admit. I love a good push-button flow, but like many tools ccopt
Synthesis
Synthesis Ideal Clocks
Floorplanning /Placement
Ideal Clocks Floorplanning /Placement
Optimization
Many iterations due to gating, generators, OCV, multi-corner, multi-mode
CTS
Build balanced clock trees to match ideal and propagated clocks
Clock Concurrent Optimization
Build clocks AND optimize simultaneously
Post-CTS Optimization
Routing Routing
Post-route Optimization
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Propagated Clocks
Propagated Clocks
Post-route Optimization
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TECHNICAL ARTICLE
control the isolation cells so entire domains can be off or on depending on desired operation. A level shifter cell does exactly as its name implies shifting signal voltages up or down appropriately, and the third in that list can perform both functions.
TECHNICAL ARTICLE
The ccopt software handles clock gating on top of what the design may already contain, cloning, decloning, and intelligently moving gates. It also adheres to multiple corners and operation modes and can implement on-thefly useful skew for timing and power goals. It’s becoming easier to break two things while fixing one in the deeper sub-micron design world, so the key word “concurrent” in this tool is notable and necessary.
Conclusion Any engineering endeavor is a juggling act. Clock tree synthesis juggles timing across modes and corners, chip architecture, power, signal integrity, and on-chip variation. Manufacturability and time-to-market also force designers to shoot for more than just effective clock trees but ones that will rock.
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References Teng, Chin-Chi and Wei-Jin Dai. “Clock Tree Synthesis For a Hierarchically Partitioned IC Layout.” U.S. Patent 6,751,786, issued June 15, 2004. Paul Cunningham and Steev Wilcox, “Clock Concurrent Optimization: Rethinking Timing Optimization to Target Clocks an Logic at the Same Time”
About the Author Billie Johnson is a Physical Design Engineer at ON Semiconductor. Her work experience spans test, design, technical marketing and layout, and she holds a B.S. in Engineering and an MBA from Idaho State University in Pocatello, Idaho. She has participated in numerous K-12 math and engineering outreach programs throughout her career including MATHCOUNTS ®,FIRST®LEGO® League (FLL®) , Wind for Schools and Introduce a Girl to Engineering Day.
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TECHNICAL ARTICLE
requires a foundation of knowledge about the design’s clock structure, modes of operation, power requirements and how the ccopt engine will incorporate all of them. The following diagram illustrates the advanced layout flow which combines CTS and the subsequent optimization into one step.
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