TECH SERIES
T
he trend for electronics is to continually push towards miniaturization while increasing
performance. With silicon MOSFET technology fast approaching its theoretical limit [1], enhancement mode gallium nitride (eGaNÂŽ) FETs
from EPC have emerged to offer a step change improvement in power FET switching performance, enabling nextgeneration power density possibilities by decreasing size and boosting efficiency. This article will explore the recommended layout techniques required to fully extract the benefits of EPC’s eGaN FETs.
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